JPH03102846A - Pattern defect detection method - Google Patents

Abstract

PURPOSE:To effect pattern defect detection while automatically switching 2-cell comparison and 2-chip comparison without specifying coordinates by selecting a comparison image pattern related to the degree of the maximum matching and by performing pattern defect detection between a reference image pattern and a detection image pattern. CONSTITUTION:A comparison image pattern from comparison image take-out means 3 and 4 is compared with a reference image pattern or a detection image pattern in terms of matching by a 2-cell matching comparison means 1-2 and a 2-chip matching comparison means 1-6, respectively and the degree of matching is output as a result of matching comparison. Being based on this degree of matching, a comparison system related to the greatest matching is selected from the degree of matching by a 2-chip/2-cell switching means 1-7 and pattern defect detection is performed by making comparison of the comparison image pattern by this comparison method with the reference image pattern or the detection image pattern by a pattern defect detection means 1-8 through an image selection means 1-10.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for comparing and detecting defects in patterns of, for example, LSIs and TPTs, and in particular, the method involves specifying in advance the coordinates of two cells that can be compared. 2 in the section where 2 cells can be compared instead.
The present invention relates to a pattern defect detection method in which 2-chip comparison is automatically selected in areas where 2-cell comparison is not possible, and pattern defects are comparatively detected.

[Conventional Techniques] Previous methods for this type of technology include the paper F Computer Controlled Imaging System for Automatic Hybrid Inspection (Solid State Technology/October 1980).
Computer Control-led Imag
ing System for Automatic
Hybrid Insp-ection (Solid
State Technology/October
1980)) is known. In this case, each time a pattern is detected, the detected pattern is temporarily stored, and the detected pattern is compared with the pattern stored immediately before, thereby detecting defects in the pattern. It looks like this. To explain in more detail, the pattern detection target is a pattern on a semiconductor wafer such as a memory LSI, or a TPT.
(Thin Film Transistor) patterns, patterns on printed wiring boards, patterns on ceramic substrates, and patterns of masks, reticles, etc. used in the process of manufacturing them. Here, a semiconductor wafer pattern will be explained as an example, but the situation is similar for other patterns as well.

Now, the pattern as a chip unit on a semiconductor wafer is eventually separated and obtained as individual chips, but before being separated, dozens of chips as individual products are mounted on a single wafer. It has become something like this. The pattern of each chip is assumed to be the same pattern, but each pattern as a chip unit also has a pattern part where the same pattern is repeated at a constant period, such as a memory cell part, and a pattern repeating period, such as a peripheral circuit. This has become a problem because of the pattern parts that have poor quality.

Here, the principle of the pattern defect detection method that has been used up to now will be explained below with reference to FIG. 7 for chip patterns.

That is, each chip has exactly the same pattern, and
Focusing on the fact that patterns corresponding to cells are repeated at regular intervals inside a chip, we can detect a pattern for a certain chip, store it, and then find a pattern for other chips that should be the same as this pattern. When detected, a pattern defect is detected by comparing it with a stored pattern. Figure 7 (a), (b). (c) shows the memory pattern, the detection pattern, and the pattern difference (difference as a comparison result), respectively, but if there is no defect in either the memory pattern or the detection pattern, almost no pattern difference will occur. ing. However, if a defect exists in any of these patterns, a pattern difference will occur at the defective part, so the pattern defect can be detected by detecting the part where the pattern difference occurs during pattern comparison. This is how it is. At that time, if a pattern difference occurs, it can be determined that a defect exists in one of the patterns, but it is impossible to determine which pattern has a defect (
Various methods are actually known for making this determination possible, but their explanation will be omitted here.)

In the above, patterns are compared with other chips (hereinafter, this comparison method is referred to as the two-chip comparison method), but pattern comparisons can also be made with respect to cell patterns within the same chip. (Hereinafter, such a comparison method will be referred to as a 2-cell comparison method). Even if concepts such as chips and cells do not exist, the pattern on the wafer can be expressed as a general concept as a part with the same pattern as a whole or a part with pattern repeatability at a certain period. It has become relatively easy to apply such a comparison method not only to general patterns but also to general patterns.

By the way, since the two-cell comparison method generally has a smaller error in the normal part than the two-chip comparison method, it is easier to distinguish between the defective pattern part and the normal pattern part. Figure 8 (
8(a) shows the pattern detection signal waveform on a certain pattern detection line, and FIGS. Figures (d) and (e) show the two-cell comparison time difference waveform and the two-chip comparison time difference waveform, respectively. As can be seen, the signal level of the difference waveform in the normal pattern area appears small when comparing the two cells. , appears larger when comparing two chips. This is because in two-cell comparison, patterns are compared within the same chip and at close positions, so various error factors in the normal pattern area are small, and as a result, the signal level of the difference waveform in the normal pattern area is appears small when comparing two cells, but appears large when comparing two chips. On the other hand, the signal level of the difference waveform at the pattern defect portion is considered to be almost the same when comparing two cells and when comparing two chips. Therefore, when a normal pattern part and a defective pattern part are discriminated by binarizing the signal level of the difference waveform, the threshold margin ΔV for discrimination is smaller when comparing two cells than when comparing two chips. This is why it is easier to distinguish between defective pattern areas and normal pattern areas in the 2-cell comparison method than in the 2-chip comparison method.

[Problems to be Solved by the Invention] Until now, for example, in order to detect pattern defects on a wafer, defects have been detected on the entire wafer using only a two-chip comparison method, or two-cell comparison is possible. By specifying the coordinates of the portion, pattern defects are detected by the 2-cell comparison method in the 2-cell comparison possible portion, and by the 2-chip comparison method in the 2-cell comparison impossible portion. Incidentally, the 2-cell comparison portion referred to herein refers to a pattern portion in which memory cells are periodically arranged at a predetermined pitch within the chip, and a 2-cell comparison portion.
The non-cell comparison area refers to a pattern area other than the 2-cell comparison area within the chip, more specifically, a peripheral circuit that lacks periodicity due to the pattern arrangement, and pattern defects can only be detected using the 2-chip comparison method. It is defined as a pattern part that is possible.

Until now, pattern defects have been detected in the manner described above, but each method has its own problems. This is because in the former method, pattern defects are detected in the two-chip comparison method even in the 2-cell comparison area, so the threshold margin in the 2-cell comparison area becomes much smaller. be. In addition, in the latter method, two
Preprocessing such as specifying the coordinates of the cell-comparable portion in advance is now required.

An object of the present invention is to provide a pattern defect detection method that can detect pattern defects while automatically switching between 2-cell comparison and 2-chip comparison without specifying coordinates.

[Means for Solving the Problem] The above purpose is to perform 2-cell comparisons using a reference image or a detected image as a plurality of comparison images, regardless of whether the 2-cell comparison is possible or the 2-cell comparison is not possible. A pattern matching comparison is simultaneously performed between the image obtained with the coordinates when comparing two chips, and the image obtained with the coordinates when comparing two chips, and among these comparison results, the image with the highest degree of matching is selected. This is achieved by selecting a pattern defect and performing pattern defect detection between this image and a reference image or a detected image.

[Effect]. The reference image pattern or the detected image pattern and each of the plural comparison image patterns are simultaneously subjected to pattern matching comparison, and based on these pattern matching comparison results, one of the comparison image patterns, more specifically, the one with the highest degree of matching is selected. In addition to selecting such a comparative image pattern, pattern defect detection is performed between it and the reference image pattern or the detected image pattern.

At that time, the plurality of comparison image patterns are a plurality of coordinate patterns to be compared between two chips and a plurality of coordinate patterns to be compared between two cells, and the plurality of coordinate patterns to be compared between two chips are the coordinates of the pattern. The difference between the coordinates of the reference image or detected image is an integral multiple of the chip pitch, and the pattern of coordinates to be compared between two or more cells is such that the difference between the coordinates of that pattern and the coordinates of the reference image or detected image is the cell pitch. A matching comparison is performed between the reference image pattern or the detected image pattern while the pattern is set to an integer multiple of .

As a result of the above, 2-cell comparison is automatically selected in the 2-cell comparison possible portion, and 2-chip comparison is automatically selected in the 2-cell comparison impossible portion. To explain in more detail, in the 2-cell comparison possible part, there is a pattern of coordinates to be compared between 2 cells, and 2 cells can be compared.
There is a pattern of coordinates that should be compared between two chips, but the pattern that allows two cells to be compared has more process errors than the pattern that allows two chips to be compared. The factor is small <, therefore, the reference image,
Alternatively, since the degree of coincidence with the detected image is large, two-cell comparison is selected. On the other hand, in the 2-cell comparison impossible part, there is a pattern in which 2-cell comparison is not possible at all in the coordinate pattern where 2-cell comparison is to be made, and a 2-chip comparison is possible in the coordinate pattern in which 2-chip comparison is to be made. Since a pattern exists, a pattern that can be compared with two chips has a higher degree of coincidence with a pattern of a reference image or a detected image, and two-chip comparison is selected.

[Example] The present invention will be explained below with reference to FIGS. 1 to 6.

First, a pattern defect detection apparatus according to the principle of the present invention will be explained. FIG. 1 shows the schematic structure thereof. In this case, the pattern on the wafer/X1-9 is detected in advance by the pattern detection means 1-1, and after being stored in the storage means 1-2,
-1 allows the pattern on wafer/X1-9 to be detected as a reference image pattern or a detected image pattern.

In synchronization with this pattern detection, comparison image extraction means 1-
3, from the storage means 1-2, the reference image pattern or the coordinates of the detected image pattern and the coordinates to be compared in the 2-cell comparison area are retrieved from the pre-stored pattern at all locations. It looks like this. In the same way, from the storage means 1-2, the reference image pattern or the detected image pattern is extracted from the pre-stored pattern by the comparison image retrieval means 1-4 at all locations. The pattern of coordinates to be compared is extracted in the comparison section).

The comparison image outputs from the comparison image extraction means 3.4 are matched and compared with the reference image pattern or the detected image pattern by the 2-cell matching comparison means 1-5 and the 2-chip matching comparison means 1-6, respectively, and the matching comparison results are obtained. The degree of matching is output as .

Based on these degrees of coincidence, 2-chip/2-cell switching means 1-
In step 7, the comparison method with the highest degree of coincidence is selected from among these degrees of coincidence, and the comparison image pattern according to this comparison method is sent to the pattern defect detection means 1-8 via the image selection means l-10, and is then selected as the reference image pattern or Pattern defects are detected by comparing with the detected image pattern. Incidentally, the comparison image pattern for pattern defect detection 1,000 steps 1-8, the reference image pattern,
Alternatively, while the pattern matching comparison is being performed, the detected image pattern is temporarily stored in a delay means and then given to the pattern defect detection means 1-8, but these delay means are not shown in FIG. has been done.

This situation is similar in other figures as well.

Now, FIG. 2 shows the pattern defect detection apparatus according to the present invention in more detail. In this example, an LSI wafer pattern inspection apparatus is assumed, and therefore, the pattern is a pattern on a wafer, but it is of course applicable to patterns such as TPT.

In this case, the entire structure includes a pattern detection section 2-3, an image input section 2-2, an image processing section 2-4, and an overall control section 2-1.
The overall control unit 2-1 controls the XY stage and stores and stores defect information from the image processing unit 2-4.
Display and overall sequence management are performed. To explain the operation here, after each part is initialized by a command from the overall control part 2-1, the wafer 2-1 placed on the XY stage 2-3-1
3-2 shows the two-dimensional pattern in synchronization with the scanning by the XY stage 2-3-1 in a state where the illumination light from the illumination unit 2-3-4 is illuminated through the illumination lens 2-3-5 etc. passes through the objective lens 2-3-6 to the one-dimensional image sensor 2-
It is detected in 3-3.

The pattern detection signal detected by being sequentially photoelectrically converted by the one-dimensional image sensor 2-3-3 is digitized by the A/D converter 2-2-1 in the image processing unit 2-2, and then converted into an image. By sequentially storing the two-dimensional pattern in the memory section 2-2-2, the two-dimensional pattern is stored in the image memory 2-2-2.
2 in the order of predetermined addresses. After this,
The two-dimensional turn of the wafer 2-3-2 is detected again with the contents of the image memory 2-2-2 already stored, but the pattern detection signal in this case is now used as a reference image signal. ing.

At the same time, after reading out the comparison signal from the image memory,
It is assumed that the image memory is rewritten with the detection signal in preparation for the next chip comparison. In synchronization with this reference image signal, the 2-chip image extraction unit 2-4-1 and the 2-cell image extraction unit 2-
4-2, a 2-chi/knob comparison image and a 2-cell comparison image are taken out for each.

Now, to explain the 2-chip image extraction section 2-4-1, FIG.
Focusing on the fact that the difference between the coordinates to be compared with the chips and the reference image is equal to the pitch of the chips, the function is to take out the image for comparison of two chips by referring to a certain address in the image memory section 2-2-2. It has become something to do. Also, to explain the 2-cell image extraction unit 2-4-2, FIG. 3(b) shows an enlarged state of the circled part shown in FIG. 3(a). Part 2-4-
2, the image memory unit 2-2-2 focuses on the fact that the difference between the coordinates to be compared with the two cells and the reference image is equal to the cell pitch.
The function is to extract a two-cell comparison image by referring to a certain address within the cell.

Now, the reference image, the 2-chip comparison image, and the 2-cell comparison image are matched and compared in the 2-chip matching comparison unit 2-4-3 and the 2-cell matching comparison unit 2-4-4, respectively. How the two-chip matching comparison is performed will now be explained as shown in FIG. As shown in Figure 4, the reference image (detection image) and the
From the image for chip comparison, the image for comparison of two chips is ΔX,
Allowable positional deviation in the ΔY direction ±δ pixels (in this example, δ = 1 is assumed, but this value is generally determined by the dimensional accuracy of the detection target and the positioning accuracy of the defect detection device, and can be set to an appropriate value as necessary) The difference between these images is calculated using equation (1) when the images are shifted by .

Sl(Δi,Δj)=ΣΣl f(i,j)−gl(
i+Δi, j+Δj)1... (1) However,
f(i,j) is the value at pixel (i.j) of the reference image,
g 1 (i, j) is the pixel (i, j
), S1 (Δi.Δj) is the image shift amount (Δ
i, Δj). Also, ΣΣ represents the addition over the entire image area where the positional shift is calculated, Δi,
Δj also takes a value from −1 to +1.

The 2-cell matching comparison unit 2-4-4 also performs the same operation as above, and the 2-cell comparison image is shifted in the ΔX and ΔY directions by an allowable amount of ±δ pixels with respect to the reference image. The difference between those images when shifted by
1), and the image difference S2 corresponding to each shift amount is obtained as the degree of coincidence (matching value).

S2(Δi, Δj)=ΣΣ1 t(i,j)−g2(
i+Δi, j+ΔJ)1...(2) However, f(
i. j) is the value at pixel (i, j) of the reference image, g2
(i, j) is the value at pixel (i, j) of the 2-cell comparison image, and Sl (Δi, Δj) is the image shift amount (Δi, Δj
) is the difference between the images. Further, ΣΣ is an addition over the entire image area in which the positional shift is calculated, and Δi and Δj also take values from −1 to +1.

In the 2-chip/2-cell selection section 2-4-5, the matching degree is 3.
1. By searching for the minimum value from S2, the comparison method related to this minimum value is selected as the one with the highest degree of coincidence, and the amount of positional deviation in the case where the minimum value is obtained is determined. It looks like this. To explain in more detail, the minimum value is found among the matching degrees SL and S2 for each shift amount. If required, the two-cell comparison method is selected. In addition, the amount of image shift or the amount of positional shift (Δi, Δj) when the minimum value is obtained is also determined. From the 2-chip/2-cell selection section Z-4-5,
Depending on the selected comparison method, the image selection section 2-4-6 selects a comparison image related to that comparison method, and the image alignment section 2-4- selects this comparison image.
7, from the 2-chip/2-cell selection section 2-4-5,
After the position is corrected based on the amount of positional deviation, the difference image extraction unit 2-4-8 extracts the difference image from the reference image using the formula (3).
It is designed to be extracted by.

S (i, j)= I f (i, j) 1g3(i,
j) l・・・・・・・・・(3) However, f (i, j
) is the value at pixel (i, j) of the reference image, g3 (i, j)
is the value at pixel (i.j) of the position-corrected comparative image, S
(ij) indicates the value at pixel (i, j) of the difference image.

The defect determination unit 2-4-9 binarizes the value of S (i, j) using the threshold value vlh for defect determination, and calculates the area, width, projected length, etc. where there is a difference. Various specials? 1
1f! The presence or absence of a defect is determined by extracting k. In this way, if a comparison image is selected to be compared with the reference image while allowing positional deviation, pattern defects can be detected even if the positioning accuracy is not good.

Although the outline of the operation of the pattern defect detection apparatus according to the present invention has been described above, the present invention is not limited thereto and various modified embodiments are possible. For example, when detecting a two-dimensional pattern on a wafer, any type of sensor can be used, such as detecting the two-dimensional pattern with a TV camera while moving the XY stage step by step, or using a point-type sensor such as a photomultiplier and a scanning mechanism. It has become.

In addition, the image difference between the reference image and the comparison image is calculated using equation (1).
, (2), and instead of obtaining the difference between images corresponding to each shift amount as a matching value, edges are extracted by filtering each of the reference image and comparison image, and the edge image is The difference is expressed as (1)
, (2), and obtain the difference between images corresponding to each shift amount as a matching value, or filter and binarize each of the reference image and comparison image, and create an edge binarized image obtained by this. The difference between the images is calculated using equation (1). It is also possible to calculate by (2) and obtain the difference between images corresponding to each shift amount as a matching value. When a matching value is obtained based on edges, it is less likely to be affected by differences in pattern brightness between the reference image and the comparison image.

Even if the amount of pattern detection light changes, the edge position as a pattern boundary does not change. Therefore, by comparing the edge positions, a matching value can be obtained without being affected by the change in the amount of detected light.

Furthermore, if two-cell comparison or two-chip comparison is performed, the comparison target can be prepared for multiple coordinates instead of just one coordinate, and the reference image and all the comparison targets can be compared. The smallest matching value will be selected. In other words, when a reference image is compared with multiple comparison images, even if one comparison image has a major defect, all other comparison images will also have defects. The probability that this is the case is extremely small, and therefore it is possible to select the correct comparison method.

Furthermore, in the 2-cell image retrieval unit, we focused on the fact that the difference between the coordinates to be compared with the 2-cells and the reference image is equal to an integral multiple of the cell pitch, so we set a fixed address in the image memory unit that is an integral multiple of the cell pitch. If two-cell comparison images are extracted with reference to Image comparison will be performed without being affected by sampling errors. For example, if we assume that the cell pitch is 5 μm and the pixel size is 0.3 μm, the difference in the number of pixels compared to adjacent cells is 16.67 (= 5 μm, 70.3 μm
), so it is not an integer. Therefore, it will be compared with the 17th pixel, which is 0.3
This results in a shift of three pixels. On the other hand, if we compare this with the third cell, the difference in the number of pixels is 50 (=5μm×3
If the 50th pixel is multiplied by an integer such as 70.3 μm), the comparison can be made without any deviation smaller than the pixel size.

In addition to the above, when setting various parameters given to the difference image extraction section and defect determination section to optimal values according to the comparison method selected by the 2-chip/2-cell selection section, the 2-cell comparison section Since the threshold value for defect determination can be set smaller than the two-cell non-comparable part,
This means that finer defects can be detected.

Finally, another example of a pattern defect detection apparatus will be described. FIG. 5 shows the configuration thereof. What is substantially different from Fig. 2 is that the reference image is taken out from the image memory section, and multiple 2-cell comparison images are taken out, and each is compared with the reference image in the 2-cell matching comparison section. This is what is now being done.

That is, the two-dimensional pattern of wafer/X2-3-2 is stored in the image memory section 2-2-2 in the same way as in the case of FIG. The difference in the case of FIG. 2 is that it is extracted from 2.

In the reference image extraction section 2-4-12, the image memory section 2-
The reference image is retrieved by referring to a fixed address in 2-2. This reference image is matched with the 2-chip comparison image and the 2-cell comparison image by the 2-chip matching comparison unit 2-4-3 and the 2-cell matching comparison unit 2-4-4 in the same way as in the case of FIG. However, in this example, the 2-cell comparison images have different coordinate positions and are also extracted by the 2-cell image extraction unit 2-4-10, and the extracted 2-cell comparison images are A matching comparison is made between the reference image and the 2-cell matching comparison section 2-4-11.

In this example, to simplify the explanation, two cell comparison images are
Although one is taken out, there is no limitation to this, and generally two or more can be taken out. 2 chips/
In the 2-cell selection section 2-4-5, in the same manner as in the case of FIG. By searching for the minimum value from the matching degree corresponding to each shift amount, the comparison method related to this is selected with the minimum value as the one with the highest matching degree, and if the minimum value can be obtained. The amount of positional deviation can be determined. The operation other than this is the same as in the case of Fig. 2, but the characteristic part of this example is that a plurality of 2-cell comparison images are extracted and each is matched and compared with the reference image. Cell comparison images can also be set on both sides of the reference image. When set in this way, as shown in FIG. 6, even if the reference image exists near the 2-cell comparison impossible part,
Since any of the cell comparison images exists within the 2-cell comparison possible area, the possibility of 2-cell comparison increases accordingly. Note that in the above description, the number of two-chip comparison images is one, but the number of images can generally be set to a plurality of images.

[Effects of the Invention] As explained above, according to the present invention, pattern defects can be detected while automatically switching between 2-cell comparison and 2-chip comparison without specifying coordinates. It is no longer necessary to specify the coordinates of the two-cell comparable portion to be set. Further, since 2-cell comparison and 2-chip comparison are performed in the 2-cell comparison possible portion and the 2-cell non-comparable portion, respectively, pattern defect detection can be performed using an optimal defect determination threshold value.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a schematic configuration of a pattern defect detection device according to the principle of the method of the present invention, and FIGS. Figure 3(a) is a diagram showing a perspective view of the wafer;
b) is an enlarged view of the circled portion shown in FIG. 3(a), and FIG. 4 is for explaining the matching comparison process in the 2-cell, 2-chip matching comparison section shown in FIG. 2. Figure 6 is a diagram for explaining the possibility of 2-cell comparison when 2-cell comparison images are set on both sides of the reference image, and Figure 7 (a), (b), ( c) is a diagram showing a memory pattern, a detection pattern, and a difference between these patterns (difference as a comparison result) for explaining a pattern defect detection method according to the prior art, and FIGS. 8(a) to (e) are ,
FIG. 4 is a diagram for explaining the difference in normal part errors between the 2-cell comparison method and the 2-chip comparison method. 1-1... Pattern detection means, 1-2... Storage means, 1-3.1-4... Comparison image retrieval means, 1-5
...2 cell matching comparison means, 1-6...2 chip matching comparison means, 1-7-.・2 chip/2 cell switching means, 1-8...pattern defect detection means, 1-9
...Wafer, 1-10...Image selection means

Claims (1)

[Claims] 1. The detected pattern is stored, and a reference image pattern and a plurality of comparison image patterns are simultaneously extracted from among the stored patterns and delayed; Each comparison image pattern is compared by pattern matching while allowing image position shift, and based on the degree of matching as a pattern matching comparison result obtained for each comparison image pattern, one of the delayed comparison image patterns is selected. 1. A pattern defect detection method, characterized in that pattern defect detection is performed between a reference image pattern that is selected, positional deviation corrected, and delayed. 2. The pattern defect detection method according to claim 1, wherein a plurality of coordinate patterns to be compared between two chips and a plurality of coordinate patterns to be compared between two cells are extracted as the plurality of comparison image patterns. 3. When any one of the delayed comparison image patterns is selected, a comparison is made based on the highest degree of agreement among the degrees of agreement obtained as pattern matching comparison results corresponding to the comparison image patterns. 3. The pattern defect detection method according to claim 1, wherein an image pattern is selected. 4. The pattern of coordinates to be compared between multiple 2 chips is such that the difference between the coordinates of the pattern and the coordinates of the reference image is an integral multiple of the chip pitch, and the pattern of coordinates to be compared between multiple 2 cells is the coordinates of the pattern. and the coordinates of the reference image are each taken out as an integer multiple of the cell pitch,
3. The pattern defect detection method according to any one of 3. 5. When pattern defect detection is performed between a comparison image pattern and a reference image pattern, the presence or absence of a defect is determined using a defect determination threshold according to a comparison method related to the comparison image pattern. 5. The pattern defect detection method according to any one of 1 to 4.