JPH03102638A - Relative address demodulation circuit - Google Patents

Abstract

PURPOSE:To demodulate a relative address with simple constitution by selecting an address with the comparison of quantity of sensor signals in wobble pits. CONSTITUTION:A relative address of an optical disk with tracking wobble pits provided thereon intermittently and a relative address formed in the tracking direction in a periodic gray code are demodulated. After the binarization of reproduction signal by the wobble pit a flag generating circuit 5 generating a flag corresponding to the relative address and a discrimination circuit 6 discriminating the quantity of a change in the reproduction signal due to the wobble pit are provided. A demodulation address is selected according to the output of the discrimination circuit 6 and the flag to demodulate the relative address with simple constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a relative address demodulation circuit for an optical disc on which a relative address pattern in the form of a Gray code is periodically recorded. [Prior Art 1] There are several known track counting methods that have been used to perform high-speed seeks on optical discs. As an example, a method using relative addresses in the form of a Gray code will be explained using FIG. FIG. 5 is a diagram showing a servo area in a sample servo type optical disc. Although not shown on this disk, one track includes 1672 servo areas, and each servo error signal for autofocus and autotracking is generated by sampling and holding the signals within the servo area. obtained by. In FIG. 5, 31a and 3lb are tracking wobble pits, which sample and hold changes in the amount of light from an optical head (not shown) at the timing of two wobble bits, and use the difference between the two as a tracking error signal. In addition, the focus error signal is obtained by sample-holding a signal obtained from an optical system similar to the known astigmatism method or knife-edge method on the mirror surface between the wobble pit 3lb and the gray code region 33 in FIG. and use it. In the gray code area 33, a pattern in which 2 bits out of 10 address bits are "1" (0 display area in the figure) and 8 bits are "O" as shown in FIG. 5 is recorded at 18 track cycles. ing. Furthermore, the position of "l" in adjacent tracks changes by only one bit. During seek, the number of tracks to be traversed is calculated by reproducing this relative address, and the target track is sought. Therefore, during the seek,
That is, even in the case of off-track, accurate demodulation of relative addresses is required. A conventional relative address demodulation circuit will be explained using FIGS. 6 and 7. FIG. 6 is a block diagram of a conventional relative address demodulation circuit. In FIG. 6, 1 is an optical head for reproducing information from an optical disc (not shown), 2 is a sensor amplifier, and 40 is an A
A D converter, 41a to 41j are memories, 42 is a converter, and 43 is a demodulation circuit. FIG. 7(a) is a diagram showing an example of the servo pattern shown in FIG.
When the information reproducing light beam of the optical head 1 passes through the position A in FIG. 7(a), the output of the sensor amplifier 2 is as shown in FIG. 7(a).
The signal waveform will be as shown in b). That is, the degree of modulation is large for bits where the light beam passing position is close to the bit center, and the degree of modulation is small when the light beam passing position is far from the center. The position of A in Figure 7(a) is
Since it is between the track with the relative address "l" and the track with the relative address "2", the gray code area is affected by both tracks, and the sensor amplifier 2 output has three peaks as shown in Figure 7(b). appear. Further, when passing through the position B in FIG. 7(a), the output of the sensor amplifier 2 as shown in FIG. 7(c) is similarly obtained. Conventionally, a method called difference detection was used to distinguish between Figures 7(b) and (c). This method is shown in Figure 7(d).
The output of the sensor amplifier in the Gray code area is AD converted in accordance with the clock shown in FIG. The two largest bits compared are input to the demodulation circuit 43 as "1",
This method performs demodulation. According to this method, even when a light beam passes between two tracks, it is possible to select the track with the greater bit influence, so that the relative address "l" in FIG. 7(b) is , FIG. 7(C) can be demodulated as relative address "2". Another method is to compare the data with the previous data every time 1 bit is AD converted. In this case, a configuration with a reduced number of memories can be used. [Problems to be Solved by the Invention] However, in the conventional example described above, the number of memories 41a to 41j that is the same as the number of bits of the Gray code is required, and the compare is also complicated in that the two largest pieces of data are selected from 10 pieces of data. The problem was that a specific configuration was required. Another method is to compare the previous data every time 1 bit is AD converted, which can reduce the number of memories, but requires a very high-speed arithmetic circuit. There was a problem that the configuration was complicated. [Means and effects for solving the problem] According to the present invention, it is possible to demodulate the relative addresses of an optical disk in which relative addresses configured in a periodic Gray code shape in the tracking direction and wobble pits for tracking are provided intermittently. In the relative address demodulation circuit that performs
A flag generation circuit that generates a flag corresponding to the relative address, and a determination circuit that determines the magnitude of change in the reproduced signal due to the wobble pit, and selects a demodulation address according to the output of the determination circuit and the flag. By doing so, it is possible to demodulate relative addresses with a simple configuration. [Example] (First Example) A first example of the present invention will be described in detail using the block diagram of FIG. 1 and FIG. 2. In FIG. 1, members that perform the same functions as those in FIG. 6 described above are given the same numbers, and detailed explanations will be omitted. Also, like FIG. 7, FIG. 2 shows the servo patterns at relative addresses 1 and 2 on the disk and each signal waveform obtained from them. 1, 3 is a binarization circuit A, 4 is a shift register, 5 is a flag generation circuit, 6 is a flag selection circuit, 7 is a decoder, and 8 is a wobble pit A. WA sample and hold circuit of sensor amplifier 2 output (hereinafter sometimes referred to as WA) at the timing of 3La,
9 is a WB sample and hold circuit for the sensor amplifier output (hereinafter sometimes referred to as WB) at the timing of wobble pit B, 3lb in Fig. 2; 10 is a combo barrette;
11 is a binarization circuit B1, 12 is a PLL, and 13 is a timing generation circuit. The output of the sensor amplifier 2 is output from the binarization circuits A and B (3.1
1) and is input to the WA and WB sample and hold circuits 8.9. When the light beam passes through the positions A and H in Fig. 2(a), the output of the sensor amplifier 2 is as shown in Fig. 2(b).
The waveform will be as shown in (c). The binarization circuit A compares the sensor amplifier 2 output with the level shown by the dashed-dotted lines in FIG. Converts 10 bits of serial data to parallel data. 2(e) and 2(f) are the outputs of the binarization circuit A;3 when the output of the sensor amplifier 2 is as shown in FIGS. 2(b) and 2(c), respectively. In both cases, relative address "1""2"
Under the influence of both tracks, three bits, bits 0, 7, and 80, become "1", as shown in Figure 2 (b) and (c).
cannot be distinguished. However, the flag generation circuit 5 can determine whether the relative address is "1' or "2'". In other words, the flag generation circuit 5 generates the following address according to the relative address bit pattern shown in FIG. A given bit comrade (
It is composed of a logic circuit that outputs 18 flags indicating a relative address by multiplying the bits (bits in the 0 display section in FIG. 5) to produce a result of 1 or 0. Flag 1 = Bit φ x Bit 8 Flag 2 = Bit φ x Bit 7 Flag 18 = Bit φ x Bit 9 Therefore, in the cases of Figure 2 (e) and (f), both flags 1 and 2 are set, so the relative It can be seen that the address is either 'l' or '2'. Next, we will explain how to distinguish between (b) and (c) in Figure 2. Binarization circuit B; ll is combined with PLL12. The dimming generation circuit 13 generates a sample and hold timing signal at the timing of wobble pits A and B based on the clock generated by the PLL 12 as shown in FIG. 2(d). The WA, WB sample and hold circuits 8 and 9 each sample and hold the sensor amplifier output according to the timing signal generated by the timing generation circuit 13. When applying tracking servo, the WA and WB sample and hold circuits 8, The difference between the outputs of 9 is used as a tracking error signal, and in this case, the comparator IO is used.In other words, the comparator 10 outputs "1" or "1" depending on the magnitude relationship of the WA and WB sample and hold circuits.
2 (b) and (c), the binary signals in the Gray code area have the same pattern, but the magnitudes of the output values of the WA sample and hold circuit 8 and the WB sample and hold circuit 9 are different. are different, that is, the output of the comparator 10 is different.Therefore, when the relative address cannot be specified only from the output of the flag generation circuit 5, the flag selection circuit 6 selects the comparator lO
The relative address is identified based on the output of . Next, the operation of the flag selection circuit 6 will be explained in detail using FIG. First, the state of the flag is checked from the output of the flag generation circuit 5 (Sl in FIG. 3). If only one flag is set, it is considered that the light beam has passed close to the on-track, so a relative address is output according to the flag that is set (S7). Next, if there are not two flags set, or even if there are two flags, it is not the address of the adjacent comrade (flag No. of the adjacent comrade), it is considered that a pattern that cannot be played back has occurred due to a defect in the disk, etc. Therefore, an error is output (S8). If there are two flags set and they are adjacent to each other, it is considered that the light beam has passed near the middle of the tracks, so the output of the converter 10 is used to compare the sizes of WA and WB. (S4). As is clear from FIG. 2, when the light beam passes closer to the outer circumference than between the two tracks, WA>WB, and when it passes closer to the inner circumference, WA<WB. Therefore, WA>WB
If so, select the flag on the outer circumference side (S5), and if WA<WB, select the flag on the inner circumference side (S6). According to the above procedure, the decoder 7
By decoding with , the relative address is demodulated. WA, WB sample and hold circuits 8.9 are originally necessary for tracking servo, and flag generation circuit 5
Since the flag selection circuit 6 can be a simple logic circuit, the circuit scale required for relative address demodulation is reduced. As described in detail above, according to the relative address demodulation circuit of the present invention, the structure is significantly simplified compared to the conventional difference detection method, and relative address demodulation can be performed even off-track. Further, the method of the binarization circuit is not limited to the method of this embodiment, and any method similar to that of the binarization circuit B can be used in common. (Second Embodiment) A second embodiment of the present invention will be described using FIG. 4. In FIG. 4, members that perform the same functions as those in FIG. 1 are given the same numbers, and detailed explanations will be omitted. In FIG. 4, 14 is an AD converter, 15 and 16 are data latch circuits for wobble pits A and B, and 17 is a converter. The data obtained by AD converting the output of the sensor amplifier 2 by the AD converter l4 is latched by the WA and WB latch circuits 15 and 16, respectively, according to the timing output of the timing generation circuit 13. The comparator 17 compares the magnitudes of WA and WB from the data of the WA and WB latch circuits l5 and l6, but since it only compares two data, the sixth
It is much simpler in construction than the conventional converter 42 illustrated in the figures. This embodiment is particularly suitable for performing tracking servo by latching the sizes of WA and WB with digital data, and even in this case, the circuit scale for relative address demodulation can be smaller than the conventional one. . [Effects of the Invention] As explained above, when demodulating relative addresses, flags are prepared according to the Gray code pattern, and furthermore, when flags of adjacent addresses are set simultaneously, wobble pits A and B By selecting an address by comparing the magnitude of the sensor signals, the relative address can be demodulated with a simple configuration.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention. FIG. 2 is a signal waveform of the first embodiment of the present invention. FIG. 3 is an explanatory diagram of the operation of the flag selection circuit of the present invention. FIG. 5 is a conventional gray code pattern. FIG. 6 is a conventional relative address demodulation circuit. FIG. 7 is a conventional signal waveform 1...optical head 2...sensor amplifier 3.
...Binarization circuit A 4...Shift register 5...
・Flag generation circuit 6...Flag selection circuit 7...
Decoders 8, 9...WA, WB sample hold circuit 10...
・Comparator 14...AD converter 15.1
6...WA, WB latch circuit 17...Converter

Claims (1)

[Scope of Claim] A relative address demodulation circuit for demodulating a relative address of an optical disk in which relative addresses configured in a gray code shape periodically in the tracking direction and tracking wobble pits are intermittently provided, comprising: By the binarized value of the reproduced signal,
A flag generation circuit that generates a flag corresponding to the relative address; and a determination circuit that determines the magnitude of change in the reproduced signal due to the wobble pit, and selects a demodulation address according to the output of the determination circuit and the flag. A relative address demodulation circuit characterized by: