JPH03102446A - Control system for double write of data to storage - Google Patents

Abstract

PURPOSE:To simplify the control mechanism for a data double write instruction and to reduce the hardware quantity by applying the access control results of the validation of a block, the generation of an intra-block address, and the detection of an address exception applied to one of two storage units to the other storage unit as they are. CONSTITUTION:At execution of a data double write instruction, only an access control logic 4 is turned into a function. In this case, the logic 4 validates all block validating signals to the storage units 1 and 2 and supplies the addresses and data included in the same block to both units 1 and 2. At the same time, the address exception detecting result to be given to the unit 1 also serves as the address exception detecting result to the unit 2. As a result, both a control sequence and a control logic are simplified. Then a control mechanism is simplified for the data double write instruction and the hardware quantity is decreased.

Description

[Detailed Description of the Invention] [Summary] Regarding a control method for executing a double write instruction that writes data twice to two different areas of a storage device, the present invention relates to a simplification of a mechanism for controlling a data double write instruction. With the aim of
Executing a double write instruction to write the same data to each of the two storage units in a storage control device of a storage device that is composed of two storage units with the same interleaving configuration and storage capacity for the purpose of reducing the amount of hardware. edge. It has a configuration in which the access control results of block validation, intra-block address generation, and address exception detection performed on one storage unit are applied as they are to the other storage unit.

[Industrial application field]

The present invention relates to a control method for executing a double write instruction that writes data twice to two different areas of a storage device, and particularly to a storage control device that controls two storage devices with the same configuration. , relates to an efficient data double write control method for writing the same data in parallel to each storage unit using the same address in the bronc.

(Prior art) Multiple CPUs are connected to a system storage unit (called SSU)
In a multiprocessor system that co-sources data, for example, processing data is written twice for the current and backup data, and if a failure occurs during real-time processing using the current data, real-time processing can be continued using the backup data. R. A.S.
Corresponding processing and distributed processing in which two CPUs perform different processing in parallel on the same data written twice in different areas are often performed.

A conventional data double write control method in such a case is shown in FIG.

In FIG. 3, 11 and 12 are system storage units SSUO and SStJ1, respectively. The SSUO is made up of two storage elements, SSEO and SSE1, and the SSUI is also made up of SSE2 and SSE3. Each system storage unit SSUO or SSUI
Each has the same interleaving configuration and the same storage capacity, and constitutes two blocks on one storage device.

1,314.15 are access sources such as CPU and CHP, respectively.

16 is a storage control device. Access source 1314. ．． 1
Priority determination control is performed for access requests from 5. The prioritized access requests are sent to system storage unit SSUO. Distribute to SSUI.

17 is an access distribution circuit M that performs access distribution control.
It is OVER.

)lOVEI? 17 is for one prioritized access request. Generates a request l-VALID to validate the storage unit (one of SSU O and SSUI) corresponding to the access destination block and an address within one storage unit, that is, an internal address ADDRESS, and applies the corresponding data along with the data. applied to the storage unit. MOVEI again? 1. 7 performs an address exception detection operation for the access address at this time.

By the way, when a double write command for data targeting SSUO and SSUI is input from the access source.
Conventionally, access control for each write destination was performed separately. For this reason, MOVER17 first uses SSU
Request VALID and AD for block of O
The occurrence of DRESS. Detects address exceptions. Next, requests VALID and ADDRESS are generated for the SSUI block, and address exceptions are detected.

[Problem to be solved by the invention]

In the conventional data double write control method described above, the storage control device writes two storage units L-SSUO and SS
For the UI. Since the generation of the request VALID block address ADDRESS and the address exception detection were performed independently and sequentially, the control for this was duplicated. The control mechanism 4 had become complicated.

The present invention aims to simplify the control mechanism for data double write commands and reduce the amount of hardware.

[Means to solve the problem]

In controlling a data double write instruction, the present invention focuses on the fact that access control to two write destination storage units I causes generation of the same address and address exception detection, and the present invention provides access control to one storage unit. By delegating access control to the other storage unit, the access control mechanism for the other storage unit is simplified.

FIG. 1 is a diagram showing the principle of the present invention.

In the figure, 1 and 2 are. Each storage unit has the same interleaving configuration and storage capacity.

L is. Record i! Unit 1.2 is a storage control device that processes access requests.

4 is the memory unit 1 when the y-tani double write instruction is executed.
This is the access control logic for 1 and 2.

Reference numeral 5 denotes an access control 1 wholesale logic for the storage unit 2 when a normal access command is executed.

When a data double write instruction is executed, only the access control logic 4 is functionalized. In this case, access control logic 4
validates all block enable signals for storage unit 1.2 and supplies the same block address and data to both storage units 1 and 2. Further, the address exception detection result for storage unit 1 is also handled as address exception detection for storage unit 2.

(Operation) In FIG. 1, when a normal access command is executed, the access control logic 4 or 5 is operated depending on the block to be accessed.

In addition, in the case of the conventional data double write control method, in response to a data double write command, access control logic 4 enables the block of storage unit l-1, generates an address in the block 1 cock, and writes data. After that, the access control logic 5 enabled the corresponding block 1 for the storage unit 2 and wrote to the memory unit 1.1 using the address and data in the same block. In the invention, when a data double write instruction is detected,
Access control logic 4 takes over the function of access control logic 5, simultaneously validates blocks for both storage units I-1.2, and distributes addresses and data within the same block.

Furthermore, since address exception detection is not required for storage units 1 and 2, the control sequence and control logic become simpler.

〔Example] Figure 2 is. FIG. 1 is a configuration diagram of one embodiment of the present invention.

In the figure, 11 is a system memory consisting of SSEO and SSEI. 2
&t System storage unit 1/SSUI consisting of SSE2 and SSE3, 13 to 15 are access sources 7, 16 is a storage controller, 17' is an access distribution circuit MOV
It is ER. Each element shown from 11 to 16 is
Since it is the same as that explained in the conventional method shown in Figure 3,
The explanation will be omitted here.

The MOVER 1 7' determines whether the access request from the access sources 13 to 15 is a data double write command or another access command, and if it is a normal access command, it determines whether it is a data double write command or another access command. Perform similar access control. However, in the case of a data double write instruction. After performing address exception detection, SSUO, SSUI
SSEO,, SSEl. All request VALIDs for SSE2 and SSE3 are enabled, and 80 DPI in the same block! Supply SS to each SSE.

Also, although it is not shown in the diagram at this time. Write data is also supplied.

As a result, the same data is written to the same block address in each of SSUO and SSUI.

8 [Effects of the Invention] According to the present invention, the access control logic when controlling a data double write instruction is simplified, and the amount of 3 hearts is reduced and the cost I.
・It is possible to achieve a reduction in

[Brief explanation of drawings]

Figure 1 shows the principle of the present invention, and Figure 2 shows the configuration of one embodiment of the tree invention method. FIG. 3 is a block diagram of a conventional system. 1 and 2 in Figure 1: Storage units 1 and 3: Storage control device 4; Storage unit 1-1 when executing the double edge command
．． Access control logic 5 for storage unit 2: Access control logic for storage unit 1-2 when executing a normal access command

Claims (1)

[Scope of Claims] In a storage control device for a storage device consisting of two storage units with the same interleaving configuration and storage capacity, when executing a double write instruction to write the same data to each of the two storage units, Data double write control for a storage device characterized in that the access control results of block validation, intra-block address generation, and address exception detection performed on one storage unit are applied as is to the other storage unit. method.