JPH03101586A - Common data bus control system - Google Patents

Abstract

PURPOSE:To relieve the load of a central processing unit and to improve the entire exchange system by revising dynamically the priority of a common data bus operating request of a communication equipment in the inside of an arbitor in matching with the traffic state of a common data bus. CONSTITUTION:A priority decision circuit 230 recognizes a common data bus operating rate of communication equipments 300-30n with traffic information of the common data bus noticed from a common data bus traffic observation circuit 220, calculates a share occupied in the entire common data bus, decides the priority of contention arbitration with respect to the communication equipments 300-30n based on the calculated data and informs a common data bus operation permission signal via an arbitor bus 421. when a change is required for the common data bus operating request level in the communication equipments 300-30n, a central processing unit 100 revises the common data bus operating request level to a relevant communication equipment via a common bus 410.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an electronic switching system, and more particularly to a common data bus control method for an electronic switching system comprising one arbiter device and a plurality of communication devices.

Conventionally, this type of common data bus control method has been used to control the common data bus of each communication device depending on the type of communication device or station data, etc., despite having multiple common data bus usage request priority levels. In most cases, the priority level of usage requests is semi-fixed, or the common data bus usage priority level is controlled by a central processing unit.

Problems to be Solved by the Invention However, in the conventional common data bus control method described above, the common data bus use request level of communication devices is semi-fixed for each type of communication device or mounting position. If there are multiple communication devices of the same type,
Even if the load is concentrated on one communication device, the common data bus usage rate between the same type of communication devices will be fixed regardless of the degree of load concentration, and the usage rate of the common data bus will be fixed regardless of the degree of load concentration. This has the disadvantage that the processing capacity of the exchange is reduced.

In addition, when the central processing unit controls the common data bus use request level, the processing capacity of the central processing unit decreases and the processing capacity of the switching equipment decreases, and the central processing unit requires the use of the common bus. Even if the priority levels are changed, if the proportion of common data bus use requests within the same priority level increases, there is a drawback that priority order within the same priority level cannot be determined.

The present invention has been made in view of the above-mentioned conventional situation,
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a novel common data bus control method that eliminates the above-mentioned drawbacks inherent in the conventional technology and makes it possible to realize highly efficient use of a common data bus.

Means for Solving the Problems In order to achieve the above object, the common data bus control method according to the present invention is capable of setting a common data bus use request level from the central processing unit in each communication device via the control bus. The arbiter device includes a common data bus traffic observation circuit that monitors the common data bus access rate of each communication device, and a common data bus traffic observation circuit that monitors the common data bus access rate of each communication device based on the traffic of the common data bus. It is configured to include a priority order determining circuit that changes the priority order of usage requests, and a common data bus traffic information holding circuit that can be scanned from the central processing unit via a control bus.

Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

Referring to FIG. 1, communication devices 300 to 3On each have a common data bus use request level determination circuit 310 internally.
~31n. The arbiter device 200 internally includes a common data bus traffic information holding circuit 210, a common data bus traffic observation circuit 220, and each communication device 300 to 3O.
It has a priority determining circuit 230 for requests to use the common data bus from n. The common data bus traffic information holding circuit 21O1 and the common data bus use request level determining circuits 310 to 31n are connected to the control bus 410. The common data bus traffic observation circuit 220 and the communication devices 300 to 3On are connected to the common data bus 420. Furthermore, the arbiter bus 421 is connected to the common data bus 42.
It is part of 0.

The central processing unit 100 is a central processing unit that can change the common data bus usage priority level based on traffic information.

When the communication devices 300 to 3On use the common data bus 420, the common data bus use request level determination circuit 31
A common data bus use request with a common data bus use request level set in advance from 0 to 31n is sent to the arbiter bus 42.
1 to the arbiter device 200.

The arbiter device 200 performs contention arbitration for each priority level of the common data bus use request from the communication devices 300 to 3On received via the arbiter bus 421, and selects the common data bus 420 for one communication device with the highest priority level.
When the communication devices 300 to 3On receive permission to use the common data bus from the arbiter device 200 via the arbiter bus 421, they can access the common data bus 420.

The common data bus traffic observation circuit 220 in the arbiter device 200 receives requests from the communication devices 300 to 30n to use the common data bus via the arbiter bus 421 and the amount of data transmitted on the common data bus 420 to the communication devices 300 to 30n. Observe the usage rate of the common data bus every 3On. Common data bus traffic observation circuit 220
The traffic information observed is held in the common data bus traffic information holding circuit 210 and is notified to the priority order determining circuit 230. Priority determination circuit 23
0 is calculated by recognizing the common data bus usage rate of each communication device 300 to 3On based on the common data bus traffic information notified from the common data bus traffic observation circuit 220, and calculating the proportion to the entire common data bus. Based on the data, the priority order of contention arbitration for each communication device 300 to 30n is determined, and a common data bus use permission signal is sent to each communication device 300 to 30n via the arbiter bus 421.
to notify.

The central processing unit 100 reads the common data bus usage request status of each communication device 300 to 30n and the usage status of the common bus 420 from the common data bus traffic information holding circuit 210 via the control bus 410.
If it is necessary to change the common data bus use request level among n, the central processing unit 100 changes the common data bus use request level to the corresponding communication device via the control bus 410.

The common data bus use request level determination circuit 311 changes the common data bus use request level upon receiving the common data bus use request level change information via the control bus 410, and thereafter controls the central processing unit until further change. 10
A request to use the common data bus 420 is made at the common data bus use request priority level set from 0 via the control bus 410.

FIG. 2 is a block diagram showing a detailed example of the internal structure of the common data bus traffic observation circuit 220.

Referring to FIG. 2, the arbiter bus interface circuit 221 is connected to the arbiter bus 421, and receives requests to use the common data bus and transmits permission to use the common data bus. Each communication device/bus use request priority level counting circuit 223 calculates, if the common data bus use request received from the arbiter bus interface circuit 221 is a request from a communication device that matches the assigned communication device number, The counter for the corresponding common data bus usage request priority level is incremented by 1. Common data bus traffic observation circuit 22
0 periodically transfers the contents of each communication device/bus use request priority level counting circuit 223 to the common data bus traffic information holding circuit 210.

Common data bus access detection circuit 222 is connected to common data bus 420 and detects whether common data bus 420 is being used. Further, when the common data bus 420 is being used according to the common data bus usage permission information, the corresponding communication device-specific counting circuit 224 is activated and the system clock is incremented by 1 until the access of the corresponding communication device is completed. This count value is periodically transferred to the common data bus traffic information holding circuit 210.

Counting circuit 22 for each communication device/bus use request priority level
3.Which communication device has more common data bus 420?
You can see if you are using

FIG. 3 is a block diagram showing a detailed example of the internal structure of the priority order determining circuit 230. As shown in FIG.

Referring to FIG. 3, the priority determining circuit 230 includes a traffic information receiving circuit 231 for receiving traffic information from the common data bus traffic observing circuit 220 and a microprocessor section 232. The microprocessor unit 232 calculates the traffic on the common data bus and the usage rate of the common data bus for each communication device from the traffic information received from the traffic information receiving circuit 231, and when a certain standard is reached, the traffic on the common data bus is calculated for the communication devices 300 to 3On. Changes the priority of permission to use the common data bus (increases or lowers the priority) and controls arbitration conflict processing.

As described in detail, according to the present invention, by dynamically changing the priority order of requests to use a common data bus from communication devices in accordance with the traffic state of the common data bus within the arbiter device, the central processing unit This has the effect of reducing the load on the system, improving the processing capacity of the entire switching system, and making efficient use of the common data bus.

According to the present invention, it is also possible to change the priority order when the common data bus usage request level becomes constant, thereby achieving the effect that the common data bus can be used efficiently without reducing the throughput of the exchange.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
1 is a block diagram showing a specific example of the configuration of the common data bus traffic observation circuit, and FIG. 3 is a block diagram showing a specific example of the configuration of the priority order determining circuit. 100... Central processing unit, 200... Arbiter device, 210... Common data bus traffic information holding circuit, 220... Common data bus traffic observation circuit, 2
21... Arbiter bus interface circuit, 222...
・・Common data bus access detection circuit, 223 ・・Counting circuit for each communication device/bus use request priority level, 224
. . . Counting circuit for each communication device, 230 . . . Priority determining circuit, 231 . . . Traffic information receiving circuit, 232.
...Microprocessor section, 300 to 30n...Communication device, 311 to 31n...Common data bus usage request level determination circuit, 410...Control bus, 420...
・Common data bus, 421...Arbiter bus

Claims (3)

[Claims] (1) A central processing unit controls a plurality of communication devices via a control bus, and an arbiter device determines the right to use a common data bus for data transfer between the plurality of communication devices; In an electronic switching system in which a plurality of communication devices are connected and have a plurality of priority levels as common data bus use requests, a common data bus use request level is sent from the central processing unit to each communication device via a control bus. a common data bus traffic observation circuit that monitors the common data bus access rate of each communication device in the arbiter device; and a common data bus traffic observation circuit that monitors the common data bus access rate of each communication device; The present invention is characterized by having a priority determination circuit that changes the priority order for common bus use requests for each common data bus request level, and a common data bus traffic information holding circuit that can be scanned from a central processing unit via a control bus. Common data bus control method. (2) The common data bus traffic observation circuit provided in the arbiter device includes an arbiter bus interface circuit that is connected to the arbiter bus and receives a request to use the common data bus and transmits a permission to use the common data bus; A communication device/bus that increments the corresponding common data bus use request priority level counter by 1 when the common data bus use request received from the bus interface circuit is a request from a communication device that matches the assigned communication device number. A counting circuit for each use request priority level and, if connected to the common data bus and the common data bus is in use, a counting circuit for each corresponding communication device are activated until the access of the corresponding communication device is completed. 2. The common data bus control method according to claim 1, further comprising a common data bus access detection circuit that increments the common data bus by +1 based on a system clock. (3) The priority determining circuit provided in the arbiter device includes a traffic information receiving circuit that receives traffic information from the common data bus traffic observation circuit, and a traffic information receiving circuit that receives the traffic information from the traffic information receiving circuit. The traffic on the common data bus and the usage rate of the common data bus for each communication device are calculated, and when a certain standard is reached, the priority order of permission to use the common data bus for each communication device is changed and arbitration conflict processing is controlled. Claim (1) characterized in that it includes a microprocessor section.
Or the common data bus control method described in (2).