JPH03101447A - Transmitter - Google Patents

Abstract

PURPOSE:To improve the entire power efficiency by preventing a phase difference of a signals inputted from 1st, 2nd class C amplifiers to a power amplifier from being larger than a prescribed value and keeping the amplitude constant. CONSTITUTION:Whether or not a modulation phase difference between in-phase component I1, orthogonal component Q1 of a 1st modulation signal and in-phase component I2, orthogonal component Q2 of a 2nd modulation signal is larger than a prescribed modulation phase difference is discriminated and when not larger, 1st and 2nd modulation signals of a 1st arithmetic means 5 are selected and when larger, 3rd and 4th modulation signals of a 2nd arithmetic circuit 12 are selected. Moreover, a bias voltage is fed to 1st, 2nd class C amplifiers 8, 9 so that the amplitude of the signal amplified by the 1st, 2nd class C amplifiers 8, 9 is constant. Thus, the phase difference of the signal inputted from the 1st, 2nd class C amplifiers 8, 9 to the power amplifier 10 is not larger than a prescribed value and the amplitude is made constant. Thus, the power loss of the power synthesizer is reduced and the entire power efficiency is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a transmitting device used in digital mobile communications and the like.

BACKGROUND OF THE INVENTION FIG. 3 shows the configuration of a conventional transmitting device, and FIG. 4 is an explanatory diagram showing main signals in the transmitting device of FIG. 3 as vectors.

In FIG. 3, 1 is a transmission signal input terminal to which a serial data signal to be transmitted is applied, and 2 is a transmission signal input terminal 1.
A serial-to-parallel converter converts the input serial data signal into two parallel data signals; 3.4 is a band-limiting through low-pass filter for each of the two parallel data signals converted by the serial-to-parallel converter 2; 5, the in-phase component II and quadrature component Q1 of the first modulated signal, and the in-phase component I2 of the second modulated signal are generated by two parallel data signals I and Q, each band-limited by a low-pass filter 3.4. , is an arithmetic circuit that calculates the orthogonal component Q2.

6 is a quadrature modulator that performs four-phase phase modulation using the in-phase component It1 of the first modulated signal calculated by the calculation circuit 5 and the quadrature component Q1; 7 is the in-phase component of the second modulation signal calculated by the calculation circuit 5 I2, a quadrature modulator that performs quadrature phase modulation using the quadrature component Q2; 89, a class C amplifier that amplifies the signal quadrature phase modulated by the quadrature modulator 6.7;
0 is a power combiner for vector-synthesizing the signals amplified by the C-class amplifiers 8.9 and transmitting them as radio waves via the antenna 11.

Next, the operation of the above conventional example will be explained with reference to FIGS. 3 and 4.

For the data signal applied to the transmission signal input terminal 1,
As shown in Fig. 4, the signal indicated by vector S is transmitted to antenna 1
1, the vector S is obtained by combining vectors S and S2 with the same absolute value, and the vector St S2 is selected so that MAX, lSl ≦2131 1=2132.

In FIG. 3, vectors S and S2 correspond to the output signals of the class C amplifier 8.9, respectively, and vectors Vl and V2 represent the four-phase phase modulated signals of constant amplitude output from the quadrature modulator 6.7. If the gain of the class C amplifier 8.9 is G, then the following relationship S+ =G-V+, S2 =
G-V2 is established. Moreover, as shown in FIG. 4, v+
= V2 = A.

In addition, the vector V IV 2 is a four-phase phase modulation of the in-phase component II and quadrature component Q of the first modulation signal calculated by the calculation circuit 5, and the in-phase component 12 and quadrature component Q2 of the second modulation signal, respectively. It can be obtained by here,
Since the vector VI V2 has a constant amplitude as described above, the vector S+ 52 amplified by the class C amplifier 8.9 is a constant multiple of the vectors V1 and V2.

Therefore, in the conventional example described above, it is possible to amplify and transmit the quadrature phase modulation signal whose band is limited in the baseband signal by the class C amplifier 8.9 while maintaining the band limiting effect.

Problems to be Solved by the Invention However, in the conventional transmitting device described above, four-phase phase modulation is performed using the in-phase component 11 and quadrature component QI of the first modulated signal, and the in-phase component I2 and quadrature component Q2 of the second modulated signal, Since class C amplification is performed, when the phase difference of the output signal (vector SI 32 ) of the class C amplifier 8.9 increases, the power loss of the power combiner 10 that vector-synthesizes these signals increases, and the power of the entire transmitting device decreases. There is a problem that efficiency decreases.

SUMMARY OF THE INVENTION In view of the above conventional problems, an object of the present invention is to provide a transmitter that can reduce power loss in a power combiner and improve overall power efficiency.

Means for Solving the Problems In order to achieve the above object, the present invention provides a first calculation means for calculating an in-phase component and a quadrature component of a first modulation signal and an in-phase component and a quadrature component of a second modulation signal. In addition, the in-phase components and quadrature components of the first modulation signal and the in-phase components and quadrature components of the second modulation signal cause the in-phase component and quadrature component of the third modulation signal and the fourth modulation with a predetermined modulation phase difference. A second calculation means for calculating an in-phase component and a quadrature component of the signal is provided;
It is determined whether the modulation phase difference between the in-phase component and quadrature component of the modulated signal and the in-phase component and quadrature component of the second modulated signal is larger than the predetermined modulation phase difference, and if not, the first calculation is performed. selects the first and second modulation signals of the means, and selects the third and fourth modulation signals of the second arithmetic circuit if they are large; The bias voltage is set to the first,
The signal is supplied to the second class C amplifier.

According to the above configuration, the phase difference between the signals input from the first and second class C amplifiers to the power amplifier does not exceed a predetermined value, and the amplitude is constant, so that the power loss of the power combiner is reduced. can be reduced and thus improve overall power efficiency.

EXAMPLES Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the transmitting device according to the present invention, FIG. 2 is an explanatory diagram showing main signals in the transmitting device of FIG. 1 as vectors, and the configuration shown in FIG. 3 The same reference numerals are given to the same parts.

In FIG. 1, 1 is a transmission signal input terminal to which a serial data signal to be transmitted is applied, and 2 is a transmission signal input terminal 1.
A serial-to-parallel converter that converts the serial data signal input into the serial-to-parallel converter 2 into two parallel data signals; 3.4 is a low-pass filter that limits the band of the two parallel data signals converted by the serial-to-parallel converter 2; 5, the in-phase components I1 . A calculation circuit (I) that calculates the orthogonal component Q1, the in-phase component 2 of the second modulation signal, and the orthogonal component Q2.
It is.

12 is a third modulation phase difference having a predetermined modulation phase difference based on the in-phase component 11 and quadrature component Q1 of the first modulation signal calculated by the calculation circuit 5, and the in-phase component I2 and quadrature component Q2 of the second modulation signal. In-phase component Il+ and quadrature component Q++ of the modulated signal
and the in-phase component 128 and quadrature component Q2+ of the fourth modulation signal
The arithmetic circuit (n) 13 calculates the control signal C1 and outputs the control signal C1 to the power supply voltage control circuit 15. It is determined whether the difference between the modulation phase of the first modulation signal and the modulation phase of the second modulation signal is larger than a predetermined value based on the in-phase component ■2 and quadrature component Q2 of the modulation signal, and the control signal is determined based on the determination result. C2 is output to the changeover switch 14, and the control signal C3 is output to the power supply voltage control circuit 1.
This is a judgment circuit that outputs the output to 5.

Note that the predetermined value of the determination circuit 13 is the same as the predetermined modulation phase difference between the third and fourth modulation signals of the arithmetic circuit 12. Also,
The changeover switch 14 selects and outputs the first and second modulation signals calculated by the calculation circuit 5 or the third and fourth modulation signals calculated by the calculation circuit 12 according to the control signal C2.

The power supply voltage control circuit 15 is connected to the arithmetic circuit 12 as described later.
control signal C0 from the determination circuit 13, and control signal C0 from the determination circuit 13.
3 and a transmission output control signal C4 from a base station (not shown) to control the bias voltage Vcc for the class C amplifier 8.9.

6 is a quadrature modulator that performs four-phase phase modulation using the in-phase component 11 and quadrature component Q+ of the first modulation signal selected by the changeover switch 14, or the in-phase component II+ and quadrature component Q1 of the third modulation signal; , an in-phase component I2, a quadrature component Q2, and a quadrature component Q2 of the second modulation signal selected by the changeover switch 14,
Or the in-phase component I21 and quadrature component Q2+ of the fourth modulation signal
This is a quadrature modulator that performs four-phase phase modulation.

Class C amplifiers 8.9 each output signals v and v2 that have been quadrature phase modulated by quadrature modulators 6.7 to bias voltages V.
The power combiner 10 is amplified according to the C class amplifier 8.
．． The signal S82 amplified by 9 is vector-combined and sent out as radio waves via the antenna 11.

Next, the operation of the above embodiment will be explained with reference to FIGS. 1 and 2.

As in the conventional example, in response to the data signal applied to the transmission signal input terminal 1, a signal indicated by a vector S is transmitted from the antenna 11 as shown in FIG. It is obtained by combining vectors S+82 with the same absolute value corresponding to the output signals S1 and S2 of 8.9.

Similarly, the vector S+ 32 corresponds to the constant amplitude output signals v1 and v2 output from the quadrature modulator 67, and is a constant multiple of the vectors V1 and 2 whose absolute values are equal,
This constant is the gain of the class C amplifier 8.9.

Here, the vector ■1, V2 is the output signal ■1. of the arithmetic circuit 5. SQI I2 and Qz are quadrature phase modulated, and the phase difference φd between vectors Vl and V2 is a predetermined value φ
, the determination circuit 13 switches the changeover switch 14 to the arithmetic device 12 side using the control signal C2.

Therefore, the output signal of the quadrature modulator 6.7 becomes a vector V, .

Here, the output signals III, Qz, I2+ of the arithmetic unit 12
*Q2+ is respectively I z= I + cos φc Q+sin φ.

Qth=Q+cosφe I+sinφ0I 21=
I 2 cO5φc Q2sinφ, Q21=Q2C
O8φe-12sinφC.

Further, as shown in FIG. 2, the signal vector S to be transmitted is the vector vll, the vector Sl which is the vector V21 multiplied by a constant.
It is obtained by combining 1% S21 using the power combiner 10.

Therefore, the determination circuit 13 outputs the switching control signal C3, and the arithmetic circuit 12 outputs the vector difference Sz l l
When the control signal C+ corresponding to the sth 1 is output, the power supply voltage control circuit 15 generates a bias voltage Vcc such that the vector of the output signal of the class C amplifier 8.9 becomes Sll 321, respectively.

Note that the power supply voltage control circuit 15 also generates a bias voltage Vcc in response to a control signal C1 from the base station to control the power of the transmission signal.

Therefore, according to the above embodiment, the phase difference between the vectors of the output signals of the class C amplifier 8.9 does not become larger than the predetermined value φ, and even if the phase difference becomes small, the bias voltage V
Since the amplitude is constant due to cc, the power loss of the power combiner can be reduced, thus improving the overall power efficiency.

DETAILED DESCRIPTION OF THE INVENTION As described above, the present invention provides, in addition to the first calculation means for calculating the in-phase and quadrature components of the first modulation signal and the in-phase and quadrature components of the second modulation signal, a first The in-phase components and quadrature components of the modulated signal and the in-phase components and quadrature components of the second modulated signal produce the in-phase components and quadrature components of the third modulated signal and the in-phase component of the fourth modulated signal with a predetermined modulation phase difference. and a second calculation means for calculating orthogonal components, wherein the modulation phase difference between the in-phase component and quadrature component of the first modulation signal and the in-phase component and quadrature component of the second modulation signal is greater than the predetermined modulation phase difference. If it is not large, the first
The first and second modulation signals of the arithmetic means are selected, and if the signal is larger, the third and fourth modulation signals of the second arithmetic circuit are selected, and the first and second class C amplifiers The bias voltage is set to the first and second bias voltages so that the amplitude of the amplified signal is constant.
Since the phase difference between the signals input to the power amplifier from the first and second class C amplifiers does not become larger than a predetermined value, and the amplitude remains constant, the power synthesis The power loss of the device is reduced, and the overall power efficiency can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a transmitting device according to the present invention, FIG. 2 is an explanatory diagram showing main signals in the transmitting device of FIG. 1 as vectors, and FIG. 3 is a diagram showing a conventional transmitting device. FIG. 4, a block diagram showing the apparatus, is an explanatory diagram showing main signals in the transmitting apparatus of FIG. 2 as vectors. 2...Series-to-parallel conversion! , 3.4... Rono Kusufili, 5.12... Arithmetic circuit, 6.7... Orthogonal modulator, 8.9... Class C amplifier, 10... Power amplifier,
11... Antenna, 13... Judgment circuit, 14...
Switching switch, 15...Power supply voltage control circuit.

Claims (1)

[Scope of Claims] Means for converting a serial data signal to be transmitted into two parallel data signals; and first and second low-pass devices for band-limiting the two parallel data signals converted by the converting means. Calculating the in-phase component and quadrature component of the first modulated signal and the in-phase component and quadrature component of the second modulated signal using the filter and two parallel data signals band-limited by the first and second low-pass filters. a first calculation means for calculating a predetermined modulation phase difference using the in-phase component and quadrature component of the first modulation signal and the in-phase component and quadrature component of the second modulation signal calculated by the first calculation means; a second calculation means for calculating the in-phase component and the quadrature component of the modulated signal of No. 3 and the in-phase component and the quadrature component of the fourth modulated signal; and the in-phase component of the first modulated signal calculated by the first calculation means. and determine whether the modulation phase difference between the quadrature component and the in-phase component and the quadrature component of the second modulation signal is larger than the predetermined modulation phase difference, and if not, the first and second calculation means of the first calculation means means for selecting the second modulation signal, and selecting the third and fourth modulation signals of the second arithmetic circuit if the value is larger; and orthogonal modulation of the first or third modulation signal selected by the selection means. a first orthogonal modulation means for orthogonally modulating the second or fourth modulation signal selected by the selection means; first and second C-class amplifiers that amplify signals, respectively; bias voltages are applied to the first and second C-class amplifiers so that the amplitudes of the signals amplified by the first and second C-class amplifiers are constant; and means for supplying a class amplifier.