JPH03101191A - Method of filling via-hole - Google Patents
Method of filling via-holeInfo
- Publication number
- JPH03101191A JPH03101191A JP23686989A JP23686989A JPH03101191A JP H03101191 A JPH03101191 A JP H03101191A JP 23686989 A JP23686989 A JP 23686989A JP 23686989 A JP23686989 A JP 23686989A JP H03101191 A JPH03101191 A JP H03101191A
- Authority
- JP
- Japan
- Prior art keywords
- board
- balls
- solder material
- brazing material
- holes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000000463 material Substances 0.000 claims abstract description 37
- 239000000919 ceramic Substances 0.000 claims abstract description 19
- 229910000679 solder Inorganic materials 0.000 claims abstract description 9
- 238000010438 heat treatment Methods 0.000 claims description 7
- 238000010304 firing Methods 0.000 claims description 3
- 238000005476 soldering Methods 0.000 abstract description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052799 carbon Inorganic materials 0.000 abstract description 2
- 239000002184 metal Substances 0.000 abstract description 2
- 229910052751 metal Inorganic materials 0.000 abstract description 2
- 238000005219 brazing Methods 0.000 description 28
- 239000000758 substrate Substances 0.000 description 13
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 235000013405 beer Nutrition 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔概要〕
ビア充填方法に係り、特にロウ材にてセラミック系プリ
ント基板に形成された表裏接続用のビアを充填する方法
に関し、
ビア充填後、ビア内に空洞、へこみ等が発生せず、信軌
性の高いセラミック系プリント基板を製造することを目
的とし、
セラミック系プリント基板にビアを形成する工程と、該
ビアが形成された位置に球状ロウ材を位置決めする工程
と、該球状ロウ材を上面から加圧する工程と、該セラミ
ック系プリント基板を加熱・焼成する工程とにより構成
される。[Detailed Description of the Invention] [Summary] This invention relates to a via filling method, in particular a method of filling vias for connecting the front and back sides formed on a ceramic printed circuit board with a brazing material, in which cavities or dents are formed in the vias after filling the vias. With the aim of manufacturing a ceramic printed circuit board with high reliability without the occurrence of such problems, the process includes a process of forming vias on a ceramic printed circuit board, and a process of positioning a spherical brazing material at the position where the via is formed. , a step of pressurizing the spherical brazing material from above, and a step of heating and firing the ceramic printed circuit board.
本発明は、ビア充填方法に係り、特にロウ材にてセラミ
ック系プリント基板に形成された表裏接続用のとアを充
填する方法に関するものである。The present invention relates to a via filling method, and more particularly to a method of filling vias for connecting the front and back sides formed on a ceramic printed circuit board with a brazing material.
近年、セラミック系プリント基板は熱伝導率が優れてい
る点や、多層化、高密度化設計が可能であることからそ
の用途が増えている。In recent years, the use of ceramic printed circuit boards has been increasing because they have excellent thermal conductivity and can be designed with multiple layers and high density.
小型電子機器においては、単層型セラミック系プリント
基板がその適用に最も適しており、この単層型セラミッ
ク系プリント基板において高密度化を図ろうには基板の
両面に部品実装を行うことで達成されており、そのため
基板の表裏接続を行う必要がある。Single-layer ceramic printed circuit boards are most suitable for use in small electronic devices, and high density can be achieved with single-layer ceramic printed circuit boards by mounting components on both sides of the board. Therefore, it is necessary to connect the front and back sides of the board.
、そのた、めには、ビアと呼ばれる孔を形成し、このビ
アを口゛つ材にて接続することが知られマいる。For this purpose, it is known to form a hole called a via and connect this via with a spout.
一方、更に実装密度の高密度化の要求に伴い、このビア
の系も年々小さくなりつつあり、系が小さくとも確実に
そのビア内にロウ材を充填することが可能である方法の
開発が要求されている。On the other hand, with the demand for higher packaging density, these via systems are becoming smaller year by year, and there is a need to develop a method that can reliably fill brazing material into the vias even if the system is small. has been done.
従来、かかるビアの充填方法としては、無電解＋電解メ
ツキ等のメツキプロセスで構成する方法が知られている
が、この方法では液体の性質上、限界があるため、第２
図（ａ）、（ｂ）に示される方法が用いられている。Conventionally, as a method for filling such vias, a plating process such as electroless + electrolytic plating is known, but since this method has limitations due to the nature of the liquid,
The methods shown in Figures (a) and (b) are used.
この方法は、−船釣にスクリーン印刷方法と呼ばれ、そ
の要旨はビア２２が形成されたセラミック系プリント基
板２１に、スキージ等の治具を用いてロウ材、例えば導
体ペースト（銅粉）２３を充填しくａ）、その後窒素炉
等の加熱か中で加熱・ロウ材することで、かかる導体ペ
ースト（銅粉）２３を熔融させ、ビア２２内に充填して
いた。This method is called a screen printing method, and its gist is that a ceramic printed circuit board 21 on which vias 22 are formed is coated with a soldering material, such as conductive paste (copper powder) 23, using a jig such as a squeegee. The conductor paste (copper powder) 23 is melted and filled into the via 22 by heating and brazing in a nitrogen furnace or the like.
しかしながら従来の充填方法では、ビアの系が小さくな
るとビア内に導体ペーストが入り難く、一方、銅粉の場
合は、充填時に空気がビア内に入ると、第２図（ｂ）の
如く、加熱・ロウ付後に空洞Ａ、へこみＢが発生し、基
板の信軌性を損なう問題があった。However, in the conventional filling method, when the via system becomes small, it is difficult for the conductive paste to enter the via.On the other hand, in the case of copper powder, if air enters the via during filling, it may cause heating as shown in Figure 2 (b). - There was a problem that cavities A and dents B were formed after soldering, impairing the reliability of the board.
従って、本発明は、ビア充填後、ビア内に空洞。Therefore, the present invention eliminates cavities within the via after filling the via.
へこみ等が発生せず、信転性の高いセラミ・ンク系プリ
ント基板を製造することを目的とするものである。The purpose is to manufacture a ceramic ink-based printed circuit board that is free from dents and has high reliability.
〔課題を解決するための手段］
かかる目的は、セラミック系プリント基板にビアを形成
する工程と、
該ビアが形成された位置に球状ロウ材を位置決めする工
程と、
該球状ロウ材を上面から加圧する工程と、該セラミック
系プリント基板を加熱・焼成する工程とを有することを
特徴とするビア充填方法、により達成される。[Means for Solving the Problems] This purpose includes a step of forming a via in a ceramic printed circuit board, a step of positioning a spherical brazing material at the position where the via is formed, and a step of processing the spherical brazing material from above. This is achieved by a via filling method characterized by comprising a step of pressing and a step of heating and firing the ceramic printed circuit board.
本発明においては上記のような方法を用いているので、
球状であるロウ材の表面張力および、かかるロウ材を上
面から加圧するため、ビア内に確実にロウ材が充填され
る。Since the present invention uses the method described above,
Because of the surface tension of the spherical brazing material and because the brazing material is pressurized from above, the brazing material is reliably filled into the via.
以下、本発明の実施例を図面を用いて詳細に説明する。 Embodiments of the present invention will be described in detail below with reference to the drawings.
第１図は、本発明の実施例を示す図であり、同図（ａ）
は、ロウ材ポールの位置決め工程同図（ｂ）は、加圧工
程
同図（ｃ）は、充填状態をそれぞれ示す。FIG. 1 is a diagram showing an embodiment of the present invention, and FIG.
(b) shows the brazing material pole positioning process, and (c) shows the pressing process, and the filling state.
図において、１はセラミック系プリント基板（以下、基
板と略す）、２はビア、３はロウ材ボール、３°は溶融
したロウ材、４は平板をそれぞれ示す。In the figure, 1 is a ceramic printed circuit board (hereinafter abbreviated as "substrate"), 2 is a via, 3 is a soldering material ball, 3° is a melted soldering material, and 4 is a flat plate.
尚、企図を通じて同一符号を付したものは同一対象物を
示す。In addition, the same reference numerals throughout the plan indicate the same objects.
基板１にドリル等で小径のビア２を複数形成した後、第
１図（ａ）に示すように、そのビア２の位置に対応する
ように充填すると７２の径の大小。After forming a plurality of small-diameter vias 2 on the substrate 1 with a drill or the like, as shown in FIG.
深さによって決定された量を有するロウ材ボール３を位
置決めする。A braze ball 3 having an amount determined by the depth is positioned.
この位置決めの方法としては、基板１の表面に多数のロ
ウ材ボール３を供給し、一方、基板１の背面にビア位置
と対応したマスク板を配置し、基板１の背面から真空吸
着する。その後、この基板１を反転させると、ビア２に
位置したロウ材ポール３は基板１の背面から吸着されて
いるため落下せず、他のロウ材ポール３は落下する。よ
って、ビア２にロウ材ボール３が１対１の関係に位置決
めが可能である。かかる方法を用いても若干ロウ材ボー
ル３がビア２に位置決めされない恐れもあるので、その
場合は作業者がピンセット等を用いて手作業で位置決め
されていないビア２にロウ材ボール３を供給するように
している。As a method for this positioning, a large number of solder balls 3 are supplied to the surface of the substrate 1, and a mask plate corresponding to the via position is placed on the back surface of the substrate 1, and vacuum suction is performed from the back surface of the substrate 1. Thereafter, when the substrate 1 is turned over, the brazing material poles 3 located in the vias 2 are attracted from the back surface of the substrate 1 and do not fall, while the other brazing material poles 3 fall. Therefore, the brazing material balls 3 can be positioned in a one-to-one relationship with the vias 2. Even if such a method is used, there is a possibility that the brazing material balls 3 may not be positioned in the vias 2, so in that case, the operator uses tweezers or the like to manually feed the brazing material balls 3 to the vias 2 that have not been positioned. That's what I do.
次に同図（ｂ）に示されるように、ロウ材ボール３を上
面から加圧するように平板４を位置決めする。Next, as shown in FIG. 4B, the flat plate 4 is positioned so as to press the brazing material ball 3 from above.
この平板４はロウ材との濡れ性が悪く、且つ少なくとも
基板１をロウ材する際の温度に充分耐えうる耐熱性に優
れた、例えばカーボン系またはセラミック性の金属より
なる物体であることが望ましい。This flat plate 4 is desirably an object made of carbon-based or ceramic metal, which has poor wettability with the brazing material and has excellent heat resistance that can withstand at least the temperature at which the substrate 1 is brazed. .
次に（ｂ）の状態を保ったままで窒素炉等の加熱炉中で
加熱・ロウ材することで、かかるロウ材ボール３を溶融
する（同図（Ｃ））。Next, while maintaining the state of (b), the solder ball 3 is melted by heating and brazing in a heating furnace such as a nitrogen furnace ((C) in the same figure).
ここで、本発明では、ロウ材ボール３の上面に配置した
平板４の自重により、ロウ材ボーク３は絶えず図中下方
向に圧力が働いている。よって、溶融したロウ材３゛が
ビア２内に充填されずに基板の表面上に逃げるといった
減少を軽減することかでき、ビア２内に気泡が介入され
ることを同様に軽減することができる。Here, in the present invention, pressure is constantly exerted on the brazing material ball 3 in the downward direction in the figure due to the weight of the flat plate 4 disposed on the upper surface of the brazing material ball 3. Therefore, it is possible to reduce the problem that the melted brazing material 3 is not filled into the via 2 and escape onto the surface of the substrate, and it is also possible to reduce the occurrence of air bubbles entering the via 2. .
次に、基板１の平面化のため基板１の表裏両面研磨し、
且つ所定の肯定を用いて配線パターン等を形成すること
で１枚の基板１が製造される。Next, both the front and back sides of the substrate 1 are polished to planarize the substrate 1,
One substrate 1 is manufactured by forming a wiring pattern and the like using a predetermined pattern.
以上詳細に説明したように本発明においては、ロウ材ポ
ールを加圧・溶融させるため、小径ビアに良好なロウ材
充填を行うことができ、セラミック系プリント基板の信
頼性を向上させることができる。As explained in detail above, in the present invention, since the brazing material pole is pressurized and melted, small-diameter vias can be filled with brazing material satisfactorily, and the reliability of ceramic printed circuit boards can be improved. .
ロウ材ボールを使用するので、ロウ材の量のコントロー
ルを行うことができる。Since a brazing material ball is used, the amount of brazing material can be controlled.
第１図は、本発明の実施例を示す図であり、同図（ａ）
は、ロウ材ボールの位置決め工程同図（ｂ）は、加圧工
程
同図（ｃ）は、充填状態
第２図は、従来の充填方法を示す図であり、同図（ａ）
は、導体充填状態
同図（ｂ）は、導体ロウ付状態をそれぞれ示す。
図において、
１は基板。
２はビア。
３はロウ材ポール。
４は平板。FIG. 1 is a diagram showing an embodiment of the present invention, and FIG.
Figure 2 shows the brazing material ball positioning process, (b) shows the pressurizing process, Figure 2 (c) shows the filling state, and Figure 2 (a) shows the conventional filling method.
(b) shows a state in which the conductor is filled and a state in which the conductor is soldered. In the figure, 1 is the substrate. 2 is beer. 3 is a waxed wood pole. 4 is a flat plate.
Claims (1)
する工程と、 該ビア（２）が形成された位置に球状ロウ材（３）を位
置決めする工程と、 該球状ロウ材（３）を上面から加圧する工程と、該セラ
ミック系プリント基板（１）を加熱・焼成する工程と、 を有することを特徴とするビア充填方法。[Claims] A step of forming a via (2) on a ceramic printed circuit board (1), a step of positioning a spherical solder material (3) at the position where the via (2) is formed, and a step of positioning the spherical solder material (3) at the position where the via (2) is formed. A via filling method comprising the steps of: pressurizing the material (3) from above; and heating and firing the ceramic printed circuit board (1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23686989A JPH03101191A (en) | 1989-09-14 | 1989-09-14 | Method of filling via-hole |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23686989A JPH03101191A (en) | 1989-09-14 | 1989-09-14 | Method of filling via-hole |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03101191A true JPH03101191A (en) | 1991-04-25 |
Family
ID=17007001
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23686989A Pending JPH03101191A (en) | 1989-09-14 | 1989-09-14 | Method of filling via-hole |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03101191A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2709913A1 (en) * | 1993-09-07 | 1995-03-17 | Sagem | Printed circuit board for vehicle dashboard. |
| US5454159A (en) * | 1994-02-18 | 1995-10-03 | Unisys Corporation | Method of manufacturing I/O terminals on I/O pads |
| US5479703A (en) * | 1992-12-23 | 1996-01-02 | International Business Machines Corporation | Method of making a printed circuit board or card |
| WO2002096170A1 (en) * | 2001-05-23 | 2002-11-28 | Pac Tech - Packaging Technologies Gmbh | Method for producing a contact substrate, and corresponding contact substrate |
-
1989
- 1989-09-14 JP JP23686989A patent/JPH03101191A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5479703A (en) * | 1992-12-23 | 1996-01-02 | International Business Machines Corporation | Method of making a printed circuit board or card |
| FR2709913A1 (en) * | 1993-09-07 | 1995-03-17 | Sagem | Printed circuit board for vehicle dashboard. |
| US5454159A (en) * | 1994-02-18 | 1995-10-03 | Unisys Corporation | Method of manufacturing I/O terminals on I/O pads |
| WO2002096170A1 (en) * | 2001-05-23 | 2002-11-28 | Pac Tech - Packaging Technologies Gmbh | Method for producing a contact substrate, and corresponding contact substrate |
| US7049213B2 (en) | 2001-05-23 | 2006-05-23 | Pac Tech-Packaging Technologies Gmbh | Method for producing a contact substrate and corresponding contact substrate |
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