JPH0298652U - - Google Patents
Info
- Publication number
- JPH0298652U JPH0298652U JP806989U JP806989U JPH0298652U JP H0298652 U JPH0298652 U JP H0298652U JP 806989 U JP806989 U JP 806989U JP 806989 U JP806989 U JP 806989U JP H0298652 U JPH0298652 U JP H0298652U
- Authority
- JP
- Japan
- Prior art keywords
- package
- board
- notch
- lower surfaces
- pins
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 2
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Multi-Conductor Connections (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP806989U JPH0298652U (cs) | 1989-01-26 | 1989-01-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP806989U JPH0298652U (cs) | 1989-01-26 | 1989-01-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0298652U true JPH0298652U (cs) | 1990-08-06 |
Family
ID=31213620
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP806989U Pending JPH0298652U (cs) | 1989-01-26 | 1989-01-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0298652U (cs) |
-
1989
- 1989-01-26 JP JP806989U patent/JPH0298652U/ja active Pending