JPH0297052A - Ceramic multilayer interconnection board - Google Patents
Ceramic multilayer interconnection boardInfo
- Publication number
- JPH0297052A JPH0297052A JP63249439A JP24943988A JPH0297052A JP H0297052 A JPH0297052 A JP H0297052A JP 63249439 A JP63249439 A JP 63249439A JP 24943988 A JP24943988 A JP 24943988A JP H0297052 A JPH0297052 A JP H0297052A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- ceramic multilayer
- laminated part
- green sheet
- multilayer interconnection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 abstract description 8
- 239000003990 capacitor Substances 0.000 abstract description 2
- 239000003822 epoxy resin Substances 0.000 abstract description 2
- 229920000647 polyepoxide Polymers 0.000 abstract description 2
- 239000007767 bonding agent Substances 0.000 abstract 1
- 238000003475 lamination Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000007747 plating Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は例えばＩＣチップ収納用パッケージの一部とし
て使用するセラミック多層配線基板に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a ceramic multilayer wiring board used, for example, as part of an IC chip storage package.
（従来の技術）
メモリー等のＩＣチップ収納するパッケージとして、プ
ラスチックよりも気密性等の特性において優れるセラミ
ックからなるものを従来から用いており、特に特公昭６
２−１７８７１号に開示されるものにあっては、パッケ
ージの基板自体を多層配線基板とし、複数のＩＣチップ
を基板上に高密度に搭載し得るようにしている。(Prior art) As a package for storing IC chips such as memory devices, ceramics have traditionally been used because they have better airtightness and other properties than plastics.
In the device disclosed in No. 2-17871, the substrate of the package itself is a multilayer wiring board, so that a plurality of IC chips can be mounted on the substrate at high density.
（発明が解決しようとする課題）
上述した多層配線基板を製作する技術としてはグリーン
シート（焼成前のセラミックシート）積層法及び印刷積
層法が知られている。(Problems to be Solved by the Invention) As techniques for manufacturing the above-mentioned multilayer wiring board, a green sheet (ceramic sheet before firing) lamination method and a printing lamination method are known.
グリーンシート積層法によって多層配線基板を製作する
場合には、−枚のグリーンシートの厚みが０．５＋ｎｍ
程度であるのでパッケージ全体の厚みが厚くなり、また
印刷積層法によフて多層配線基板を製作する場合には、
パッケージ全体の厚みは薄くなるが、信号用配線と電源
用配線及び接地用配線とが近接するため浮遊容量が大き
くなり、信号の伝送速度の遅延が起こり、電気特性が低
下する。When manufacturing a multilayer wiring board using the green sheet lamination method, the thickness of the green sheet is 0.5+nm.
Since the thickness of the package is only about 100%, the overall thickness of the package becomes thick.
Although the overall thickness of the package becomes thinner, stray capacitance increases because the signal wiring, power supply wiring, and grounding wiring are close to each other, resulting in a delay in signal transmission speed and deterioration of electrical characteristics.
（課題を解決するための手段）
上記課題を解決すべく本発明は、ＩＣパッケージとして
用いるセラミック多層配線基板を印刷積層部とグリーン
シート積層部とによって構成し、何層も重ねる必要があ
る信号用配線を印刷積層部に形成し、電源用配線及び接
地用配線をグリーンシート積層部に形成した。(Means for Solving the Problems) In order to solve the above problems, the present invention configures a ceramic multilayer wiring board used as an IC package with a printed laminated part and a green sheet laminated part, and is used for signals where many layers need to be stacked. Wiring was formed on the printed laminated portion, and power wiring and ground wiring were formed on the green sheet laminated portion.
（作用）
信号用配線と電源用配線及び接地用配線が離れることで
浮遊容量が小さくなり、且つ信号用配線を印刷積層部に
形成することで全体の厚みを薄くできる。(Function) Stray capacitance is reduced by separating the signal wiring from the power supply wiring and the grounding wiring, and the overall thickness can be reduced by forming the signal wiring in the printed laminated portion.
（実施例） 以下に本発明の実施例を添付図面に基いて説明する。(Example) Embodiments of the present invention will be described below with reference to the accompanying drawings.
第１図は本考案に係るセラミック多層配線基板を適用し
たＩＣパッケージの全体斜視図、第２図は第１図のＡ−
Ａ線断面図、第３図は第２図の一部拡大図、第４図は第
３図のＢ−Ｂ線断面図である。FIG. 1 is an overall perspective view of an IC package to which a ceramic multilayer wiring board according to the present invention is applied, and FIG. 2 is an A--
3 is a partially enlarged view of FIG. 2, and FIG. 4 is a sectional view taken along line B--B of FIG. 3.
ＩＣパッケージはセラミック多層配線基板１の上面にＩ
Ｃチップ２の収納用の凹部３及びコンデンサー４の収納
用凹部５を連結して形成し、これら凹部３．５を塞ぐ蓋
体６がエポキシ樹脂等の接着剤７を介してセラミツク多
層配線基板１上面に貼着され、更にセラミック多層配線
基板１の一側には段部８を形成し、この段部８にクリッ
プ端子９・・・を取付けるようにしている。The IC package is mounted on the top surface of the ceramic multilayer wiring board 1.
A recess 3 for accommodating the C chip 2 and a recess 5 for accommodating the capacitor 4 are connected and formed, and a lid body 6 that closes these recesses 3.5 is attached to the ceramic multilayer wiring board 1 via an adhesive 7 such as an epoxy resin. A stepped portion 8 is formed on one side of the ceramic multilayer wiring board 1, and clip terminals 9 are attached to the stepped portion 8.
また、セラミック多層配線基板１はグリーンシートを積
層してなるグリーンシート積層部１０と印刷積層部２０
にて構成され、グリーンシート積層部１０は複数のセラ
ミックグリーンシート１１．１２．１３，１４．１５を
積層してなり、グリーンシート１１，１２．１３につい
ては予じめ窓部を打抜いて前記凹部３．５と成し、グリ
ーンシート１３上面にはボンディングフィンガ一部１６
を形成し、このボンディングフィンガ一部１６とＩＣチ
ップ２とを金線１７にて接続している。ここでボンディ
ングフィンガ一部１６はタングステンをメタライズした
部分にニッケルメッキを施し、このニッケルメッキの上
に金メツキを施すようにしている。The ceramic multilayer wiring board 1 also includes a green sheet lamination section 10 formed by laminating green sheets, and a printed lamination section 20.
The green sheet laminated section 10 is formed by laminating a plurality of ceramic green sheets 11, 12, 13, 14, 15, and the green sheets 11, 12, 13 are made by punching out window portions in advance. A recess 3.5 is formed, and a bonding finger portion 16 is formed on the upper surface of the green sheet 13.
This bonding finger portion 16 and the IC chip 2 are connected by a gold wire 17. Here, the bonding finger portion 16 is made by applying nickel plating to the metallized tungsten portion, and gold plating is applied to the nickel plating.
また、第４層となるグリーンシート１４上面にはダイア
タッチ部１８が形成され、第５層となるグリーンシート
１５上面には第４図に示すように、電源用配線１９ａ及
び接地用配線１９ｂがベタ層として形成され、更にグリ
ーンシート１５裏面には印刷積層法によって３．０ｍｍ
〜４０ｍｍ厚の印刷積層部２０を形成している。この印
刷積層部２０は信号用配線２０ａと絶縁層２０ｂをそれ
ぞれ３層づつ交互に重ねている。尚、各グリーンシート
に形成した導体間の導通は各グリーンシートを貫通して
穿設したスルーホールに充填した導体２１により行う。Furthermore, a die attach portion 18 is formed on the upper surface of the green sheet 14 that is the fourth layer, and a power supply wiring 19a and a ground wiring 19b are formed on the upper surface of the green sheet 15 that is the fifth layer, as shown in FIG. It is formed as a solid layer, and furthermore, on the back side of the green sheet 15, a layer of 3.0 mm is formed by a printing lamination method.
A printed laminated portion 20 having a thickness of ~40 mm is formed. This printed laminated portion 20 has three signal wirings 20a and three insulating layers 20b alternately stacked one on top of the other. Incidentally, conduction between the conductors formed on each green sheet is performed by a conductor 21 filled in a through hole formed through each green sheet.
そして、上記の如き構造のＩＣパッケージを製作する手
順としては例えば第５図の工程図に従って行う。The procedure for manufacturing an IC package having the above structure is performed, for example, in accordance with the process diagram shown in FIG.
尚、実施例にあっては４個のＩＣチップを収納する例を
示したがその数は任意である。また図示例にあっては電
源用配線１９ａと接地用配線１９ｂとを同一のグリーン
シート１５上面に形成したが、これら配線を異なるグリ
ーンシート上面に形成してもよい。Incidentally, in the embodiment, an example in which four IC chips are housed is shown, but the number is arbitrary. Further, in the illustrated example, the power supply wiring 19a and the grounding wiring 19b are formed on the top surface of the same green sheet 15, but these wirings may be formed on the top surface of different green sheets.
（発明の効果）
以上に説明した如く本考案によれば、セラミック多層配
線基板を印刷積層部とグリーンシート積層部にて構成し
、印刷積層部に信号用配線を形成し、グリーンシート積
層部に電源用配線及び接地用配線を形成したので、基板
の厚みを薄くしつつ浮遊容量を従来の１５０ピコフアラ
ツドから３０ピコファラッド程度まで減少でき、極めて
電気特性の優れた製品を得ることができる。(Effects of the Invention) As explained above, according to the present invention, a ceramic multilayer wiring board is composed of a printed laminated part and a green sheet laminated part, signal wiring is formed in the printed laminated part, and the green sheet laminated part is formed with a signal wiring. Since the power supply wiring and the ground wiring are formed, it is possible to reduce the stray capacitance from the conventional 150 picofarads to about 30 picofarads while reducing the thickness of the board, making it possible to obtain a product with extremely excellent electrical characteristics.
第１図は本発明に係るセラミック多層配線基板を適用し
たＩＣパッケージの全体斜視図、第２図は第１図のＡ−
Ａ線断面図、第３図は第２図の要部拡大図、第４図は第
３図のＢ−Ｂ線断面図、第５図は製作工程を示すブロッ
ク図である。
尚、図面中１はパッケージ本体、２はＩＣチップ、３は
凹部、６は蓋体、８は段部、１０はグリーンシート積層
部、１１，１２．１３，１４゜１５はグリーンシート、
１９ａは電源用配線、１９ｂは接地用配線、２０は印刷
積層部、２０ａは信号用配線である。
特 許 出 願人 東陶機器株式会社
代 理 人弁理士 下 １）容−即
問 弁理士 大 橋 邦 産量
弁理士 小 山 有第４
図
９ａ
９ａFIG. 1 is an overall perspective view of an IC package to which a ceramic multilayer wiring board according to the present invention is applied, and FIG. 2 is an A--
3 is an enlarged view of the main part of FIG. 2, FIG. 4 is a sectional view taken along line B--B of FIG. 3, and FIG. 5 is a block diagram showing the manufacturing process. In the drawings, 1 is the package body, 2 is the IC chip, 3 is the recess, 6 is the lid, 8 is the step, 10 is the green sheet stack, 11, 12, 13, 14, 15 is the green sheet,
19a is a power supply wiring, 19b is a grounding wiring, 20 is a printed laminated portion, and 20a is a signal wiring. Patent Applicant Totokiki Co., Ltd. Representative Patent Attorney 2 1) Yong - Immediate Question Patent Attorney Kuni Ohashi Production Volume
Patent Attorney Yudai Koyama 4 Figure 9a 9a
Claims (3)
ケージ等として用いるセラミック多層配線基板において
、このセラミック多層配線基板は印刷積層部とグリーン
シート積層部とからなり、印刷積層部には信号用配線を
形成し、この信号用配線と離れたグリーンシート積層部
には電源用配線及び接地用配線を形成したことを特徴と
するセラミック多層配線基板。(1) In a ceramic multilayer wiring board used as a multi-chip package etc. on which multiple IC chips are mounted, this ceramic multilayer wiring board consists of a printed laminated part and a green sheet laminated part, and signal wiring is formed in the printed laminated part. A ceramic multilayer wiring board characterized in that a power supply wiring and a grounding wiring are formed in a green sheet laminated portion separate from the signal wiring.
ンシート上に形成したことを特徴とする請求項１に記載
のセラミック多層配線基板。(2) The ceramic multilayer wiring board according to claim 1, wherein the power supply wiring and the grounding wiring are formed on the same green sheet.
用凹部を形成したことを特徴とする請求項１に記載のセ
ラミック多層配線基板。(3) The ceramic multilayer wiring board according to claim 1, wherein a recess for accommodating an IC chip is formed in the green sheet laminated portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63249439A JPH0297052A (en) | 1988-10-03 | 1988-10-03 | Ceramic multilayer interconnection board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63249439A JPH0297052A (en) | 1988-10-03 | 1988-10-03 | Ceramic multilayer interconnection board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0297052A true JPH0297052A (en) | 1990-04-09 |
Family
ID=17192986
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63249439A Pending JPH0297052A (en) | 1988-10-03 | 1988-10-03 | Ceramic multilayer interconnection board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0297052A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100420880B1 (en) * | 1999-06-02 | 2004-03-02 | 세이코 엡슨 가부시키가이샤 | Multichip Mounted structure, Electro-optical apparatus, and Electronic apparatus |
| JP2014002450A (en) * | 2012-06-15 | 2014-01-09 | Tokai Rika Co Ltd | Touch panel switch |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5640674B2 (en) * | 1973-12-08 | 1981-09-22 | ||
| JPS6022394A (en) * | 1983-07-18 | 1985-02-04 | 日本電気株式会社 | Circuit board |
-
1988
- 1988-10-03 JP JP63249439A patent/JPH0297052A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5640674B2 (en) * | 1973-12-08 | 1981-09-22 | ||
| JPS6022394A (en) * | 1983-07-18 | 1985-02-04 | 日本電気株式会社 | Circuit board |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100420880B1 (en) * | 1999-06-02 | 2004-03-02 | 세이코 엡슨 가부시키가이샤 | Multichip Mounted structure, Electro-optical apparatus, and Electronic apparatus |
| JP2014002450A (en) * | 2012-06-15 | 2014-01-09 | Tokai Rika Co Ltd | Touch panel switch |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4763188A (en) | Packaging system for multiple semiconductor devices | |
| US5831833A (en) | Bear chip mounting printed circuit board and a method of manufacturing thereof by photoetching | |
| JP3544974B2 (en) | Integrated laminate | |
| US4038488A (en) | Multilayer ceramic multi-chip, dual in-line packaging assembly | |
| US5661336A (en) | Tape application platform and processes therefor | |
| US5883428A (en) | Package for housing a semiconductor element | |
| JPS61108160A (en) | Semiconductor device with built-in capacitor and manufacture thereof | |
| US4748537A (en) | Decoupling capacitor and method of formation thereof | |
| JPS6355213B2 (en) | ||
| KR100647090B1 (en) | Semiconductor component with several semiconductor chips | |
| CN206195735U (en) | Encapsulation structure of sound surface wave filter | |
| EP0272046A2 (en) | Circuit arrangement including a composite ceramic substrate | |
| US6806563B2 (en) | Composite capacitor and stiffener for chip carrier | |
| EP1072058A2 (en) | Device for electronic packaging, pin jig fixture | |
| JPS5998543A (en) | Semiconductor device | |
| JPH0297052A (en) | Ceramic multilayer interconnection board | |
| JPH07142283A (en) | Capacitor and packaging structure using the same | |
| JP2581532B2 (en) | Semiconductor device | |
| JPS58220492A (en) | Composite circuit device | |
| JPH01500866A (en) | Trimming of passive components embedded in multilayer structures | |
| JPH05160334A (en) | Multilayer lead frame and capacitor parts used in between and semiconductor device | |
| JPS589585B2 (en) | Dense hinge lead frame | |
| JPH0297040A (en) | Ic package | |
| JPH02164096A (en) | Multilayer electronic circuit board and its manufacture | |
| JP3447025B2 (en) | Surface mounted electronic component and method of manufacturing the same |