JPH0296368A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To improve the reliability of a wiring with the scaling down and miniaturization of cell size by forming capacitance, shaping a single crystal semiconductor thin-film to the upper section of the capacitane and forming a selective transistor to the single crystal semiconductor thin-film. CONSTITUTION:A single crystal semiconductor thin-film 2 is isolated by dielectrics 4 and active regions are formed, transistors are shaped in each active region, and first conductor layers 18 for capacitance isolated at every active region through dielectric layers 16 are formed to the lower sections of each active region. A second conductor layer 22 for capacitance is shaped to the lower sections of the first conductor layers 18 through a dielectric layer 20 for capacitance and capacitance at every active region is formed, contact holes are shaped in the isolation regions of the single crystal semiconductor thin-film 2, and the selective transistors of the active regions and capacitance 20 under the active regions are connected through the contact holes. Accordingly, the capacitance 20 is formed to the lower sections of the active regions, to which the selective transistors are shaped, thus scaling down the size of a DRAM memory cell, then making a metallic wiring finer than the capacitance 20 is laminated to the upper sections of the active regions.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to semiconductor memory devices, particularly DRAM (Random Access Memory).

(Prior Art) Among DRAMs, a memory cell called a one-transistor type has a storage capacitor connected in series to one selection transistor.

In order to reduce the size of a memory cell, it is not enough to simply reduce the size of the selection transistor; it is also necessary to reduce the area occupied by the capacitor.

If the capacitor is formed on the same plane as the selection transistor, the area for the capacitor becomes large, making it impossible to reduce the size of the memory cell. Therefore, it has been proposed to form a capacitor on the inner wall of the trench by digging a trench in the substrate, or to form a capacitor in a stacked state above a selection transistor, a bit line, or an isolation region.

(Problem M to be solved by the invention) In a memory device in which a capacitor is stacked on top of a selection transistor, etc., the level difference on the surface becomes large in the later wiring process.
This makes it difficult to form fine wiring, which poses a problem in increasing the degree of integration.

Furthermore, if the capacitance is made to exceed a predetermined value, the area of the capacitor increases, which becomes an obstacle to reducing the cell area.

The present invention is a DRA that can reduce the cell size and improve the reliability of interconnects as miniaturization progresses.
The purpose is to provide M.

(Means for solving W problem) In the present invention, a capacitor is formed below the selection transistor.

Therefore, the present invention utilizes a single crystal semiconductor thin film. That is, after forming a capacitor, a single crystal semiconductor thin film is formed on the capacitor, a selection transistor is formed in the single crystal semiconductor thin film, and the capacitor and the selection transistor are connected through a contact hole.

That is, in the present invention, a single crystal semiconductor thin film is separated by a dielectric to form active regions, a transistor is formed in each active region, and a dielectric layer is provided below each active region to form active regions. A separated first conductor layer for capacitance is formed, and a second conductor layer for capacitance is formed below the first conductor layer via a dielectric layer for capacitance, thereby forming an active region. A contact hole is provided in the isolation region of the single crystal semiconductor thin film, and the selection transistor in the active region and the capacitor under the active region are connected through this contact hole.

(Operation) Charge is accumulated in the capacitor below the selection transistor, and the charge in the capacitance is read out via the selection transistor.

Since the selection transistor and capacitor are formed on different layers,
The size of memory cells is reduced.

(Example) Fig. 1 is a sectional view showing one embodiment, Fig. 2 is a plan view of the same embodiment, and Fig. 1 shows a state cut along the line A-A' in Fig. 2. There is. FIG. 3 is a sectional view taken along line BB' in FIG. 2.

2 is a P-type wheel crystal silicon thin film, and the film thickness is approximately 50 mm.
There are 00 people. The monocrystalline silicon thin film 2 is separated by a dielectric layer 4 such as a silicon oxide film. A source 8 and a drain 10 are formed on the surface side of the single crystal silicon thin film 2 by an N-type impurity diffusion region, and a gate electrode 12 made of polycrystalline silicon is formed on the channel region with a gate oxide film interposed therebetween. A transistor is formed.

A high melting point metal thin film layer 14 such as tungsten is formed at the bottom of the single crystal silicon thin film 2 to provide a substrate potential.

A conductor layer 18 patterned for each active region is formed below the single crystal silicon thin film 2 and the refractory metal thin film layer 14 with a dielectric layer 16 such as a silicon oxide film interposed therebetween. The conductor layer 18 is made of an N+ polycrystalline silicon layer whose resistance has been lowered by doping with impurities such as phosphorus.
The film thickness is, for example, 1,500 to 2,500 people. A conductor layer 22 is formed below the conductor layer 18 with a dielectric layer 20 such as a silicon oxide film interposed therebetween. The dielectric layer 20 is, for example, a silicon oxide film with a thickness of about 200 to 250 μm, and the conductor layer 22 is, for example, an N+ diffusion layer formed by implanting arsenic into the surface of a P-type (100) silicon substrate 24. be.

A capacitor is formed by the conductor layers 18, 22 and the dielectric layer 20 therebetween. In order to connect this capacitor to the source 8 of the selection transistor, a contact hole is formed in the isolation region, and a conductor 26, such as N+ polycrystalline silicon, is embedded in the contact hole.

An interlayer insulating film 28 such as a PSG film is formed over the selection transistor on the active region, and a metal wiring 30 is formed to be connected to the selection transistor through a contact hole.

Although the structure of the embodiment has been explained from the selection transistor downward, in order to manufacture this memory cell, it is formed from the bottom to the top in the figure.

Next, an example of a method for manufacturing the DRAM of this embodiment will be described.

Silicon substrate, for example P type (100) silicon substrate 24
Arsenic is implanted into the surface of the capacitor to form an N+ diffusion layer 22 which will become one electrode of the capacitor.

Next, the surface of this silicon substrate is oxidized by HCQ oxidation at 950°C to form a silicon oxide film 2 that will become a capacitor dielectric layer.
0 to a thickness of about 200-250 people. in addition,
A polycrystalline silicon layer with a thickness of approximately 1,500 ~
Deposit to a film thickness of 2,500 people. This polycrystalline silicon layer is made N+ type and has a low resistance by diffusing phosphorus. The polycrystalline silicon layer is patterned by photolithography and etching to form a conductor layer 18 that will become the other electrode of the capacitor.

Thereafter, a silicon oxide film 16 is formed as a dielectric layer by CVD or the like.

A high melting point metal film, such as tungsten, is formed on top of the silicon oxide film 16 by deposition or sputtering, and patterned by photolithography and etching to form the conductor layer 14.

Next, polycrystalline silicon is deposited thereon to a thickness of about 5 mm by the LPC:VD method to form a single-crystal silicon thin film 2. This single crystallization method will be explained later with reference to FIG.

If the thickness of the single crystal silicon thin film 2 does not reach a predetermined thickness, the thickness of the single crystal silicon thin film 2 may be increased by epitaxial growth after single crystallization.

In order to separate the single crystal silicon thin film 2 into cells, R
A trench is formed by etching using the IE method, and a silicon oxide film 4 is formed in the trench using a TE01 (tetraethoxysilane) method or the like to fill the trench.

Next, a contact hole reaching the conductive layer 18 is formed in a part of this isolation region, and a conductive material such as N+ polycrystalline silicon 26 is filled in the contact hole.

Thereafter, a selection transistor including a gate electrode 12, a source 8, and a drain 10 is formed according to a normal MOS process procedure. And the source 8 of the selection transistor
and the N+ polycrystalline silicon 26 buried in the contact hole are connected.

Thereafter, the formation of the first interlayer insulating film 28, metal wiring 30, passivation film, etc. follows conventional processes.

A method for forming the single crystal silicon thin film 2 will be explained with reference to FIG.

Generally, SOI is used to form the single crystal silicon thin film 2.
A technique known as (Silicon on In5ulator) can be used. Here, a method that can form a single-crystal silicon thin film over a wide area will be described.

Reference numeral 40 denotes a base, in this case, an N'' diffusion layer 22, a dielectric layer 20, a conductor M18, a dielectric layer 16, and a high melting point metal film 14 are formed on the surface of a silicon substrate 24.

Polycrystalline silicon film 42 is formed on base 40 by low pressure CVD method.
was deposited to a thickness of 5,000 to 1 μm, and then heated under reduced pressure C.
Silicon nitride film (Si3N4) 44 is deposited by approximately 8
Deposited to a thickness of 0.00 people. Further, a silicon oxide film 46 is deposited thereon to a thickness of approximately 1000 nm by low pressure CVD, and a polyethylene glycol layer 48 as a cooling medium is formed on the surface thereof. An optical glass plate 50 is placed on the polyethylene glycol layer 48.

After laminating the layers as shown in FIG. 4, for example, an argon ion laser beam 52 with an optical output of about 3 W is focused by a lens and irradiated onto the polycrystalline silicon film 42, and the laser beam 52 is scanned to remove the polycrystalline silicon film 42. The molten portion 54 is moved to cause crystal growth, thereby forming the single crystal silicon film 2.

Thereafter, the optical glass plate 50, polyethylene glycol layer 48, silicon oxide film 46, and silicon nitride film 44 are removed.

In the manufacturing process shown in FIG. 4, instead of the laser beam 52, other light beams, electron beams, heat rays, or other energy beams may be used.

In addition to polyethylene glycol 48, as a cooling medium,
Generally known surfactants such as polyethylene ether, polyethylene ester, and polypropylene oxide can be used.

Silicon oxide film 46 and optical glass plate 5o in FIG.
Although it is possible to form the single crystal silicon film 2 without it,
Polyethylene glycol 48 has better wettability when applied through silicon oxide film 46 than when directly formed on silicon nitride film 44, and by placing optical glass plate 50 on it, the thickness of polyethylene glycol layer 48 can be reduced. It can be made uniform.

FIG. 5 represents another embodiment.

The conductor layer that becomes the lower electrode of the capacitor buried under the selection transistor is an N+ diffusion layer in the embodiment shown in FIG. 1, but in the embodiment shown in FIG. A conductor layer 60 made of a high melting point metal or the like is used. 62 is a substrate, and 64 is a dielectric layer.

In the embodiment shown in FIG. 5, the substrate 62 is not limited to a silicon single crystal substrate, and various substrates such as a ceramic substrate can be used.

In the embodiment shown in FIG. 1 or FIG. 5, the conductor layer serving as the electrode of the capacitor buried under the selection transistor and the conductor layer for taking out the substrate potential of the selection transistor are as follows:
Any material selected from polycrystalline silicon with reduced resistance, tungsten, molybdenum, and other high melting point metals can be used.

The dielectric layer 20 constituting the capacitor is not limited to the silicon oxide film as in the embodiment, but may be a silicon nitride film, or may have two or more dielectric layers.

(Effects of the Invention) In the present invention, since the capacitor is formed below the active region where the selection transistor is formed, the size of the DRAM memory cell can be reduced, and when the capacitor is stacked above the active region, it is possible to reduce the size of the DRAM memory cell. In comparison, metal wiring can be made finer, which is effective in increasing the degree of integration of memory cells.

In addition, contact areas with metal wiring are provided in the upper part of the active region, which limits the area for forming capacitors and limits the ability to increase capacitance. There are fewer constraints and therefore capacity can be increased.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing one embodiment, and FIG. 2 is a plan view of the same embodiment, and FIG. 1 shows a state cut along the line AA' in FIG. FIG. 3 is a sectional view taken along line BB' in FIG. 2. FIG. 4 is a sectional view illustrating a method of forming a single crystal silicon thin film, and FIG. 5 is a sectional view showing another embodiment. 2... Single crystal silicon thin film, 4... Separation dielectric, 8... Source, 10...
Drain, 12...Gate electrode, 16...
...Dielectric layer, 18, 22, 60... Conductive layer for capacitance, 20... Dielectric layer for capacitance, 26...
...Conductor for connection. Figure 1

Claims (1)

[Claims] (1) A single crystal semiconductor thin film is separated by a dielectric to form active regions, a transistor is formed in each active region, and each active region is separated by a dielectric layer below the active region. A first conductive layer for capacitance is formed under the first conductive layer, and a second conductive layer for capacitance is formed via a dielectric layer for capacitance to form a capacitance for each active region. A semiconductor memory device in which a capacitor is formed, a contact hole is provided in the isolation region of the single crystal semiconductor thin film, and a selection transistor in an active region and a capacitor under the active region are connected through the contact hole.