JPH0296247A - Malfunction preventing circuit - Google Patents

Abstract

PURPOSE:To prevent the malfunctions of a microcomputer, etc., by using a circuit which produces a clear signal when at least one of outputs of (n) pieces of dummy registers is inverted and at the same time allocating these dummy registers at the periphery of a pad of a chip. CONSTITUTION:When just one of dummy registers 4 is inverted to 1 by the electrostatic noise, a malfunction detecting signal 6 becomes active to sets again a microcomputer in its initial state. Then a clear signal 2 is produced by a clear signal generating circuit 7 and all registers 4 are cleared to 0. Thus the signal 6 is inactive again and no signal 2 is produced any more. The registers 4 are set at the periphery of a pad 9 of a chip 8 to easily receive the effect of the electrostatic noise. Thus the overall monitor is possible to the chip 8.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a malfunction prevention circuit for microcomputers and the like, and more particularly to a malfunction prevention circuit built into a microcomputer chip and provided with electrostatic noise countermeasures.

[Conventional technology]

Conventionally, in this type of microcomputer, a watch dog timer is used to detect malfunction and perform control to return the microcomputer to its initial state.

FIG. 3 is a block diagram of a malfunction prevention circuit for explaining an example of such a conventional system.

As shown in FIG. 3, the conventional operation prevention circuit uses a watch dog timer 11. That is, a watch dog timer 11 built in a microcomputer (hereinafter referred to as microcomputer) or connected externally is cleared by a clear signal 12 at regular intervals under software control. If the timer 11 is not cleared, the watch dog timer 11 overflows and generates a malfunction detection signal 13. As a result, it is determined that the microcomputer has gone out of control, and the microcomputer is reset to its initial state.

[Problem to be solved by the invention]

The conventional malfunction prevention circuit described above resets the microcontroller to its initial state when the software runs out of control, so for example, if the software does not run out of control and only the input/output switching mode register of the board malfunctions due to electrostatic noise, etc. That is, in the case of a malfunction such as when the mode register changes from input mode to output mode, there is a drawback that the microcomputer cannot be reset to its initial state.

An object of the present invention is to provide a malfunction prevention circuit that can detect malfunctions caused by such electrostatic noise and reset the microcomputer to its initial state.

[Means to solve the problem]

The malfunction prevention circuit of the present invention is a malfunction prevention circuit for a microcomputer mounted on a chip, and includes a first logic circuit that inputs a reset signal and a clear signal, and an arbitrary circuit connected to the output terminal of the first logic circuit. When inputting n dummy registers (n = positive integer) that are fixed to logical values and cannot be written to, and the output of each of the dummy registers, and at least one output of the n registers is inverted, a second logic circuit that generates a malfunction detection signal;
a clear signal generation circuit that generates a clear signal for the first logic circuit based on the malfunction detection signal;
dummy registers are arranged around the pads of the chip.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a malfunction prevention circuit for explaining one embodiment of the present invention.

As shown in FIG. 1, the malfunction prevention circuit of this embodiment includes a first logic circuit 3 which receives a reset signal 1 and a clear signal 2 and takes NOR logic, and an arbitrary logic circuit 3 which inputs the NOR output. Unwritable n fixed to
dummy registers 4 (n is a positive integer), a second logic circuit 5 that takes the NOR logic and inverter logic of the output of each dummy register 4 and outputs a malfunction detection signal, and a second logic circuit 5 that outputs a malfunction detection signal. A clear signal generation circuit 7 generates a clear signal 2 which is one input of one logic circuit 3.The dummy registers 4 are arranged around pads of the chip, which will be described later. The operation of the prevention circuit will be explained below.

First, when the reset signal 1 input to the first logic circuit 3 is released, the n dummy registers 4 are fixed to 0''. Therefore, the malfunction detection signal 2 does not become active, and therefore The clear signal 2 from the clear signal generation circuit 7 is not generated.Next, if even one of the dummy registers 4 is inverted to "1P" due to electrostatic noise etc., the malfunction detection signal 6 becomes active and the microcontroller is reset to the initial state. At the same time, the clear signal 2 is sent to the clear signal generation circuit 7.
This occurs, so set all dummy registers 4 to ``0''.
Clear to. Since all the dummy registers 4 are cleared, the malfunction detection signal 6 becomes inactive again, and the clear signal 2 is no longer generated.

FIG. 2 is a layout diagram in which dummy registers of the malfunction prevention circuit shown in FIG. 1 are arranged on a chip.

As shown in FIG. 2, the dummy register 4 of the malfunction prevention circuit is arranged on the chip 8 near (around) a pad 9 provided around the chip 8. Note that IO indicates an output buffer circuit.

The reason why the above-mentioned dummy resistor 4 is arranged around the pad 9 is that it is particularly susceptible to the influence of electrostatic noise.

In short, the malfunction prevention circuit of this embodiment generates the malfunction detection signal 6 to reset the microcomputer to its initial state when even one of the dummy registers 4 reverses its operating state due to electrostatic noise or the like. Moreover, the plurality of dummy registers 4 are arranged around the pads 9 of the chip 8 which are susceptible to electrostatic noise, etc., so that the entire chip 8 can be monitored.

〔Effect of the invention〕

As explained above, the malfunction prevention circuit of the present invention provides a dummy register that inputs the logic outputs of the reset signal and the clear signal, and by arranging the dummy register around the pad of the chip, static electricity can be prevented. Even if there is a malfunction that does not result in runaway due to noise, etc., if the contents of the dummy register are inverted, a malfunction detection signal can be generated and the initial state can be reset, so malfunctions of the microcontroller, etc. can be reliably prevented. There is an effect that it can be done.

1...Reset signal, 2...Clear signal, 3...
First logic circuit, 4... Dummy register, 5... Second logic circuit, 6... Malfunction detection signal, 7... Clear signal generation circuit, 8... Chip, 9... pad, 1
0...Output buffer circuit.

Agent Patent Attorney Uchihara Fees

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a malfunction prevention circuit for explaining one embodiment of the present invention, FIG. 2 is a layout diagram of dummy registers arranged on a chip in the malfunction prevention circuit shown in FIG. 1, and FIG. FIG. 2 is a block diagram of a malfunction prevention circuit for explaining a conventional example.

Claims (1)

[Claims] In a malfunction prevention circuit of a microcomputer mounted on a chip, a first logic circuit inputs a reset signal and a clear signal, and a write terminal connected to an output terminal of the first logic circuit and fixed to an arbitrary logic value. n dummy registers (n = positive integer), and a second device that inputs the output of each of the dummy registers and generates a malfunction detection signal when at least one output of the n registers is inverted. and a clear signal generation circuit that generates a clear signal for the first logic circuit based on the malfunction detection signal, and the n dummy registers are arranged around pads of the chip. Malfunction prevention circuit.