JPH0296210A - Input/output circuit - Google Patents

Abstract

PURPOSE:To attain the data communication of the wired logic without using any special input/output circuit by connecting an output terminal to a data bus via an input terminal of an IC and a resistance. CONSTITUTION:When '1' is outputted to an output terminal 6 of an IC1, a resistance 7 is pulled up. That is, the data are transferred from the ICs except the IC1, the data on '1' is transferred from the IC1 or no data is transferred. Under such conditions, a data bus 8 is set at '0' as long as one of input/output terminals of the IC10 and 14 is equal to '0'. While the bus 8 is set at '0' via the resistance 7 regardless of the logic of the input/output terminals 9 and 18 of the IC10 and 14 as long as '0' is outputted to the terminal 6. Then the data on '0' is transferred from the IC1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an input/output circuit, and particularly to an input/output circuit that transfers wired logic data between a plurality of ICs.

[Conventional technology]

Conventionally, this type of input/output circuit has three
Wired logic data communication is performed between the ICl00, 109, and 114.

In FIG. 3, input/output terminals 104. of ICl00, 109, 114. ], 08, 113 are commonly connected to form a data bus 107, and the first power supply line 1 is connected via a resistor 106.
The configuration is pulled up to 05. each I
The internal circuits of Cl00, 109° 114 input the logic of the input/output terminals 1042108 and ilB, respectively, and the input terminals 101. ．． 110
Input buffer 102111 for input to @1151
．． 116, and output transistors 103112.117 for outputting the logic of output terminals 101b, 110b, 115b of internal logic circuits 101, 110.115 to each input/output terminal 104.108 113, respectively.

FIG. 4 is a diagram showing the relationship between data transfer direction and truth value for explaining the operation of the input/output circuit of FIG. 3.

The operation of the input/output circuit shown in FIG. 3 will be explained below with reference to FIG. In FIG. 4, "1°" indicates the potential of the power supply line 105, 0'' indicates the source potential of each output transistor 103, 112, 117, and DAT
A indicates the desired data value, depending on the direction of data transfer,
The conditions are classified into seven types, as shown in Figure 4.

As is clear from this, the ICs that receive data and the ICs that are not involved in data transfer use their internal logic circuits to set their output transistors in a non-conducting state so that the data bus 107
, and only the IC that transmits data makes its output transistor conductive or non-conductive using its internal logic circuit, thereby executing data transfer.

That is, the logic of the data bus 107 is
. Although the number of ICs is assumed to be several, there is no particular restriction on the number of ICs as long as they are plural.

[Problems to be Solved by the Invention] In the conventional input/output circuit described above, when transmitting and receiving data, it is necessary to specifically transfer data based on a specific communication protocol. For example, a microprocessor is used with one control function.

Now, the first IC 100 is a microprocessor,
Suppose you want to control data communication. At this time, the first IC
100, i.e. the microprocessor has an input buffer 10
2 and an output transistor 103, or a so-called three-state buffer having a high impedance state.

However, there is no problem if the microprocessor is specially designed to be able to control communication of wired logic, but if a general-purpose microprocessor is used, an oven train type input/output circuit is required. This is generally rare, and the use of a limited number of three-state type input/output ports has the disadvantage of causing limitations in application.

The purpose of the present invention is to enable a general-purpose microprocessor to perform this type of wired logic communication using only ordinary input and output terminals, without using special oven train type input/output circuits or three-state buffers. The objective is to provide input/output circuits that

[Means to solve the problem]

The input/output circuit of the present invention includes a first IC having a control function based on a preset communication protocol, and respective input/output terminals operated under the control of the first IC connected to a common data bus. In an input/output circuit that includes a plurality of second ICs and mutually transfers data, the first IC has an input terminal connected to the data bus and an output connected to the data bus via a resistor. It has a terminal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

As shown in FIG. The input terminal 5 of C1 and the input/output terminals 9, 18 of the second ICs 10, 14 are commonly connected to form a data bus 8, and the output terminal 6 of the ICI is further connected to the data bus 8 via a resistor 7. It has become.

The internal circuit of the ICI has an input buffer 3 that provides the logic of the input terminal 5 to the input terminal 2a of the internal logic circuit 2, and an output buffer 4 that outputs the logic of the output terminal 2b of the internal logic circuit 2 to the output terminal 6. are doing.

ICl0, 14 are each configured to include input/output terminals 9, 18, input buffer 12.16, internal logic circuit 1115, and output transistor 13.17. In addition, IC
l0.14 performs an operation equivalent to the ICs 109 and 114 in FIG. 3 described above.

FIG. 2 is a diagram showing the relationship between the data transfer direction and the truth value for explaining the operation of the embodiment of FIG. 1. The operation of the embodiment shown in FIG. 1 will be explained below with reference to FIG.

As shown in FIG. 2, as in the case of FIG. 4 described above, the state is divided into seven states depending on the data transfer direction. As is clear from FIG. 2, logic circuits 2. ．． 11.
15 output terminals 2b, llb.

15b is the output terminal 10lb of the internal logic circuits 101, 110, 115 of the input/output circuit shown in FIG.

It is controlled in exactly the same way as 110b and 115b, and performs the desired operation.

Here, the difference in operation from the conventional example is that the logic of the output terminal 2b of the internal logic circuit 2 is applied to the data bus 8 via the output buffer 4 and the resistor 7. That is, output terminal 6
When "1" is output, the resistor 7 is isometrically in a pull-up state, and data transfer from other than IC1, data transfer of 1"' from IC1, or no data transfer is possible. It is.

In this state, if even one of the input/output terminals of ICl0, 14 is "0", the data bus 8 becomes "0". Also, when “0°” is output to the output terminal 6, the IC
Regardless of the logic of the input/output terminals 9 and 18 of l0 and 14, the data bus 8 becomes "0" through the resistor 7, resulting in data transfer of "0" from the ICI. That is, the embodiment shown in FIG. 1 is capable of wired AND logic data transfer similar to the input/output circuit shown in FIG.

〔Effect of the invention〕

As explained above, the present invention provides the first IC on the data bus.
By connecting the input terminal and the output terminal through the resistor, wired logic data communication is possible without using a special open train type input/output circuit or three-state input/output circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
3 is a block diagram of an example of a conventional input/output circuit, and FIG. 4 is the input/output circuit of FIG. 3. FIG. 2 is a diagram showing the relationship between data transfer direction and truth value for explaining the operation of FIG. 1.10,14,100,109,114...IC1
2,11,15,101,110,115...Logic circuit, 3.12.16,102,111゜116...Input buffer, 4...Output buffer, 5...Input terminal,
6...Output terminal, 9,18,104゜108.113
...Input/output terminal, 7,106...Resistor, 8,107
...Data bus, 13, 17, 103.112, 11
7... Output transistor, 105... Power supply line. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] The first one has a control function based on preset communication rules.
and a plurality of second ICs whose respective input/output terminals are connected to a common data bus and which operate under the control of the first IC, and which mutually transfer data, An input/output circuit characterized in that the first IC has an input terminal connected to the data bus and an output terminal connected to the data bus via a resistor.