JPH029513B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image information processing device, and in particular to image information processing for combining image information created using an arithmetic processing device such as a microcomputer with reproduced video information reproduced from a recording medium. Regarding equipment. Conventional image information processing devices for image synthesis synthesize signals at the video signal stage,
Various devices exist for switching and creating composite video signals. A schematic block diagram of the synthesizer according to FIGS. 1A-E is shown. In FIG. 1A, for example, a color video signal source 101 and a monochrome (black and white) video signal source 10 are shown.
2 are synchronized by the vertical and horizontal synchronizing signal rates by the synchronizer 103 and mixed by the adder 104. In FIG. B, two color video signal sources 101 and 105 are
In this method, a synchronizer 103 performs time axis correction at a subcarrier signal rate to achieve synchronization, and a video switcher 106 selectively derives the signals as appropriate to synthesize a color image. In FIG. C, two video signal sources 101,
For the signal of one source 105 among 105,
This is a method in which the other signal source 101 is synchronized by a synchronizer 103 and selectively derived by a switch 106. In FIG. D, for example, there are two VTRs (video tape recorders) 107 and 108.
The reproduced video signals are subjected to time axis correction at the subcarrier signal rate using TBCs (time base collectors) 109 and 110, phase synthesis is performed, and then selectively outputted by a switch 106. Furthermore, in the one shown in FIG.
Digitized by TBC113 and TBC11 respectively.
4, the synthesizer 1
Digitally synthesized using 15. After that, a D/A (digital-to-analog) converter 116 converts the signal into an analog video signal. In this way, conventional synthesis methods basically
The video may be synthesized at the video format stage before being input to a disk display device such as a CRT (cathode ray tube), or it may be digitized using a high-speed A/D converter and synthesized after arithmetic processing. Since the conventional device is configured as described above, extremely accurate time axis correction is required. Furthermore, when compositing color signals, even the slightest phase error appears as hue fluctuation, so accurate phase matching must be performed, and malfunctions may occur due to temperature characteristics, changes over time, etc. . Furthermore, in order to prevent these adverse effects, many compensation circuits are required, resulting in an increase in cost and a decrease in reliability due to an increase in the number of parts. The present invention has been made in view of the above-mentioned drawbacks of the prior art, and an object of the present invention is to provide an image information processing device capable of image synthesis with an extremely simple configuration. The image information processing device according to the present invention synthesizes an image of first image information in the form of a composite video signal and second image information that has been subjected to arithmetic processing by an arithmetic processing device (including a microcomputer, etc.) and displays an image. The object is a device that displays information on an image processing device, and includes a conversion means for converting first image information into three component signals corresponding to the three primary colors of light for display on an image processing device, and a conversion means for this conversion means. It is characterized by having a switching means for selectively switching between the output and the second image information and supplying the same to the image display device. Embodiments of the present invention will be described below with reference to the drawings, but in order to facilitate understanding of the present invention, a case where the present invention is applied to a video game will be described. FIG. 2 is a schematic block diagram of a video game device constructed using the present invention, in which a person playing the game makes decisions according to the image displayed on the image display device 1, and controls switches and potentiometers according to the judgment. Operate the information input device 2 configured with a meter or the like.
The information obtained by this input device 2 is sent to a decoder 3
The signal is converted into a signal format that can be processed into digital information, and is supplied to a control device 4 comprising, for example, a microcomputer. This microcomputer 4
The main configuration is a CPU (central processing unit) 5,
The information supplied by the decoder 3 is processed based on a program stored in advance in a storage means 6 such as a ROM (read only memory). CPU
5 composes the results of predetermined arithmetic processing into an image displaying the game development, and sends the arithmetic results to the video generator 8. The information processed by the CPU 5 in accordance with the signal from the decoder 3 according to the program is primary display information that directly contributes to the development of the game, and secondary display image information that does not directly contribute to the development of the game. Preferably, as external memory, for example VDP
(Video Disc Player) 9 is now used. The secondary image information recorded in this VDP9 includes background images, message information, etc. that do not directly contribute to the development of the game, and this information is a video format signal (a signal in the form of a composite video signal).
is FM modulated and recorded on a video disc. The VDP output as external memory 9 is supplied to demodulation circuit 10 . The external memory device 9
The operation is controlled according to a control signal from the CPU 5. The output of the demodulation circuit 10 is supplied to a video generator 8 and a detector 11. Detector 11
Furthermore, the output of the reference signal generation circuit 12 and
A timing signal from CPU5 is input.
On the other hand, a synchronization signal of reproduced color video information is output from the demodulation circuit 10 and supplied to the CPU 5. The operation will be explained in detail below. The FM color video signal reproduced from the video disc is sent to the demodulation circuit 10.
Once the FM demodulation is carried out within the system, and the synchronization signal is separated, this synchronization signal is decoded into an appropriate form.
External memory device 9 by supplying to CPU 5
The aim is to establish synchronization between the output and the output processed by the CPU. Furthermore, in the demodulation circuit 10, the color video signal is converted into three primary colors of video, R (red) and G.
(green) and B (blue) component signals. The separated RGB component signals are
is supplied to the video generator 8, where the CPU
The image information is combined with the image information calculated in step 5 and displayed on the image display device 1. On the other hand, the RGB component signal is further supplied to the detector 11, and the reference signal generation circuit 12
The hue of the image at a predetermined timing supplied from the CPU 5 is detected by comparison with a reference signal from the CPU 5. Furthermore, in the video generator 8, the output of the demodulation circuit 10 and the calculation output from the CPU 5 are directly combined. FIG. 3 shows a specific example of the configuration of the detection circuit 11. That is, the RGB component signals output from the demodulation circuit 10 are respectively supplied to the first gate array 13 constituted by AND gates 13a to 13h connected in parallel. Inputs are input to each gate 13a to 13h via an inverter in the required order, and one of the AND gates 13a to 13h is set to logic "1" according to the pattern of RGB information represented by the RGB component signal. , and all other gates output logic "φ". The outputs of the AND gates 13a-h are as shown in the truth table at the end of the detailed description. Each output of the first gate array 13 is supplied to one input terminal of AND gates 14a to 14h constituting the second gate array 14, respectively. The output of the reference signal generation circuit 12 is supplied to the other input terminals of the AND gates 14a to 14h. The output pattern of the reference signal generation circuit 12 is determined by a control signal from the CPU 5. All the output terminals of the AND gates 14a to 14h are connected to the input terminal of the OR circuit 15,
The output of the OR circuit 15 is supplied to the other input of an AND gate 16 which receives the timing information signal from the CPU 5 as one input. This and gate 16
The output of is supplied to the CPU 5 as a command signal. Next, an example of the operation of this detection circuit will be explained. For example, when the external memory 9 is outputting color video information corresponding to red, the demodulation circuit 10
represented by RGB component output
The RGB information becomes the pattern shown by A in the truth table above. Therefore, only the AND gate 13d of the first gate column 13 outputs logic "1", and all the other AND gates output logic "φ". here
Depending on the control signal from the CPU 5, only the output of the reference signal generation circuit 12 that is supplied to the AND gate 14d is set to logic "1", and the others are set to logic "φ".
If we make it correspond to the AND gate 14d
The logic is established and a logic "1" is output. If the output of the reference signal generation circuit 12 is maintained in this state, each time the external memory 9 outputs information corresponding to the color red, the output corresponding to logic "1" from the OR circuit 15 becomes one input of the AND gate 16. Supplied. The output pattern of the reference signal supply means 11 is controlled according to the color to be detected. Here, from the other input of the AND gate 16, the CPU
A signal corresponding to logic "1" is supplied only for a predetermined period determined and output by the circuit 5. When the AND gate 16 outputs a signal corresponding to logic "1", a command signal is supplied to the CPU 5, and the CPU
5, predetermined processing is performed. The output from the demodulation circuit 10 is combined with image information from the CPU 5 in the video generator 8 by a video switch 17 as shown in FIG. That is, the switch elements 17a to 17c in the switch 17 normally select the RGB component signal side supplied from the demodulation circuit 10, but when any of the RGB component signals is supplied from the CPU 5, this is changed. The OR circuit 18 detects and each element 17a to c during this period.
The switch is made to select the RGB component signal from the CPU 5. Note that the control signal is sequentially supplied to the reference signal generation circuit 12 at regular intervals, and the AND gates 14a to 14 are sequentially supplied to the reference signal generation circuit 12.
If the input of 4h corresponds to logic "1" and the timing signal supplied to AND gate 16 corresponds to logic "1" for that period, AND gate 1
The color at that time can be detected by the timing at which the output No. 6 is generated. Further, as the output of the reference signal generation circuit 12, a plurality of signals corresponding to logic "1" may be supplied to the second gate array 14. A game device to which the present invention is applied will be explained in more detail with reference to the drawings. FIG. 5 shows a screen reproduced on the image display device 1 based on image information supplied from the external memory device 9. As shown in FIG. Targets 19a-d appearing on the screen
Each has a different color and moves randomly over time. The colors of the targets 19a-d are also different from the background color.
FIG. 6 shows a screen created from the image information supplied by the CPU 5, with a score display section 20a showing the score at the upper left corner and a cursor section 20b at the center. The score display section 20a displays the scores obtained as the game progresses, and the cursor section 20b displays the points obtained as the game progresses.
It is possible to move freely on the screen by operating the input device 3. Figure 7a shows the image of the external memory device 9 and the CPU 5.
The images from the above are synthesized by the synthesis circuit shown in FIG. Now, regarding the scanning line X, for example, if the target 19c is red, the RGB component signals of the demodulation circuit 10 will be as shown in FIGS. 7b to 7d. Now, when the output of the reference signal supply means 12 is set to detect red color, an output signal is obtained from the OR circuit 15 as shown in FIG. 7e, and is supplied to one input of the AND gate 16. has been done. Here, depending on the position of the cursor 20b, the CPU
5, the timing signal (FIG. 7f) is supplied to the other input of the AND gate 16, but the OR circuit 1
Since the logic does not hold with the output signal of 5, no command signal is generated (see Figure 7g). On the other hand, as shown in FIG. 8a, when the cursor section 20b is positioned on the target 19c, the timing of generation of the timing signal (see FIG. 8f) changes, and a command signal is obtained (see FIG. 8g). . This command signal is supplied to the CPU 5, the score of the game is counted, and the score displayed on the score display section 20a changes (see FIG. 8a). It is also possible to detect colors using the method described above and change the score value for each target. Similarly, it is also possible to configure the game so that the game ends when the cursor portion 20b hits a target of a specific color. Further, in the above embodiments, a video game device has been described, but the same applies to learning devices and the like. For example, Japanese Patent Application Publication No. 54-157027 (Patent Application No. 53-65371)
When inputting the answer to a question using a device such as that described in Figure 9, targets 21a to 21c of different colors are displayed in front of the selection options, as shown in Fig. It is possible to have the CPU confirm the answer of the answerer, depending on whether the answer is correct or not. Furthermore, the information obtained from the external memory device may be color video information with arbitrary brightness, brightness, and saturation, and in the case of color video information with arbitrary brightness, brightness, and saturation, the information obtained from the demodulated RGB component signal It is sufficient to slice the level at a predetermined comparison level and supply it to the detection circuit. As described above, according to the present invention, as shown in FIGS. 2 and 4, two pieces of image information to be combined are selected not as video format signals but as three types of component signals corresponding to the three primary colors. Since the configuration is such that images are synthesized by switching and outputting signals, there is no need for accurate phase alignment through time axis correction at the color subcarrier signal rate.
Image synthesis becomes possible extremely easily, and the device can be expected to be smaller, lower in price, and more reliable, and this type of image information processing device can be widely used in consumer equipment. Additionally, the color of the image based on the component signal generated by the arithmetic processing device or the like is not affected by the component signal obtained by demodulating the composite video signal. The composite output obtained by the present invention (the R, G, and B outputs of the video switch 17 in FIG. 4) is composed of three component signals corresponding to the three primary colors, so it can be used as a CRT drive signal. It can be used as is. Furthermore, it goes without saying that the configuration of the above embodiment can be modified in various ways. 【table】

[Brief explanation of drawings]

Fig. 1 is a block diagram of various conventional image synthesis devices, and Fig. 2 is a diagram of a video game to which the present invention is applied.
FIG. 3 is a diagram showing an example of a detection circuit in the block of FIG. 2, FIG. 4 is a circuit diagram of an embodiment of the present invention, and FIG. 5 is an example of an image display from an external memory. FIG. 6 is a diagram showing a mode of image display from the CPU, and FIGS. 7 to 9 are diagrams explaining one mode of a composite image. Explanation of symbols of main parts, 1...Monitor, 5...
CPU, 8...Video generator, 9...VDP,
10... Demodulation circuit, 17... Video switch.

Claims (1)

[Scope of Claims] 1. A component signal forming means for forming a generated component signal in synchronization with a synchronization signal included in a composite video signal, a converting means for demodulating the composite video signal and converting it into a demodulated component signal, An image information processing device comprising: switching means for selectively switching between the generated component signal and the demodulated component signal and supplying the signal to an image display device. 2 The switching means selectively outputs the generated component signal when at least one of the generated component signals means the presence of image information, and selectively outputs the demodulated component signal when the remaining component signals exist. The image information processing apparatus according to claim 1, wherein the image information processing apparatus is configured to perform the following operations.