JPH0295010A - Malfunction monitoring circuit for m series generating circuit - Google Patents

Abstract

PURPOSE:To detect a loop period from the time point of a loop is started by holding initial data in the internal part of the loop, and monitoring a loop internal part condition. CONSTITUTION:FF a3 and a4 are latch circuits to execute the initial set value holding for comparison. Data 1 and 2 which are initial set values are latched to FF a3 and a4 and one of the latched data is used as the set data with FF a1 and a2 of a loop and one of them is used as the compared data with an output Q of the FF a1 and a2 of the loop. Thus, since the comparison with the initial data is executed, the loop period from the time point of the loop is started.

Description

[Detailed Description of the Invention] This invention relates to a method of detecting a loop period in a loop that generates an M sequence, and a method of using the detection signal to detect loop periods in a plurality of loops and detecting malfunctions in each loop. .

(b) Prior art and problems Conventionally, in the M-sequence generation loop, one cycle detection is performed using, for example, the number of stages of the M-sequence n as a feature of the M-sequence pattern.
Then, "0" does not occur consecutively n or more times, and (n
-1) Utilize the fact that they occur consecutively.

The number of times is once in one cycle of the M sequence. Therefore, if you monitor "0" during the output turn and count "0", M
It is possible to detect the cycle of sequence loops and malfunctions.

FIG. 5 shows a conventional circuit using a method of counting "0" during output turn.

The two-stage M-sequence generation circuit EXORs the outputs Q of NFF a 1 and a2 with b and feeds them back to the D input of FFal.

In the case of a two-stage M sequence, "0" does not occur two or more times in succession, but "0" occurs once in one cycle. C in Figure 5 counts these "0"s, and a loop detection signal is a detection signal that indicates that the loop has operated once with one "0", and a loop detection signal that indicates that the loop has malfunctioned with two or more "0s". The configuration is configured to output a loop error signal which is a detection signal indicating that the

The "0" count circuit needs to change the count number depending on the number of stages of the M series.

A signal loop detection indicating that the loop has operated one cycle does not become a detection signal indicating that the loop has operated one cycle from the time the loop started.

(C) Purpose of the Invention It is an object of the present invention to monitor the internal state of the loop and detect the loop cycle from the time of initial setting by retaining the initial data inside the loop. Furthermore, by monitoring the loop period of each loop, the purpose is to monitor the entire loop period and loop malfunctions.

(d) Embodiment of the Invention In FIG. 1, there is shown a two-stage M
An embodiment of a loop operation detection circuit of a sequence generation circuit is shown.

At-a4 in Figure 1 is FF1bl ~ b3 are switches,
d is OR.

The FFs of al and a2 and the EXOR of cl in FIG. 1 are a two-stage M-sequence generation circuit.

Depending on the select signal, switch b1 inputs A, switch b
If the A input is set to 2 and the A input is outputted from Q by switch b3, the output Q of FFa2 is EXORed with the output Q of FFa 1 and EXORc 1, and the D of FFa 1 is
is input. Also, the output Q of FFal is F Fa
It is input to D of No. 2 and becomes a loop with three clocks as one cycle.

FFs a3 and a4 in FIG. 1 are latch circuits that hold initial setting values for comparison. The initial setting values, data 1 and 2, are
The data is latched into the FFs a3 and a4 by the data latch pulse. One of the latched data is the loop's FFal
One of the setting data for and a2 is loop FFal and a2.
The configuration is such that it is used as comparison data with the output Q of.

When data is set to the loop, the B input is outputted from the Q by the switches b1 to b3 using the select signal.

Data 1 is latched into FFa3, selected by switch b1, and becomes the D input of FFa1. Similarly,
Data 2 also becomes the D input of FFa2. Here, FFal is set by the data set pulse selected by switch b3.
and data is set in a2.

During loop operation, as described above, if the select signal is used to output the A input from Q at switches bl-b3, FFal and a2 form a loop, and switch b3
It operates with the clock selected by.

The outputs Q of FFal and a2 are always compared with initial value data 1 and 2 and EXORc 1 and C3.

Each EXOR c1 and c3 becomes L only when outputs equal to data l and 2 are output from FFs al and a2.

FIG. 2 shows a time chart during loop operation when data 1.2 is set to "1".

One cycle from the start of the loop is detected by the loop detection signal.

Next, an embodiment of a plurality of loop operation detection and loop error detection circuits using the above-described loop operation detection circuit will be described.

FIG. 3 shows an embodiment with four loops.

Here, the loops to be detected are limited to those with the same period.

The loop detection signal of each loop becomes an all-loop detection signal by ORa 1, which indicates that all the loops are making one revolution at the same time.

Further, the detection signal of each loop is compared with a certain loop detection signal by EXORb1 to b3.

Normally, when each loop starts at the same time and operates at a constant cycle, the loop detection signals 1 to 4 of each loop have the same pattern (section C of the time chart in Figure 4).
. Therefore, the output of EXORbl-b3 remains at L, and the loop error signal also remains at L.

If an abnormality occurs in the loops and the loops do not start at the same time (section C of the time chart in Figure 4), the loop detection signals 1 to 4 of each loop will be different, and E
The outputs of XORbl-b3 become H, and the loop error signal becomes H.

Cf') Effects of the Invention Since the comparison is made with initial data, the loop cycle from the time the loop starts can be detected.

When multiple loops are operated simultaneously, synchronization and malfunction of each loop can be detected.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment according to the present invention, and FIG. 2 is a circuit diagram of an embodiment according to the present invention.
FIG. 3 is a circuit diagram of an embodiment according to the present invention in the case of four loops, FIG. 4 is a time chart of FIG. 3, and FIG. 5 is a circuit diagram of a prior art. a1~a4...FF, bl~b3...
Switch, c1~c3...EXORld...
...OR. To the agent and patent attorney, Kin Komata, Q.

Claims (1)

[Claims] 1. Malfunction monitoring of an M-sequence generation circuit, characterized in that the loop that generates the M-series includes a circuit that holds data to be initialized in the loop and compares it with the internal state of the loop. circuit. 2. A malfunction monitoring circuit for an M-sequence generation circuit, which detects normal operation or malfunction of each loop in a device having a plurality of the above loops.