JPH0290619A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0290619A
JPH0290619A JP24504888A JP24504888A JPH0290619A JP H0290619 A JPH0290619 A JP H0290619A JP 24504888 A JP24504888 A JP 24504888A JP 24504888 A JP24504888 A JP 24504888A JP H0290619 A JPH0290619 A JP H0290619A
Authority
JP
Japan
Prior art keywords
wiring
film
semiconductor device
oxide film
conductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24504888A
Other languages
Japanese (ja)
Inventor
Akira Tamakoshi
晃 玉越
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP24504888A priority Critical patent/JPH0290619A/en
Publication of JPH0290619A publication Critical patent/JPH0290619A/en
Pending legal-status Critical Current

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Landscapes

  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To obtain the semiconductor device with a wiring which is resistant to migration by a method wherein the surface of a wiring layer mainly composed of aluminum is coated and closely fixed using an oxide film. CONSTITUTION:A conductor layer 3 is formed on a semiconductor substrate 1 through the intermediary of a silicon oxide film 2, and an Al wiring 5 is formed on the conductor layer 3 through the intermediary of an interlayer insulating film 4. Especially, an Al2O3 film 7 is formed on the surface of said Al wiring 5.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に配線の構造に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device, and particularly to a wiring structure.

〔従来の技術〕[Conventional technology]

従来の半導体装置は、例えば第2図に示すように、半導
体基板1上の眉間絶縁膜4上に形成されたAf配線5の
上には、直接絶縁保護膜としてのPSG膜6が形成され
ていた。尚、第2図において2はシリコン酸化膜、3は
多結晶シリコンからなり、ゲート電極を構成する導体層
である。
In the conventional semiconductor device, for example, as shown in FIG. 2, a PSG film 6 as an insulating protective film is directly formed on the Af wiring 5 formed on the glabellar insulating film 4 on the semiconductor substrate 1. Ta. In FIG. 2, 2 is a silicon oxide film, and 3 is a conductor layer made of polycrystalline silicon and constitutes a gate electrode.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

配線中を電流が流れる場合、電子の流れによって金属中
の原子が電子の力を受け、一方向の電流の流れにより原
子が移動してゆく、いわゆるマイグレーションが生じ、
配線の一部で配線幅が減少するという現象が起きる。そ
して、一箇所で配線幅が減少すると、この部分は他の配
線部より抵抗値が増大し電流の流れを大きく受けるよう
になり、金属原子がより大きな力を受けて移動速度が速
まり、最終的にはこの部分において配線の切断というこ
とがおきる。そのため半導体集積回路の微細化が進み、
配線幅の縮小化が進むとマイグレーションの問題がより
大きなものとなる。
When current flows through wiring, the atoms in the metal are subjected to electron force due to the flow of electrons, causing so-called migration, where the atoms move due to the flow of current in one direction.
A phenomenon occurs in which the wiring width is reduced in a part of the wiring. When the wiring width decreases in one place, this part has a higher resistance value than other wiring parts and receives a larger current flow, and the metal atoms receive a larger force and move faster, resulting in the final Generally speaking, the wiring may be cut at this part. As a result, the miniaturization of semiconductor integrated circuits has progressed,
As the wiring width becomes smaller, the problem of migration becomes more serious.

一般に導体中を流れる電子は、導体中心部よりも表面に
近い方がより多く流れる。そのため、金属原子の移動は
導体表面部より起こるものとなる。
Generally, more electrons flow in a conductor near the surface than in the center of the conductor. Therefore, the movement of metal atoms occurs from the surface of the conductor.

第2図に示した従来の半導体装置におけるAJ配線5と
CVD法により形成されたPSG膜6との接着性はそれ
程強くはないため、上記理由によりマイグレーションに
弱いという問題がある。
Since the adhesion between the AJ wiring 5 and the PSG film 6 formed by the CVD method in the conventional semiconductor device shown in FIG. 2 is not so strong, there is a problem that it is susceptible to migration for the above-mentioned reason.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置は、アルミニウムを主成分とする配
線層を有する半導体装置であって、前記配線層の表面は
酸化膜により覆われているものである。
The semiconductor device of the present invention is a semiconductor device having a wiring layer mainly composed of aluminum, and the surface of the wiring layer is covered with an oxide film.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例の断面図である。FIG. 1 is a sectional view of an embodiment of the present invention.

第1図において、半導体基板1上にはシリコン酸化膜2
を介して導体層3が形成されている。この導体層3は、
例えば多結晶シリコンからなるゲート電極である。そし
て、この導体層3上には眉間絶縁膜4を介してA1配線
5が形成されている。そして特に、このAJ配線5の表
面にはAJ、O,膜7が設けられている。尚、6は絶縁
保護膜としてのPSG膜である。
In FIG. 1, a silicon oxide film 2 is formed on a semiconductor substrate 1.
A conductor layer 3 is formed through the conductor layer 3. This conductor layer 3 is
For example, it is a gate electrode made of polycrystalline silicon. A1 wiring 5 is formed on this conductor layer 3 with a glabella insulating film 4 interposed therebetween. In particular, an AJ, O, film 7 is provided on the surface of this AJ wiring 5. Note that 6 is a PSG film as an insulating protective film.

A々20’3膜7は、/Ml配線5を形成したのち、酸
素雰囲気中で500〜600℃で熱処理することにより
、200〜300Aの厚さに形成できる。
The A20'3 film 7 can be formed to a thickness of 200 to 300 Å by performing heat treatment at 500 to 600° C. in an oxygen atmosphere after forming the /Ml wiring 5.

このように構成された本実施例によればAJI配線5は
Aff120.膜により保護され応力が与えられるため
、マイグレーションの発生は抑制されたものとなる。更
に水分を遮断できるためA1配線の腐食を防ぐことがで
きる。
According to this embodiment configured in this way, the AJI wiring 5 is Aff120. Since the film protects and applies stress, the occurrence of migration is suppressed. Furthermore, since moisture can be blocked, corrosion of the A1 wiring can be prevented.

尚、上記実施例においてはA1配線は1層の場合につい
て説明したが、2層以上であってもよいことは勿論であ
る。
In the above embodiment, the case where the A1 wiring is one layer has been described, but it goes without saying that it may be two or more layers.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、アルミニウムを主成分と
する配線層の表面を酸化膜で覆って密着させ、配線層表
面に応力を与えているため、マイグレーションに強い配
線を有する半導体装置が得られる。
As explained above, in the present invention, the surface of the wiring layer mainly composed of aluminum is covered with an oxide film and brought into close contact with each other, and stress is applied to the surface of the wiring layer, so that a semiconductor device having wiring that is resistant to migration can be obtained. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の断面図、第2図は従来の半
導体装置の一例の断面図である。 1・・・半導体基板、2・・・シリコン酸化膜、3・・
・導体層、4・・・層間絶縁膜、5・・・A、R配線、
6・・・PSG膜、7・・・AJ、03膜。
FIG. 1 is a sectional view of an embodiment of the present invention, and FIG. 2 is a sectional view of an example of a conventional semiconductor device. 1... Semiconductor substrate, 2... Silicon oxide film, 3...
・Conductor layer, 4... Interlayer insulating film, 5... A, R wiring,
6...PSG film, 7...AJ, 03 film.

Claims (1)

【特許請求の範囲】[Claims]  アルミニウムを主成分とする配線層を有する半導体装
置において、前記配線層の表面は酸化膜により覆われて
いることを特徴とする半導体装置。
1. A semiconductor device having a wiring layer containing aluminum as a main component, wherein a surface of the wiring layer is covered with an oxide film.
JP24504888A 1988-09-28 1988-09-28 Semiconductor device Pending JPH0290619A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24504888A JPH0290619A (en) 1988-09-28 1988-09-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24504888A JPH0290619A (en) 1988-09-28 1988-09-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0290619A true JPH0290619A (en) 1990-03-30

Family

ID=17127806

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24504888A Pending JPH0290619A (en) 1988-09-28 1988-09-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0290619A (en)

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