JPH0290371A - Pattern inspecting method - Google Patents

Abstract

PURPOSE:To reduce the deciding reference at a pattern boundary part by producing plural sampling pictures and deciding these pictures. CONSTITUTION:The pictures received from an image pickup device 1 are binarized by a binarization circuit 2 and inputted to a RAM 51 or 52 via a switch circuit 4. The data on the RAM 51 and 52 are inputted to a shift register group 7 via a switch circuit 6. In this case, both circuits 4 and 6 input the horizontal synchronizing signal Yc8 to an n-ary (n = 2) disk counter 9 and work with the obtained switch signal 10. While the write and read addresses 14 and 12 of both RAMs are produced from the scan clock Xc11. The sampled binary signals are successively inputted to the register group 7 and the output of the group 7 is inputted to a serial-in/parallel-out shift register 23 consisting of (M X N) picture elements. Then plural pictures are decided.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to pattern appearance inspection of printed boards and the like.

[Conventional technology]

The conventional technology for pattern inspection is the Japanese Patent Publication No. 59-2456.
There is No. 1. This is a method that extracts features such as boundaries and minute parts from two binary images, and if the same features exist in the two binary images, it is considered a good product, and if it exists only in one, it is considered a defective product.

[Problem to be solved by the invention]

In multilayer printed boards, etc., some unevenness at the border of the turn is unavoidable due to the manufacturing process, resulting in breakage of the turn,
Different criteria are needed for determining defects inside and outside the pattern, such as short circuits, but the conventional technology described above uniformly processes pattern defects inside and outside the pattern boundary dock turn. There was no consideration given.

SUMMARY OF THE INVENTION An object of the present invention is to provide an entire pattern inspection method in which judgment criteria are changed at pattern boundaries, inside and outside of the putter.

[Means to solve the problem]

In order to achieve the above object, the present invention basically performs determination processing on the obtained image, which is sampled in the horizontal and vertical directions every n pixels (n, 22). However, if the image is simply sampled, as shown in FIG. 2, although it is possible to soften the unevenness of the boundary, there is a possibility that defects inside and outside the pattern will be erased. Therefore, in the present invention, as shown in the sixth factor, a plurality of sampling images t' are created and a determination process is performed on the plurality of sampling images.

[Effect]

By performing the determination process on multiple sampling images, even if a defect is not detected in one sampling image, the defect will not be detected in other sampling images (Figure 6(c)). , (d) ),
In addition, since sampling is performed, the irregularities at the boundaries of each sampled image are softened.

〔Example〕

An embodiment of the present invention will be explained with reference to FIG. In this embodiment, it is assumed that the method disclosed in Japanese Patent Publication No. 59-24361 is used for the determination process. In Japanese Patent Publication No. 59-24561, partial images of MxN pixels are sequentially detected from the inspection image and the reference image, and judgment processing is performed. Explain in detail. Further, in FIG. 1, the following description will be made assuming that sampling is performed every two pixels (n=2) in the horizontal and vertical directions. In FIG. 1, 1 is the #L image device, 2 is the binarization circuit, and 0. Binarization code 3 is the switching circuit 4.
The data is input to a RAM (random access memory) 5.1 or 5.2 via the RAM. The RAM 5 is connected via the switching circuit 6.
The signal is input to a shift register group 7 consisting of N shift registers each having a length n times (in this embodiment, twice) the length of a scanning line. The switching circuit 4.6 operates every time the scanning line changes by one, and determines whether R, AM 5.1 and 5.2 are used for writing or reading.
c) is input to the n-ary counter 9 (in the case of this embodiment, n=2), and the switching signal 10 obtained performs multiple operations.几AM5
The write address and read address of are scanned by the scanning clock 11 (
Xc) Generate. The subsequent address 12 is generated by inputting 11 into the cram school terminal 13. Write address 14 is an n-ary counter (n=2 in this embodiment)
15 is counted by the counter 16, and the switching circuit 19 is operated by the scanning clock 11 to switch the n (in this embodiment, two) preset address values 18 to 1.
By adding the output of 6 and the adder circuit 20, it is generated. For example, if the length of the scanning line is 11024, 1z18 is set to ``0'' and ``512''. In this way, the write address 14 will be o, 51 to 1.51 2, 51
It changes as 4...511.1025. Write address 14 obtained as above. The read address 12 is read through a switching circuit 2t22 that operates according to the switching signal 10.
It is supplied as the address of 几AM5.

By adopting such a configuration, shift register group 7
In this case, the sampled 2
Value codes are input one after another. Serial-in-parallel output shift register 2 with output of 7 as MxN pixels
By inputting to 3, 23 becomes n pixels horizontally and vertically (
In this example, n=2) and trap-sampled MXN
Partial images of pixels are input one after another. 25 is subjected to the determination process shown in Japanese Patent Publication No. 459-24361.

〔Effect of the invention〕

According to the present invention, the criteria for judgment at pattern boundaries can be relaxed, so it is suitable for pattern inspection of printed boards and the like.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is an explanatory diagram of problems in image sampling, Fig. 3 is an explanatory diagram of the image sampling principle of the present invention, and Fig. 4 is a shift register in the embodiment. FIG. 1... Imaging device, 2 - Binarization circuit, 5... RAM
17...Shift register group, 25...Serial in-parallel out shift register. Deputy AjP8! Katsuo Shi Ogawa-Law

Claims (1)

[Claims] 1. A means for binarizing the image signal obtained from the imaging device, a means for rearranging the binarized signals for each scanning line, and a means for temporarily storing the rearranged binary signals over a plurality of scanning lines are provided. , sequentially reading binary images from the storage means,
Detecting the sampled partial binary image and extracting defects by inputting the input to the shift register group having the length of the plurality of scanning lines, and inputting the input from the shift register group to the serial-in-parallel-out shift register. A pattern inspection method characterized by: