JPH0289355A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0289355A
JPH0289355A JP24135588A JP24135588A JPH0289355A JP H0289355 A JPH0289355 A JP H0289355A JP 24135588 A JP24135588 A JP 24135588A JP 24135588 A JP24135588 A JP 24135588A JP H0289355 A JPH0289355 A JP H0289355A
Authority
JP
Japan
Prior art keywords
lead terminal
groove
package
semiconductor device
view
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24135588A
Other languages
Japanese (ja)
Inventor
Yoshihiro Matsumoto
松本　良博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP24135588A priority Critical patent/JPH0289355A/en
Publication of JPH0289355A publication Critical patent/JPH0289355A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent a lead terminal from being deformed against an external force by providing a groove which is slightly wider than the lead terminal width at either the lower surface of a package or a side surface, or both of lower and side surfaces and by inserting a lead terminal in that groove. CONSTITUTION:A groove 3 which is slightly wider than a package 1, a lead terminal 2, and a lead terminal width is provided. The tip of the lead terminal 2 is inserted into the groove 3 on the lower surface of the package 1 and are held by the both side surfaces and bottom surface of the groove 3. It allows the tip of lead terminal to be held at the both side surfaces and the bottom surface of the groove, and prevents it from being deformed by any external force in left/right directions and lower direction.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、フラットパッケージ半導体装置、あるいはＳ
Ｏパッケージ半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to flat package semiconductor devices or S
The present invention relates to an O-package semiconductor device.

従来の技術 従来、フラットパッケージ半導体装置あるいはＳＯパッ
ケージ半導体装置において、リード端子は第７図に示す
様な形状であり、リード端子先端は機械的に何らの拘束
もさせておらず、外力に対してはフリーであった。Conventional technology Conventionally, in a flat package semiconductor device or an SO package semiconductor device, the lead terminal has a shape as shown in Fig. 7, and the tip of the lead terminal is not mechanically restrained in any way, and is resistant to external force. was free.

発明が解決しようとする課題 従って、上記の従来のフラットパッケージ半導体装置、
あるいはＳＯパッケージ半導体装置においては、製造工
程間あるいは完成後においても何らかの外力に対してリ
ード端子が変形するという問題があった。本発明は上記
従来の問題点を解決するもので、外力に対してリード端
子が変形することを防止できる半導体装置を提供するこ
とを目的とするものである。Problems to be Solved by the Invention Therefore, the above conventional flat package semiconductor device,
Another problem with SO packaged semiconductor devices is that the lead terminals are deformed by some external force during the manufacturing process or even after completion. The present invention solves the above-mentioned conventional problems, and aims to provide a semiconductor device that can prevent lead terminals from deforming due to external forces.

課題を解決するための手段 この目的を達成するために、本発明の半導体装置は、パ
ッケージ下面、側面あるいは下面と側面との両方にリー
ド端子幅よりわずかに大きい幅の溝を有し、その溝にリ
ード端子をはめ込んだものから構成されている。Means for Solving the Problems To achieve this object, the semiconductor device of the present invention has a groove having a width slightly larger than the lead terminal width on the bottom surface, side surface, or both the bottom surface and the side surface of the package. It consists of a lead terminal fitted into the inside.

作用 この構成によって、リード端子先端は、溝の両側面及び
底面にて拘束されており、左右方向及び下方向からの何
らかの外力に対しても変形することが防止される。Function: With this configuration, the lead terminal tip is restrained by both side surfaces and the bottom of the groove, and is prevented from being deformed by any external force from the left or right direction or from below.

実施例 以下、本発明の一実施例について、図面を参照しながら
説明する。第１図は本発明の一実施例半導体装置の断面
図を示し、また、第２図はその一部破断側面図を示すも
のである。第１図、第２図において、１はパッケージ、
２はリード端子、３はリード端子幅よりわずかに大きい
幅の溝を表わす。第１．２図に表わす様に、リード端子
２の先端は、パッケージ１の下面の溝３にはまり込んで
おり、溝３の両側面及び底面で拘束されているものであ
る。EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 shows a sectional view of a semiconductor device according to an embodiment of the present invention, and FIG. 2 shows a partially cutaway side view thereof. In Figures 1 and 2, 1 is a package;
2 represents a lead terminal, and 3 represents a groove having a width slightly larger than the width of the lead terminal. As shown in FIG. 1.2, the tips of the lead terminals 2 fit into the grooves 3 on the lower surface of the package 1, and are restrained by both sides and the bottom of the grooves 3.

第３図、第４図は本発明の他の実施例半導体装置の断面
図、一部破断側面図を示すものである。FIGS. 3 and 4 show a sectional view and a partially cutaway side view of a semiconductor device according to another embodiment of the present invention.

第３図、第４図において、１はパッケージ、２はリード
端子、３はスリット状の溝を表わす。各図に表わす様に
、リード端子２はパッケージ１の側面の溝３にはまり込
んでおり、溝の両側面及び底面にて拘束されているもの
である。In FIGS. 3 and 4, 1 represents a package, 2 a lead terminal, and 3 a slit-like groove. As shown in each figure, the lead terminal 2 fits into a groove 3 on the side surface of the package 1, and is restrained by both side surfaces and the bottom surface of the groove.

さらに、第５図、第６図は本発明の別の実施例における
半導体装置の断面図、一部破断側面図を示すものである
。第５図、第６図において、１はパッケージ、２はリー
ド端子、３はリード端子幅よりわずかに大きい幅の溝を
表わす。第５図、第６図に表わす様に、リード端子２の
先端は、パッケージ１の側面及び下面の溝３にはまり込
んでおり、溝の両側面及び底面にて拘束されている。Furthermore, FIGS. 5 and 6 show a sectional view and a partially cutaway side view of a semiconductor device in another embodiment of the present invention. In FIGS. 5 and 6, 1 represents a package, 2 represents a lead terminal, and 3 represents a groove having a width slightly larger than the width of the lead terminal. As shown in FIGS. 5 and 6, the tips of the lead terminals 2 fit into the grooves 3 on the side and bottom surfaces of the package 1, and are restrained by both side and bottom surfaces of the grooves.

発明の効果 以上のように本発明によれば、パッケージ下面または側
面あるいは下面、側面の両方に溝を有し、この溝内に折
り曲げたリード端子をはめ込むことにより、半導体製造
工程間、あるいは完成後においても、何らかの外力に対
してリード端子の変形が防止でき、歩留り向上、あるい
は製品の信頼性向上に大きく役立つものとなる。Effects of the Invention As described above, according to the present invention, the package has a groove on the bottom surface or side surface or both the bottom surface and the side surface, and by fitting the bent lead terminal into the groove, the package can be used during the semiconductor manufacturing process or after completion. Even in this case, deformation of the lead terminals due to some external force can be prevented, which greatly contributes to improving yield and product reliability.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例半導体装置の断面図、第２図
はその一部破断側面図、第３図および第４図は本発明の
他の実施例装置の断面図、および一部破断側面図、第５
図および第６図は本発明の別の実施例装置の断面図およ
び一部破断側面図、第７図は従来例装置の断面図である
。 １・・・・・・パッケージ、２・・・・・・リード端子
、３・・・・・・溝 代理人の氏名　弁理士　粟野重孝　ほか１名第１１２１ ／゛−パツプー Ｖ−リード端子 ３−　溝− 第２図 ／ 第 図 第 図 第 第 図 図 ？FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a partially cutaway side view thereof, and FIGS. 3 and 4 are sectional views and partially Broken side view, 5th
6 are a sectional view and a partially cutaway side view of another embodiment of the device of the present invention, and FIG. 7 is a sectional view of a conventional device. 1... Package, 2... Lead terminal, 3... Groove Name of agent Patent attorney Shigetaka Awano and 1 other person No. 1121 /゛-Patpuu V-Lead terminal 3- Groove - Fig. 2/ Fig. Fig. Fig. Fig. ?

Claims (1)

【特許請求の範囲】[Claims] パッケージ下面または側面もしくは下面、側面の両方に
リード端子幅よりわずかに大きい幅の溝を有し、その溝
にリード端子の先端をはめ込むことにより、リード端子
の変形を拘束していることを特徴とする半導体装置。It is characterized by having a groove with a width slightly larger than the lead terminal width on both the bottom surface or side surface of the package or the bottom surface and the side surfaces, and by fitting the tip of the lead terminal into the groove, deformation of the lead terminal is restrained. semiconductor devices.
JP24135588A 1988-09-27 1988-09-27 Semiconductor device Pending JPH0289355A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24135588A JPH0289355A (en) 1988-09-27 1988-09-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24135588A JPH0289355A (en) 1988-09-27 1988-09-27 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0289355A true JPH0289355A (en) 1990-03-29

Family

ID=17073062

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24135588A Pending JPH0289355A (en) 1988-09-27 1988-09-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0289355A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6433418B1 (en) 1998-07-24 2002-08-13 Fujitsu Limited Apparatus for a vertically accumulable semiconductor device with external leads secured by a positioning mechanism

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6433418B1 (en) 1998-07-24 2002-08-13 Fujitsu Limited Apparatus for a vertically accumulable semiconductor device with external leads secured by a positioning mechanism

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