JPH0289305A - Lithography device - Google Patents

Abstract

PURPOSE:To minimize the drop in alignment accuracy while improving the yield by forming a resist pattern on a substrate while finding the optimal exposure time and the correction value of an alignment position and controlling a treatment condition of an exposure treatment device every shot region. CONSTITUTION:A main control device 25 performs every two times of exposure (tested exposure and untested exposure) on a wafer W for finding the optimal exposure condition (the optimal exposure time T and alignment correction values DELTAX, DELTAY) every shot region of the wafer W by test exposure and for controlling exposure parameter of a stepper SR according to the optimal exposure condition by untested exposure in order to form a pattern of a reticle R on the wafer. By repeating aforesaid operation every wafer W, the uneven line width of a circuit pattern and a drop in alignment accuracy or the like can be minimized and as a result the yield also can be improved.

Description

Detailed Description of the Invention [Industrial Field of Application] The present invention relates to lithography equipment for forming a predetermined pattern on a thin substrate such as a semiconductor wafer or a liquid crystal substrate, and in particular, in the manufacturing process of semiconductor integrated circuits. The present invention relates to a lithography apparatus that exposes a circuit pattern of a semiconductor element formed on a semiconductor wafer to form a resist pattern on a semiconductor wafer.

L Prior Art] In the manufacturing process of semiconductor integrated circuits, a lithography apparatus that exposes a circuit pattern formed on a mask or reticle (hereinafter referred to as a reticle) to form a resist pattern on a wafer uses a resist coating device (coater). ), the resist coating section (coater section), and the developing section (part of the daybelo soba), centered on the developing device (daybelosoba).
Resist processing equipment (coater/
A step-and-type process that sequentially exposes the circuit pattern of the reticle onto the wafer under predetermined exposure conditions.
It consists of a repeat-type reduction projection exposure device (stepper). In this type of lithography apparatus, the wafer is transported through a substrate processing process in the order of a coater section, a stepper, and a portion of a developer flange, and is subjected to various processes, and the circuit pattern of the reticle R is formed on the wafer W as a resist pattern. At this time, processing conditions such as resist coating and development processes and management of the wafer during processing are configured to be performed by a control means including a processor such as a microcomputer. In order to obtain a circuit pattern, it is necessary to determine in advance the optimum conditions for forming a resist pattern using a wafer processing unit such as a coater or a developer or a stepper, and to manually input it to the control means. Therefore, conventionally, when starting up a lithography apparatus, a test reticle is used to form a resist pattern on a wafer under predetermined formation conditions, and the formation state, that is, the line width of the resist pattern, etc. is measured using an inspection device. Then, based on the measured values and the design values of the test pattern, optimal forming conditions for the wafer processing unit and stepper are calculated, and the optimal forming conditions are fed back to the control means. As a result, the control means controls the processing conditions of the lithography apparatus according to the optimum formation conditions, and forms a desired semiconductor element circuit pattern on the wafer that has been sequentially transported through the substrate processing steps and subjected to various treatments.

[Problem to be solved by the invention]

However, in the above-mentioned lithography apparatus, processing conditions such as a stepper are controlled based on the optimal forming conditions calculated at the time of starting the apparatus, and all wafers sequentially transferred through the substrate processing process are uniformly processed under the same processing conditions. There is. For this reason, film thickness unevenness occurs in the base material such as BPSG between the wafer and the resist layer on which the pattern is formed by etching using the resist pattern as a mask, especially the base material that has low absorption of light at the exposure wavelength. As a result, the reflectance of exposure light on the wafer surface changes. For this reason, if a reticle pattern is exposed onto a wafer in a state where the underlying film thickness is uneven, there is a problem in that line width unevenness will occur in the resist pattern formed on the wafer. In addition, when performing alignment between the projected image of the reticle pattern and the circuit pattern already formed on the wafer (hereinafter referred to as a chip), it is especially important to check the alignment marks formed on the chip and the If film thickness unevenness occurs in the nearby base, the reflectance of the alignment light at the alignment mark will similarly change, and the waveform of the photoelectric signal of the light reflected from the alignment mark will become asymmetrical. As a result, there was a problem that the position of the alignment mark could not be detected accurately, resulting in a decrease in alignment accuracy. Furthermore, there is a problem in that the yield is lowered due to these uneven line widths, lowered alignment accuracy, and the like.

The present invention has been made in consideration of the above points, and is a high-precision lithography method that can minimize line width unevenness and deterioration in alignment precision due to underlying film thickness unevenness, and improve yield. The purpose is to obtain equipment.

[Means to solve problems]

In order to solve this problem, the present invention provides a coater/develo burr having a coater part C centered on the coater and a deibero flange part centered on the develo sobber.
It consists of a CD and a stepper SR, and the wafer W is transferred to the coater section C.
In a lithography apparatus that forms a resist pattern on a wafer W by transporting a stepper SR and a developer part in this order, the wafer W is sequentially transferred to a substrate processing step consisting of a coater part C, a stepper SR and a developer part. The main transport bag 'IIMt [
a sub-transport device St (second transport device) that appropriately transports the wafer W transported through the substrate processing step by the main transport device Mt from a predetermined first position to a second position in the substrate processing step; By using at least one of the main transport device Mt and the sub-transport device St, the formation state of the resist pattern in all shot areas on the wafer W transported from the processing end position P7 of the substrate processing step, that is, the exposure Mark length Δ of resist image R1 of condition measurement mark Ml
t, y, positional deviation measurement mark Ms (Msx, May)
The laser step alignment system [pattern detection means] detects the position of the resist image RsxSRsy in the X1Y direction, etc., and the optimum formation conditions for each shot area, that is, the optimum exposure conditions for the stepper SH, based on the formation state of the resist pattern. A main controller 25 (control means) that calculates the optimum exposure time T and alignment correction values (ΔX, ΔY) and controls the processing conditions of the stepper SH for each shot area according to the optimum exposure conditions is provided. The wafer W whose formation state has been detected is transported again to the substrate processing step via the resist stripping device 5, and a resist pattern is formed in each ship DI area under optimal exposure conditions.

[For production]

According to the present invention, by detecting the formation state of resist patterns in all shot areas on the substrate for each substrate or for each rod containing a plurality of substrates, the exposure processing apparatus can perform optimal formation ( (exposure) conditions, that is, the optimum exposure time and alignment correction value. Then, the substrate whose formation state has been detected is transported again to the substrate processing process,
The resist pattern is formed while controlling the exposure parameters of the exposure processing apparatus for each shot area according to the optimum exposure conditions. Therefore, it is possible to minimize line width unevenness, deterioration in alignment accuracy, etc., which occur due to changes in the type of base layer, film thickness, etc. of the resist layer.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a plan layout diagram showing a schematic configuration of a lithography apparatus comprising a stepper SR and a coater developer CD according to a first embodiment of the present invention, and FIG. FIG.

In FIG. 1, the lithography apparatus consists of a caulk section C centered on a coater that performs hexamethyldisilazane (HMDS) treatment and coating of a positive resist layer as a pre-resist coating process and a resist coating process, and a wafer coating area as a development process. Coater/Developer CD, stepper S, which has a Deiberopobber part as the center, which etches the resist image of the circuit pattern printed on the W.
The main transfer device jMt sequentially transfers the wafer W to a substrate processing step consisting of the coater section C1, stepper SR, and developer stepper.

Now, the main transport device Mt is the loader (unloading) cassette 1 (
The wafer W stored in the buffer cassette ffP1) is transported through the coater section C, and the wafer W, which has been subjected to various treatments such as resist coating, is transferred to the buffer cassette 2 (which adjusts the cycle time).
-Hour is stored in position tP3).

Next, the wafer W in the buffer cassette 2 is transferred to the stepper SR.
The wafer W is transported to the wafer stage 7 (position P4), where the wafer W is exposed with a predetermined reticle pattern. Furthermore, after carrying out the exposed wafer W from the wafer stage 7 to position P5 of the substrate processing step, it is transferred to the unloader (carrying in) via the buffer cassette 3 (position P6), developer part, and processing end position P7. ) Cassette 4 (position P8). Here, the main conveyance device Mt uses both a belt conveyance method and an air conveyance method, and only the conveyance path thereof is shown in FIG. Big up arm PM capable of oscillating motion and 360 degree rotation, and linear
Consists of motor and guide RG! ll11m feeding device St
is provided at the center of the coater/developer CD.

The pick-up arm PM vacuum-chucks the back surface of the wafer W at a predetermined first position 1 in the substrate processing process (e.g., processing end position 1fiP?), and moves it to a desired second position (e.g., position P5?).
) to release the vacuum suction and transfer the wafer W to the main transfer device Mt.
It is configured so that it can move freely on G. Furthermore, a resist stripping device ra5 (position P9) for stripping the resist layer on the wafer W is provided in the lithography apparatus, and the wafer W at an arbitrary position in the substrate processing process is carried into the resist stripping device 5 by the sub-transfer device St. It is configured so that it can be done.

Next, the schematic structure of the stepper SR shown in FIG. 1 will be explained using FIG. 2. Since it is disclosed in Japanese Patent No. 60-130742, etc., it will be briefly explained here. In FIG. 2, an exposure illumination light source (not shown) generates illumination light of a wavelength (n light wavelength) that sensitizes the resist layer, such as g-line and i-line, and this illumination light is applied to the pattern area Pa of the reticle R. A one-sided (or both-sided) telecentric projection lens 6 that illuminates with uniform illuminance projects an image of the circuit pattern formed in the pattern area Pa onto the wafer W coated with a resist layer. In this embodiment, the optical system is a non-telecenter link on the reticle R side and a telecenter link on the wafer W side. Wafer W
is placed on a wafer stage 7 that moves two-dimensionally in the X and Y directions via a wafer holder (not shown).

The wafer stage 7 is moved two-dimensionally in a plane (imaging plane) substantially perpendicular to the optical axis AX of the projection lens 6 by the drive unit 8,
The two-dimensional position of the wafer stage 7 in the coordinate system XY is determined by a light wave interferometer (hereinafter referred to as a laser interferometer)
9, it is configured to be constantly detected with a resolution of, for example, 0°02 μm.

In addition, as an alignment system that detects the positions in the X and Y directions of a wafer mark for alignment that is printed on a chip on a wafer W, especially a diffraction grating mark that consists of a plurality of grating elements, a 2m TTL (through・The lens) method laser step alignment (L
SA) system is provided. In addition, only the LSA system that detects the position of the alignment mark in the Y direction is shown in FIG. A laser light source lO having a light source generates laser light with a linear polarization different from the exposure wavelength, and this laser light
The beam is expanded to a predetermined beam diameter by cylindrical lens 1.
2, the cross section is shaped into an elongated elliptical beam. The laser beam shaped in this way is reflected by the mirror 13, and then passes through the lens 14, the polarizing beam block 15, the quarter-wave plate 16 as a phase rotation member, and the objective lens 1.
After passing through 7, the light is reflected upward from the lower surface of the reticle R by the mirror 18. After the laser beam from the mirror 18 is once converged into a slit shape, it reaches the entrance pupil 6a of the projection lens 6 via the mirror 19 below the reticle R, which has a reflection plane parallel to the reticle R, and is directed onto the wafer W in the form of a long and narrow strip. A spot light SPy is formed. The spot light SPy extends in the X direction within the exposure field of the projection lens 6, is formed toward the optical axis AX of the projection lens 6, and is formed at a predetermined distance away from the optical axis AX on the X axis. be done. Then, when the wafer stage 7 is slightly moved in the X direction so that the spot light SPy scans the alignment mark (diffraction grating mark) in the X direction, scattered light and Diffracted light (first-order light or higher) is generated, and this optical information is transmitted to the projection lens 6,
The projection lens 6
Arranged approximately conjugate to the entrance pupil 6a of! The light then reaches a spatial filter 20 having an aperture that matches the diffracted light or scattered light distribution. Only the diffracted light or scattered light is extracted by the spatial filter 20 and sent to the light receiving element 22 via the condenser lens 21.
The light is focused on the light receiving surface. The light receiving element 22 serving as a photoelectric detector outputs a photoelectric signal corresponding to the intensity of the diffracted light or scattered light, and this photoelectric signal is input to an alignment signal processing circuit (hereinafter referred to as LSAC) 23.

The LSAC 23 also inputs position information from the laser interferometer 9, samples photoelectric signals in synchronization with up/down pulse signals generated every unit movement amount (0°02 μm) of the wafer stage 7, and performs predetermined calculation processing. This detects the scanning position of the mark in the X direction. In addition, in FIG. 1, in order to simplify the explanation, the LS that detects the position in the X direction is
Although only the A system is shown, there is actually another set of LSA systems with a similar configuration that detects the position in the X direction, and the first
In the figure, only the mirror 24 corresponding to the mirror 19 is shown. In addition, the main controller 25 uses the LSA system described above to determine the resist pattern formation conditions, that is, calculates the optimum exposure conditions such as exposure time, and also operates the two sets of LSA systems and the main transport device described above. It centrally controls the operation of the entire lithography apparatus including Mt, sub-transfer device St, and the like.

Next, the operation of this embodiment will be explained with reference to the schematic flowchart shown in FIG.

In step 100, the main controller 25 uses the main transport device M to unload the wafer W stored in the loader cassette 1 and transport it into the coater section C via the processing start position P2. In this coater section C, the wafer W is HM
Various treatments such as DS treatment and resist coating are performed. The wafer W having the resist layer formed on its surface in this manner is placed on the wafer stage 7 via the buffer cassette 2, and the main controller 25 executes the next step 101.

In step 101, the main controller 25 uses a reticle R having a predetermined shape of a mark for measuring exposure conditions and a mark for measuring positional deviation, and performs a first process on the entire surface of the wafer W under preset predetermined exposure conditions. Exposure (test exposure) is performed. Here, the alignment of a cross-shaped mark, a rectangular mark, a diffraction grating mark, etc. formed along with the pattern area Pa of the reticle R is performed as a mark for measuring exposure conditions and a mark for measuring positional deviation. Although the marks may also be used as marks, in this embodiment, as shown in FIG.
Measurement marks (hereinafter simply referred to as ME and Ms) are provided. Measurement marks Me, M are shown in Fig. 5 (a) and (b).
As shown in FIG. 5(a), which shows a schematic configuration of an example of s, the measurement mark M1 has a pattern in which the line width changes continuously or stepwise, for example, two wedge-shaped patterns on the left and right (
Three symmetrical patterns (with respect to the X direction) are formed in parallel at regular intervals in the X direction. Further, as shown in FIG. 5(b), a plurality of measurement marks M3 (in particular,
In this example, 5) lattice elements (minute convex portions or concave portions)
is composed of diffraction grating marks M x and M a y arranged to extend in the Y and X directions, respectively, with a certain pinch. Note that the positions where the measurement marks M1 and Ms shown in FIG. 4 are formed are not limited to the area corresponding to the scribe line, but may be formed so as to fall within the exposure field of the projection lens 6.

As described above, the sea urchin/%W on which the reticle R having the measurement marks Me and Ms has been exposed is returned to the main transport device M.
t from stepper SR to position P5 of the substrate processing process.
Then, the main controller 25 executes the next step 102.

In step 102, the wafer W on which the reticle pattern has been exposed is subjected to various processes such as development by a developer. Then, the main controller 25 carries out the wafer W on which the resist pattern has been formed from the developer substrate part to the processing end position P7, and executes the next step 103.

In step 103, the main controller 25 controls whether the resist pattern formed on the wafer W at the processing end position P7 is
It is determined whether it was formed during the second exposure (test exposure) or the second exposure (main exposure). The wafer W on which a resist pattern has been formed by test exposure is transported from the processing end position P7 to the position P5 by the sub-transport device St, and then placed on the wafer stage 7 by the main transport device Mt. Further, the wafer W on which the resist pattern has been formed by the main exposure is directly stored in the unloader cassette 4 from the processing end position P7 by the main transport device Mt. Here, since the test exposure of the reticle R shown in FIG. 4 was performed, the main controller 25 places the wafer W on the wafer stage 7 as described above, and executes the next step 104.

In step 104, the main control unit 25 controls two sets of L
Using the SA system, the formation state of the resist pattern is determined for each shot area on the wafer W, that is, the mark length in the Y direction of the resist image R1 of the measurement mark M1, and the resist images of the diffraction grating marks Msx and Msy that constitute the measurement mark Ms. Rs.
% Detect the position of RSy in the X and Y directions. Therefore,
Next, this measurement operation is shown in Figs. 6(a), (b), and 7(a).
) and (b). Note that FIG. 6(a) shows the state in which the spot light SPy scans the resist image R1, and FIG. 6(b) shows the waveform of the photoelectric signal Sl obtained at that time.
FIG. 7(a) shows the state in which the spot light SPy scans the resist image Rsy, and FIG. 6(b) shows the waveform of the photoelectric signal S2 obtained at that time.

First, the main controller 25 uses the drive unit 8 to slightly move the wafer stage 7 in the Y direction so that the spot light spy relatively scans the resist image R1 in the Y direction (FIG. 6(a)). At this time, the spot light SPy is applied to the resist image R1.
When scanning starts, scattered light (or diffracted light) is generated from the edge E1, and the light receiving element 22 receives this scattered light (or diffracted light).
Diffracted light) is photoelectrically detected and a photoelectric signal corresponding to the intensity of the scattered light begins to be output. Furthermore, as the scanning progresses, the scattered light also increases and decreases depending on the line width, height, etc. of the resist image Rf, and when the spot light SPy passes the edge E2, a photoelectric signal St from the light receiving element 22 (Fig. (b)) becomes approximately zero. The photoelectric signal Sl output from this light receiving element 22 is L
It is input to the SAC23, and the LSAC23 receives this photoelectric signal S.
Based on l and the position signal of the laser interferometer 9, the edge E
1, detect the Y-direction coordinate values Yl, Y2 of E2. Next, the main controller 25 determines the resist image R from the coordinate values Yl and Y2.
The mark length of 1 is calculated and the value is stored as ΔLy.

Next, the main control device B 25 uses two sets of LSA systems to measure the resist image R3X in the same manner as measuring the mark length ΔLy.
, R3) detect the position of l in the X and Y directions. First, the seventh
As shown in Figure (a), the spot light SPy illuminates the resist image R.
The wafer stage 7 is moved in the Y direction so as to scan sy in the Y direction.
Make a slight movement in the direction.

Then, the diffracted light generated from the resist image Rsy is charged and detected by the light receiving element 22, and the light receiving element 22 converts the photoelectric signal S2 according to the intensity of the diffracted light as shown in FIG. 7(b) into the LSAC.
Output to 23. The LSAC 23 detects the coordinates (aY3) of the resist image Rsy based on the photoelectric signal S2 and the position signal of the laser interferometer 9, and outputs this position information (coordinate value Y3) to the main side fl! device 25. A measurement mark (diffraction grating mark) having the same shape as that shown in FIG. 5 is formed along with the circuit pattern on the base such as BPSG under the resist pattern by the etching process in the previous process.Therefore, the main controller 25 Similar to the above operation, the LSA system is used to detect the position of the diffraction grating mark formed on the base in the Y direction, and the detected value is stored as a coordinate value Y4.

Here, since the projected image of the reticle R is normally aligned with the chips on the wafer W and then overlaid and exposed,
The coordinate values Y3 and Y4 detected as described above are set in a predetermined positional relationship, for example, set to be separated from each other by an interval of about 20 μm in the Y direction, or the coordinate values Y3 and Y4 are set to be separated from each other by an interval of about 20 μm in the Y direction, or the coordinate values Y3 and Y4 are set to be separated from each other by an interval of about 20 μm in the Y direction. They should be set up to lose each other. However, due to changes in the reflectance of the alignment light due to unevenness in the underlying film thickness, it is not possible to accurately detect the position of the alignment mark, and accurate alignment is not always performed. calculates the amount of positional deviation from the designed position in the Y direction from the coordinate values Y3 and Y4, and stores this value as the alignment error ΔY. Similarly, main controller 2
5 detects the position of the resist image Rsx and the diffraction grating mark formed on the base in the X direction, calculates the amount of positional deviation in the X direction from this detected value, and stores this value as alignment error ΔX. The main controller 25 then determines the mark length ΔL7 and the alignment errors ΔX and ΔY in the X and Y directions.
This detection is repeated for all shot areas on the wafer W, and the mark length ΔLy and alignment error ΔX1ΔY for each shot area are stored.

Next, in step 105, the main controller 25 determines the mark length ΔL for each shot area detected in step 104.
It is determined whether F and alignment error Δx1ΔY are each within predetermined tolerance ranges. If the judgment result is good, the wafer W is carried out from the stepper SR by the main transfer device Mt and the sub-transfer device St, and is stored in the unloader cassette 4. In this embodiment,
It is assumed that both the mark length ΔL7 and the 7 alignment errors ΔX and ΔY exceed the allowable range, and the next step 106
Execute.

In step 106, the main controller 25 first determines the optimum timing for each shot area on the wafer W based on the mark length ΔLy detected in step 104 and the predetermined relationship between the mark length ΔLy and the exposure time. Calculate the exposure time T and store this value.

Note that the optimum exposure time T is usually calculated by measuring the line width of the circuit pattern or alignment mark on the wafer W and from this measured value and the designed line width. However, in this method, the line width of the circuit pattern is - When the line width is on the order of microns, it becomes difficult to detect the line width and the measurement error increases, making it impossible to accurately calculate the optimum exposure time T. However, in this example, a measurement mark Ml that is a combination of two wedge-shaped patterns with extremely sharp apex angles is used, and the exposure time Detects the mark length ΔLy of the measurement mark Ml, which is several tens of times more sensitive to changes in , and calculates the optimum exposure time T from this mark length ΔLy. It is possible to calculate the exposure time T.

Next, the main controller 25 determines the position of the projected image of the reticle R and the chip due to the unevenness of the underlying film thickness! In order to correct the deviation, the alignment errors ΔX and ΔY detected in step 104 are
LSAC23 as alignment correction value (offcent)
Set to . This completes the setting of the optimal formation conditions for the resist pattern, that is, the optimal exposure conditions (optimal exposure time T, alignment correction values ΔX, ΔY) for the stepper SR, and the main controller 25 executes the next step 107.

In step 107, the main controller 25 uses the main transport device ML and the sub-transport device St to transport the wafer W from the stepper SR to the resist stripping device 5 via the position P5 of the substrate processing process. In the resist stripping device 5, the wafer W having a resist pattern formed on its entire surface is cleaned with an organic solvent, and the resist layer is stripped off. The wafer W from which the resist layer has been peeled off in this way is transported to the processing start position P2 of the substrate processing step by the sub transport bag y1st.
Next, the main controller 25 again executes steps 100 to 103, and in step 106 sets the settings for each shot area on the wafer W that has been subjected to resist coating, etc. in the coater section C under the same processing conditions as during test exposure. The second exposure of reticle R shown in FIG.
Main exposure). In other words, the operation of a shutter (not shown) that closes and opens the optical path of the exposure light is controlled according to the optimum exposure time T for each shot area, and the overlapping is performed by shifting the exposure light from the alignment position by alignment correction values ΔX and ΔY. While doing so, perform the main exposure. After the wafer W is subjected to a development process in the developer section, the wafer W having a resist pattern formed on its entire surface is stored in the unloader cassette 4.

As described above, the main controller 25 exposes the wafer W twice (test exposure and main exposure), and in the test exposure, the optimum exposure conditions (optimum exposure time T
and alignment correction values ΔX, ΔY), and in the main exposure, the operation of forming the pattern of the reticle R on the wafer W is repeated for each wafer W while controlling the exposure parameters of the stepper SH according to the optimum exposure conditions. By doing so, it is possible to minimize line width unevenness of the circuit pattern, deterioration in alignment accuracy, etc., and as a result, yield can also be improved. It should be noted that the wafer W to which the main exposure is performed is processed by the coater section C and the developer section under the same processing conditions as during the test exposure. There is no need to set the conditions again, and the time required to set the processing conditions can be shortened.

As mentioned above, in the above embodiment, test exposure and main exposure are performed for each wafer W, but for example, for wafers W stored in the same rod, only the first wafer W is described above. Similarly, test exposure may be performed to calculate the optimum exposure conditions, and all subsequent wafers W in the rod may be uniformly exposed under these optimum exposure conditions. While the subsequent wafers W are being processed, the first wafer W is subjected to processes such as resist removal, and at the end of the rond, the first wafer AW is transported to the substrate processing process and the main wafer W is processed. It is good to be able to perform exposure.

In addition, in this embodiment, the formation state of the resist pattern was detected using an LSA system, but the projection lens 6 disclosed in, for example, Japanese Patent Application Laid-open No. 130742/1983, which was previously filed by the applicant of the present application, A separate off-axis wafer alignment system, in other words, irradiates alignment marks such as diffraction grating marks on the wafer W with a spot light extending in the alignment direction of the alignment marks, and directs the spot light to a galvano mirror, etc. By using a vibrating mirror to make minute vibrations in a direction approximately perpendicular to the alignment direction of the alignment marks,
The same effect as the LSA system can be obtained even by using an alignment system that detects the position of the alignment mark in the X or Y direction. Furthermore, a device suitable for detecting the formation state of a resist pattern is not particularly limited to an alignment system such as an LSA system or a wafer alignment system provided in the stepper SR. For example, an inspection device 26 (dotted line in FIG. 1) such as a micro-dimensional measuring device using a slit scan method, which is a type of photoelectric measurement, is installed in a lithography apparatus, and a wafer W that has been subjected to development processing, etc. is subjected to substrate processing. The structure is such that it can be carried in from the processing end point 1fP7 of the process. Then, in the inspection device 26, the above-mentioned LSA
By detecting the mark lengths and positions of the resist images R1 and Rs in the same manner as the system, the formation state of the resist pattern can be similarly measured.

Further, as is clear from the flowchart shown in FIG. 3, in this example, the formation state of the resist pattern formed by the main exposure was not detected, but for example, the wafer carried out from part of the day Before W is stored in the unloader cassette 4, the LSA system mentioned above,
The formation state may be detected using the inspection device 26 or the like, and it is clear that the yield can be further improved by detecting the formation state of the resist pattern formed by the main exposure in this way. At this time, the inspection device 26
It is configured so that it can be used in combination with the LSA system (or wafer alignment system), that is, the formation state of the resist pattern formed by the main exposure is controlled by a stepper S such as the LSA system.
If the detection is performed using the inspection device 26 without using the R alignment system, it is possible to prevent a decrease in throughput that may occur due to detecting the formation state of the resist pattern twice.

Furthermore, in this embodiment, a resist stripping device 5 was provided separately from the lithography apparatus as a device for stripping off the resist pattern formed by test exposure. This type of resist stripping device may be incorporated into a CD, or may be configured to serve both as a coater and a resist stripping device by providing a dedicated nozzle for resist stripping on a coater that uses the same organic solvent as the resist stripping device. For example, the lithographic apparatus can be made more compact.

〔Effect of the invention〕

As described above, according to the present invention, in the first exposure (test exposure), the optimum exposure conditions for each shot area on the substrate, that is, the correction values for the optimum exposure time and alignment (overlapping) position are determined, and the In the second exposure (main exposure), the resist pattern is formed on the substrate while controlling the processing conditions of the exposure processing device for each shot area according to the optimal exposure conditions, so the resist layer is It is possible to minimize line width unevenness in the resist pattern caused by changes in the reflectance of the exposure light and alignment light due to uneven underlying film thickness, etc., and a decrease in alignment accuracy between the mask pattern and the chip on the substrate. A highly accurate lithography apparatus that can also improve yield can be realized.

[Brief explanation of the drawing]

FIG. 1 shows a stepper and a coater according to an embodiment of the present invention.
FIG. 2 is a plan view showing the general structure of a stepper, and FIG. 3 is a schematic diagram illustrating the operation of an embodiment of the present invention. FIG. 4 is a diagram showing a schematic configuration of a reticle used in an embodiment of the present invention, and FIG. 5(a) is a diagram showing a schematic configuration of marks for measuring exposure conditions formed on the reticle. Figure 5(b) is a diagram showing a schematic configuration of the mark for measuring positional deviation formed on the reticle, and Figure 6(a) is a diagram showing the resist image of the mark for measuring exposure conditions. A diagram showing the scanning state, Fig. 6(b)
) shows the waveform of the photoelectric signal obtained when the spot light scans the resist image of the mark for measuring the exposure conditions, and FIG. 7(a) shows the state when the spot light scans the resist image of the mark for measuring positional deviation. The figure shown in FIG. 6(b) is a diagram showing the waveform of a photoelectric signal obtained when a spot light scans a resist image of a mark for measuring positional deviation. [Explanation of symbols of main parts] 5... Resist stripping device, 6... Projection lens, 7...
...Wafer stage, 20...Spatial filter, 22
... Light receiving element, 23 ... Laser step alignment system processing circuit, 25 ... Main controller, R ... Reticle, W ... Wafer, spy ... Spot light, S
R...Stepper, CD...Coater/Developer-2M1...Mark for measuring exposure conditions, Ms...Mark for measuring positional deviation.

Claims (6)

[Claims] (1) Consisting of a resist processing device and an exposure processing device having a resist coating section and a developing section, by transporting a predetermined substrate in the order of the resist coating section, the exposure processing device, and the development section, A lithography apparatus for forming a resist pattern on a substrate, comprising: a first transport means for sequentially transporting the substrate to a substrate processing step constituted by the resist coating section, an exposure processing device, and a developing section; The substrate being transported through the process is
a second transport means for transporting the resist from the processing end position of the substrate processing step by at least one of the first transport means and the second transport means; a pattern detection means for detecting the formation state of a pattern; calculating optimal formation conditions for the resist pattern based on the formation state detected by the pattern detection means, and controlling the exposure processing apparatus according to the optimal formation conditions; and a control means for controlling processing conditions, the substrate on which the formation state of the resist pattern has been detected is transported again to the substrate processing step, and the resist pattern is formed under the optimum formation conditions. lithography equipment. (2) The substrate is transported to the substrate processing step again by at least one of the first transport means and the second transport means via a resist peeling means for peeling off the resist layer. The lithographic apparatus according to item 1. (3) The lithography apparatus according to claim 2, wherein the resist stripping means is also used as a resist coating device of the resist coating section. (4) The lithography apparatus according to any one of claims 1 to 3, wherein the control unit transports only the substrate whose formation state is determined to be defective to the substrate processing step again. (5) The lithography apparatus according to any one of claims 1 to 4, wherein the control means calculates the optimum forming conditions for each substrate or for each rod in which a plurality of substrates are stored. (6) The exposure processing apparatus has an alignment system as the pattern detection means, and the alignment system operates to detect the formation state. lithography equipment.