JPH0289149A - Bus priority device - Google Patents

Abstract

PURPOSE:To obtain bus use right without delay when a bus master with a highest priority requests the bus use right by providing a circuit outputting a bus request signal by means of a bus strobe signal from the bus master with highest priority. CONSTITUTION:When a bus request generation block 10 outputs the active bus request signal BS.RQO by an address strobe signal AD.STB.MO from the bus master with highest priority, the output signal of a Q terminal in a D flip 21 comes to a low level. Consequently, the output signals of AND gates 41 and 42 respectively come to the low levels, and a bus available signal BS.AV0 with respect to the bus master with highest priority being the output signal of a NOR gate 43 comes to a high level. Thus, the bus master with highest priority can use the bus without delay when bus masters below a second- order do not use the bus.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a path priority device used in office automation equipment such as personal computers and optical file systems.

Conventional technology FIG. 5 shows a conventional path priority device.

In Figure 5, 1.2.3 are the highest priority and second priority, respectively.
path request signal BS-RQO1 from the lowest path master (not shown); A mountain gate 5 outputs the AND signal of the output signal of the Q terminal of the D flip-flop 1, the output signal of the Q terminal of the D flip-flop 2, and the output signal of the Q terminal of the D flip-flop 2. The M gate 6.7.8 outputs the AND signal of the output signal of the Q terminal of the D flip-flop 1, and the output signal of the gate 4.5 of the D flip-flop 1 as a clock signal. BS-AVQ, which is latched by CLK and sends a path available signal (path usage permission signal) to the highest priority, second priority, and lowest priority path masters.
BS, AVl, BS-A■2 are output smooth flip-flops.

FIG. 6 shows general main signals when a path master uses a path (not shown), in which the path master outputs a path request signal BS-RQ to this path priority circuit, and Available signal BS-AV
The address strobe signal AD-8TB and write/
A read signal WT - RD multiplied signal is output to transfer data between a memory (not shown) and an I10 device (not shown).

In the above configuration, for example, when the highest priority path master outputs the path request signal BS-RtQQ, the D flip-flop 1 latches and outputs this signal BS-RQQ at the next rising edge of the clock signal CLK, and the D flip-flop 6 outputs the signal BS-RQQ. This signal is further converted into the next clock signal CL.
At the rising edge of K, it is latched and a path available signal BS-AVO is output.

In this case, since the output signal of the Q terminal of the D flip-flop l is low level, even if the second and lowest path master request signals BS-RQl and B5-1 (Q2 are output), the path available signal BS. AVI 1BS-
AV2 Power is not output.

Problems to be Solved by the Invention However, in the above-mentioned conventional path priority device, the sixth
As shown in the figure, the path availability signal BS-AV is output in response to the path request signal BS-RQ from the path master and the right to use the path is granted, so even if the highest priority path master requests the right to use this time, There is a problem that it becomes a waiting state.

SUMMARY OF THE INVENTION In view of the above-mentioned conventional problems, it is an object of the present invention to provide a path priority device that can obtain the right to use a path without delay when the highest priority path master requests the right to use the path.

Means for Solving the Problems In order to achieve the above object, the present invention provides a circuit that outputs a path request signal that becomes active in response to a path strobe signal from the path master with the highest priority. When the path request signal becomes active when the path is not in use, a path use permission signal is output to the path master with the highest priority.

Operation According to the present invention, with the above-described configuration, when the second or lower-ranked path master is not using the path, the path mask with the highest priority can use the path without delay by the path strobe signal.

EXAMPLES Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram illustrating an embodiment of the path priority device according to the present invention, and FIGS. 2, 3, and 4 each illustrate the operation of the path priority device shown in FIG. This is a timing chart for

In FIG. 1, IO is activated by the address strobe signal AD-8TB/MO of the highest priority path master (not shown), and the path usage end signal B@MO-END is activated.
The path request signal BS becomes inactive due to
- The path request creation block 11 that outputs RQQ resets the D flip-flop 21 using path available signals BS-AVI, BS・AV2 and read/write signals RD/WT for the second, lowest, and lowest path masters. , a path request-time stop circuit that temporarily stops the path request signal BS-RQQ from the path request creation block 10;
12 is the path available signal BS-AV2 and the lead/
This is a path request-time stop circuit that resets the D flip-flop 22 by the write signal RD/WT and temporarily stops the path request signal BS-RQI from the second-highest priority path master (not shown).

20 are respective path request signals BS-RQQ from the highest priority, second priority, and lowest priority path masks (not shown);
This circuit 20 is a path request request reception circuit for accepting and accepting BS-RQl and BS/Kai 2. This circuit 20 receives the path request signal BS-RQ from the path request-time stop circuit 11
Q, a path request signal BS-RQI from the path request-time stop circuit 12, and a path request signal BS-RQ2 from the lowest path master are input to the D terminals of D flip-flops 21, 22, and 23, respectively.

The Q terminal of the D flip-flop 21 is the M gate 41, 4.
2, and is connected to the input terminal of D flip-flop 22.
The Q terminal of the D flip-flop 23 is connected to the input terminals of M gates 41 and 42, respectively, and the Q terminal of the D flip-flop 23 is connected to the A
It is connected to the input terminal of the ND gate 42.

30 are respective path request signals BS-RQQ and BS-RQ from the highest priority, second priority, and lowest priority path masters;
This circuit 30 is a path use determining circuit that determines the right to use a path based on BS-RQ2 and BS-RQ2. , the output signals of the Q terminals of the D flip-flops 31 and 32 are the path available signals B for the second and lowest path masters, respectively.
S-AVI, BS/AV2.

43 is a No gate that outputs a path available signal BS-AVo for the highest priority path master based on the NOR signal of the output signals of the Q terminals of the D flip-flops 31 and 32.

Next, the operation of the above embodiment will be explained.

FIG. 2 shows a case where there is no path use request from the second or lowest path master. In this case, the output signals of the Q terminals of the D flip-flops 22 and 23 are at low level, so the AND gate The output signals of 41 and 42 are each at low level, therefore the output signals of the Q terminals of D flip-flops 31 and 32 are each at low level, and the path available signal BS-AVO, which is the output signal of NOR gate 43, is at high level. be.

Therefore, the highest priority path master can use the path without delay by outputting the address strobe signal AD-8TB-MO.

FIG. 3 shows a case where the highest priority path master and the second or lowest priority path master request the use of a path within one cycle of the clock signal CIJK. In this case, the path request creation block IO is the highest priority path master. When the active path request signal BS-RQO is output according to the address strobe signal AD-STB-MO from the priority path master, the output signal of the Q terminal of the D flip 21 becomes low level, so that the M-mount gates 41 and 42 The output signals of qAD and ST respectively become low level, and therefore, as in the case shown in FIG.
By outputting B.MO, the path can be used without delay. Therefore, according to the above embodiment, if the second or lowest path master is not using the path, the path with the highest priority is The path master sends the address strobe signal AD-8TB-M
By outputting O, the path can be used without delay.

FIG. 4 shows a case where the second or lowest path master requests the use of the path earlier than the highest priority path master by at least one clock signal αχ;
Path request signal B from the lowest or lowest path master
5-1 (When Qn becomes active, the output signal of the Q terminal of the D flip-flop 22 or 23 becomes high level, and therefore the output signal of the Φ gate 41 or 42 becomes high level, and the output signal of the D flip-flop 31 or 23 becomes high level. 32 latches with the next clock signal CLK, the path available signal B8AVn for the second or lowest path master becomes active, and the path available signal BS-AVO for the highest priority path master becomes inactive.

Next, the address strobe signal AD-8TB-MO from the highest priority path master causes the path request signal BS to be activated.
- When RQQ becomes active, D flip-flop 2
The output signal of the Q terminal of the first circuit becomes low level, but the path request/stop circuit 11 resets the D flip-flop 21 by the active path available signal BS-AVn, and the output signal of the Q terminal becomes high level.

Therefore, the path available signal BSAVn for the second or lowest priority path master continues to be active, and the path available signal BS-AVO for the highest priority path master continues to be inactive. The pass master acquires the right to use the pass.

While the second or lowest level path master is using the path, the path request/time stop circuit 11 is in a state where no problem will occur even if the request from the highest level path master is accepted, for example, the second level path master. Or, the D flip-flop 2 is activated by the fall of the read/write signal RD/WT from the lowest path master.
Reset 1.

Therefore, since the D flip-flop 21 latches the active path request signal BS-RQo, the output signal of its Q terminal becomes low level, and the M mountain gate 41
．． Each of the 42 output signals becomes low level, so the path master with the highest priority acquires the right to use the path.

As described in detail, the present invention includes a circuit that outputs a path request signal that becomes active in response to a path strobe signal from a path master with the highest priority, and when a path is not used by a path master with the second or lower priority. In this case, when the path request signal becomes active, a path use permission signal is output to the highest priority path master, so if the second or lower priority path master is not using the path, , the highest priority path master can use the path without delay due to the path strobe signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the path priority device according to the present invention, and FIGS.
FIG. 5 is a block diagram showing the conventional path priority device, and FIG. 6 is a timing chart showing the main signals of the path master. 10...Path request creation block, 11.12...Path request-time stop circuit, 20...Path request request reception circuit, 30...Path use decision circuit, old, 42...A
ND gate, 43...OR gate. Name of agent: Patent attorney Shigetaka Awano and 1 other person 2nd
Figure No. 3 Kususu ND-4゜ Diagram

Claims (1)

[Claims] a circuit that outputs a path request signal activated by a path strobe signal from the highest priority path master;
When the path request signal becomes active when the second or lower path master is not using the path,
A path priority device includes a circuit that outputs a path use permission signal to a path master with the highest priority.