JPH028751A - Semiconductor integrated circuit tester - Google Patents

Abstract

PURPOSE:To facilitate the maintenance and control of a program for testing by arranging a connection array on a socket body at input and output terminals of a semiconductor IC to be tested to be in a mirror symmetry with the array when the terminal is led directly out of the socket body. CONSTITUTION:When a ceramic chip carrier 2 is set directly on a socket body 11-1, a data terminal 21-1, a clock terminal 21-2, an inversion Q terminal 24-4, a Q terminal 21-5, a power source terminal 21-6 of a circuit chip 21 sealed therein are connected to circuit boards I8, I6, O3, O2 and V1. Even when the circuit chip 21 as wafer is set indirectly on the socket body 11-1 through a wafer prober, the connection of the data terminal 21-1, the clock terminal 21-2, an inversion Q terminal 21-4, the Q terminal 21-5 and the power source terminal 21-4 of the circuit 21 to the circuit boards I8, I6, O2, O3 and V1 is made in a mirror symmetry with that when these are set directly. Thus, an electric characteristic test is accomplished for a ceramic chip, a carrier 2 and the circuit chip 21 as wafer using the same testing program.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to a test device for testing semiconductor integrated circuits with different terminal arrangements, particularly for semiconductor integrated circuits in a wafer state and semiconductor integrated circuits in a package state. The present invention relates to a semiconductor integrated circuit testing device suitable for use.

[Conventional technology]

Traditionally, this type of test equipment has been an IC tester or LS tester.
There is a semiconductor integrated circuit testing device called an I tester. For example, in an IC tester, a large number of pins (for example, 256 bins)
It is equipped with a large number of test signal generation circuits, output determination circuits, power supply circuits, etc. in order to enable testing of the electrical characteristics of ICs. That is, a test signal generation circuit that generates a test signal to be supplied to the input terminal of the IC, an output determination circuit that determines the acceptability of a response signal appearing at the output terminal of the IC, and a power supply that generates power to be supplied to the power supply terminal of the IC. IC
1 of the test signal generation circuit at the plug connection to the input terminal of
one of the output determination circuits is selectively connected to the plug-in connection to the output terminal of the IC, and one of the power supply circuits is selectively connected to the plug-in connection to the power supply terminal of the IC. The control circuit is operated based on the test program written according to the connection combination of the test signal generation circuit, output judgment circuit, and power supply circuit for these plug-in connections, and the control circuit is connected to the plug-in connection. I will be
Set the desired test conditions for C and conduct the electrical characteristics test.

Generally, electrical characteristic tests during the IC manufacturing process are performed both in the wafer process completed state (wafer state) and in the package state. In other words, first, a group of circuit chips built on a wafer is selected for each chip, and then
Out of the pair chips obtained by cutting Ueno 1, only good products are sealed to form a package, and a final test is performed on this package state (packaged IC). For packaged ICs, experiments are conducted by directly contacting the input/output terminals of the packaged IC with the connections of the IC tester, but for circuit chips on a wafer, the connections are electrically connected. This is done through the contact needle of the connected Ueno 1 blower. That is, by bringing the contact needle of the Uni/''t prober into contact with the input/output terminals of the circuit chip, desired test conditions are set for the circuit chip, and the same electrical characteristic test as for the packaged IC is performed.

FIGS. 3(a) and 3(b) are a plan view and a front sectional view showing a schematic configuration of a test head section of a conventionally employed IC tester. By setting a packaged IC as a semiconductor integrated circuit under test on the test head surface 1-1 provided on the upper surface 1-2 of the test head section 1, an electrical characteristic test is performed on the assembled packaged IC. is possible. The tC tester shown in the same figure is
It is possible to test the electrical characteristics of a 6-pin package Ic (for example, the ceramic chip carrier 2 whose plane is shown in FIG. 4), and the test head surface 1
Into the recess step 1 formed in 1, insert a ceramic plate with the input/output terminal forming part 1-1a on the lower side.

Drop in the tube carrier 2 and set it. That is,
Side electrode surfaces 2-1 to 2 as input/output terminals of the ceramic Tsukuchi subcarrier 2 are attached to the connecting portions 1 to 1-16 exposed and provided on the inner side surface of the recessed step portion 1.
5), and the cover 3 is placed so as to cover the top surface of the ceramic chip carrier 2.

The test head section 1 is equipped with a large number of circuit boards that are constructed by dividing test circuits such as a test signal generation circuit, an output determination circuit, and a power supply circuit, and these circuit boards are connected to the connection sections 1 to 1. It is determined either by the combination -ti-te or by selecting the circuit board with the shortest distance from each desired circuit group. In this case, connection portion 1-. 1. , , connect the test signal generation circuit board 1.13 to the output determination circuit board 06.0 to the section 1-15.
The power circuit board V4 is selected and connected to the connection portion 1-16.

FIG. 6 shows a circuit chip (21 shown in FIG. 7) in a wafer state before being sealed in the ceramic chip carrier 2.
A method of attaching the test head section 1 to the wafer blower 4 that enables electrical characteristic testing is shown, and the upper surface 4 of the wafer blower 4 is shown. The upper surface part 1-2 of the rad part 1 is covered and brought into close contact with the heat test, and the connection parts 1 to 1-16 are electrically connected to contact needles (not shown) in the wafer processor 4. That is, as the operating speed of the IC increases, high-speed pulses are handled, and therefore it is required to shorten the signal propagation path during testing as much as possible. By closely contacting the portion 1-2 so as to cover it, shortening of the signal propagation path between each circuit board in the IC tester and each terminal of the circuit chip 21 on the wafer is promoted.

Here, regarding the ceramic chip carrier 2 that is directly set on the test head surface 11 of the test head section 1 and the circuit chip 21 that is indirectly set via the wafer prober 4, the connection parts 1- to 1-16 are Take a look at the terminal arrangement.

As shown in FIG. 7, the L circuit chip 21 has a data (D) terminal 21, a clock (CLK) -1 terminal 21, a ground (GND) terminal 21, and a Q terminal -2.
1-3ゝ21 Q terminal 21 14ゝ-5ゝ as a power supply terminal 21-6 is placed on the mounting part of the ceramic chip carrier 2 with each electrode surface facing upward, and the terminals 21 to 21-6 are connected to the ceramic chip carrier 2. are connected to terminals 2-1 to 2-6. In other words, the ceramic chip carrier 2 is placed on the test head surface l.
If it is directly set to -1, the terminals 21 to 21-6 of the circuit chip 21 will be connected to the l connections 1- to 1-16.

However, when the circuit chip 21 is set indirectly via the wafer blower 4, the circuit chip 21 is turned over with respect to the test head surface 1-1, and the terminals 21 to 21-6 are connected. It will be connected to parts 1- to 1. In other words, the ceramic chip carrier 2 and the circuit chip 21 have the same function (setting test conditions) as D-type flip-flops, but the test head surface 1 during the test is
The terminal arrangements for the connecting portions 1-tt to 1 are different and mirror-symmetrical to each other.

[Problem to be solved by the invention]

For this reason, in the past, circuit chips 2 in wafer state were
1, the connection combinations of the test signal generation circuit board, output judgment circuit board, and power supply circuit board for the connection parts 1-11 to 1-16 in the test head section 1 are different. ing. However, simply changing the combination of connection circuit boards for connection sections 1-1□ to 1-16 results in multiple or long wiring lines inside the test head section 1, which is an initial step to shorten the signal propagation path. It would be contrary to the purpose of Therefore, when testing the circuit chip 21 in the wafer state, the circuit board with the shortest wiring distance for each connection part is reselected from the desired circuit board group. , a new test program is written to correspond to this connection combination. In this example, the power supply port ■ is sent to connection section 1, and the output judgment time is sent to connection sections 1 and 1-13!
-12 Connect the test signal generation circuit boards I6 and 8 to the connections 1- and 1-16.

In other words, conventionally, there are two types of similar test programs for the wafer state and the package state, and maintenance management such as version upgrades must be performed for each of these test programs in parallel. First, there was a problem in that it was easy to make mistakes when updating the program, such as changing one part but forgetting to change the other.

In addition, the task of changing the combination of connections between the circuit boards and the connection portions is extremely troublesome, and there is a high risk of erroneous connections occurring when changing the combination.

[Means to solve the problem]

The present invention was made to solve these problems.
Therefore, the semiconductor integrated circuit under test is supported in the socket body with the input/output terminal forming part facing upward, and the socket lid is placed over the semiconductor integrated circuit under test supported by the socket body. A connecting portion to an input/output terminal of a semiconductor integrated circuit under test is led out from the socket body through the socket.

[Effect]

Therefore, according to the present invention, the connection arrangement on the socket body for the input/output of the semiconductor integrated circuit under test is different from the connection arrangement when the input/output terminals of the semiconductor integrated circuit under test are led out directly from the socket body with the forming part of the input/output terminals on the lower side. It is possible to have mirror symmetry.

〔Example〕

The semiconductor integrated circuit testing apparatus according to this embodiment will be described in detail below.

FIGS. 2(a) and 2(b) are a plan view and a front cross-sectional view showing a schematic configuration of a test head portion of an IC tester showing an embodiment of this test device.

In the figure, 11. is the upper surface part 1 of the test head part 11
The socket body 1-2 is provided, 11-3 is a recessed stepped portion formed on the upper surface of the socket body 11-1, and 11 to 11-6 are the upper edge portions of the socket body 11-1. a plug-in connection configured with a plug-in connection 11;
~11. ．． ．． Test signal generation circuit board I and ■6
However, the output determination circuit boards O and 02 are connected to the plug connections 11 and 11-, and the output determination circuit boards O and 02 are connected to the plug connections 11-16.
A power supply circuit V1 is connected to.

Test head section 11 of the IC tester configured in this way
When testing the electrical characteristics of the ceramic chip carrier 2 using the
1-3, and set the ceramic chip carrier 2 with the input terminal forming part facing upward. That is, the ceramic chip carrier 2 is turned over, and the ceramic chip carrier 2 is set in the recessed stepped portion 11-3 of the socket body 11, with the side electrode surfaces 2-1 to 2-6 forming the input/output terminals facing upward. do. Then, the socket lid 31 is placed so as to cover the ceramic chip carrier 2 supported in the recess step 11-3 of the socket body 11 (FIG. 1). The inner surface of the socket lid 31 has contact portions 31 to 31-6 that contact the electrode surfaces 2-1 to 2-B while covering the ceramic chip carrier 2.
are provided, and by fitting the lead-out plug connections l pins 31 to 31- of the contact portions 31 to 31-6 into the plug connection portions 11-11 to 11-16 of the socket body 11-1, the ceramic Electrode surface 2-2 of chip carrier 2
and the plug connection part 11 in the socket body 11-1
- to 11-6 will be mutually connected. As a result, the electrode surface 2 2 of the ceramic chip carrier 2
are connected to the test signal generation circuit boards I, I through the plug-in connections 11 to 11-1°, and the electrode surfaces 2-4°
Plug-in connection 1. 1-15 to the output determination circuit board 0.0°, and the electrode surface 2 is connected to the power supply circuit board 1 through the insertion connection 1-16.

On the other hand, when performing an electrical characteristic test on the circuit chip 21 in a wafer state, the socket body 11-1 of the test head section 11 is directly covered and brought into close contact with the upper surface of the Uni/1 blower. Its plug connection 11
- 11-16 and the contact needle in the ueno\obber 0-bar are electrically connected.

That is, when the ceramic chip carrier 2 is directly set in the socket main body 11-1, the data terminal 21 of the circuit chip 21 sealed therein, the lock terminal 21, the Q terminal 21, the Q terminal 21-5
, power terminal 21 and circuit board! , 16,03゜02
, Vt. However, even when the circuit chip 21 in a wafer state is indirectly set in the socket main body 11-1 via a wafer prober, the data terminal 2jl of the circuit chip 21 is connected.

Clock terminal 21 Q terminal 21 Q terminal = 2ゝ -4ゝ21 Power terminal 21 and circuit board I,! 65l-6
8 O, O, and V, and as a result, using the same test program, electrical characteristic tests can be performed on the ceramic chip carrier 2 and the circuit chip 21 in the wafer state. Become.

In addition, once the test head part 1 is inserted into the connection part 1
After selectively connecting the circuit boards 1 to 11-6, conduct an electrical characteristic test on both the ceramic chip carrier 2 and the circuit chip 21 in the wafer state without changing the connection combination. This simplifies the number of tasks compared to conventional methods.
Inadvertent misconnections that occur when changing the connection combination of circuit boards are also eliminated.

〔Effect of the invention〕

As explained above, according to the semiconductor integrated circuit testing apparatus according to the present invention, the semiconductor integrated circuit under test is supported by the socket body with its input/output terminal forming portion facing upward, and the semiconductor integrated circuit under test supported by the socket body is The socket lid is designed to cover the socket, and the connection part to the input/output terminals of the semiconductor integrated circuit under test is led out from the socket body through the socket lid, so that the socket for the input/output terminals of the semiconductor integrated circuit under test is The connection arrangement on the main body can be mirror-symmetrical with respect to the connection arrangement when the input/output terminals are directly led out from the socket main body with the forming part of the input/output terminals on the bottom side. It is now possible to test the electrical characteristics of semiconductor integrated circuits in both states using the same test program, making maintenance and management of the test program easier than before, and making it easier to update the program. It has many excellent effects, such as eliminating mistakes.

[Brief explanation of the drawing]

FIG. 1 is a front sectional view showing a state in which a ceramic chip carrier is set in the test head portion of an IC tester showing one embodiment of a semiconductor integrated circuit testing device according to the present invention;
Figures (a) and (b) are a plan view and a front sectional view showing the schematic configuration of the test head section of this IC tester, and Figures (a) and (b) are
A plan view and a front cross-sectional view of the test head section of the IC tester, FIG. 4 is a plan view of a ceramic chip carrier whose electrical characteristics are tested using this IC tester, and FIG. FIG. 3 is a front cross-sectional view showing a state in which the ceramic chip carrier is set in the test head section of the conventional IC tester shown in FIG. FIG. 7 is a plan view showing a circuit chip whose electrical characteristics are tested via the wafer blower. 2... Ceramic chip carrier, 2-1 to 2-6.
... Electrode surface (input/output terminal), 11 ... Test head section, 11 ... Socket body, 11-3 ... Recess step section, 11 - 11.6 ... Plug-in connection section, 31 ...・
Sokerato lid, 31~31...Contact part, 31-1□~
-t -e 31-... Plug-in connection pin, I, Ig...
Exam 16
e signal generation circuit board, 0, O...output determination circuit board, vl...r3 source circuit board. Patent applicant: Sumitomo Electric Industries, Ltd. Representative patent attorney Yoshiki Hase
Salt 1) Tatsuya's Example of Ishiyuki-sama Figure 1 (bl Iseira Techniques Figure 3 (a) (b) Practical Garden Example 2 Figure 4 Figure 5

Claims (1)

[Claims] The socket body is provided with a socket body that supports the semiconductor integrated circuit under test with the input terminal formation portion on the upper side, and a socket lid that covers the semiconductor integrated circuit under test supported by the socket body, and the socket body is inserted through the socket lid. A semiconductor integrated circuit testing device comprising a lead-out path for leading out a connecting portion to an input/output terminal of the semiconductor integrated circuit under test.