JPH0287399A - System for testing semiconductor memory - Google Patents

Abstract

PURPOSE:To facilitate the analysis of a detect, etc., by setting a mode to utilize an input timing to be inhibited on a specification in a dummy static RAM, and realizing a page mode with an action separation between a row side and a column side. CONSTITUTION:In the dummy static RAM, a counter check mode to utilize the mode of the input sequence of an external control pin to be inhibited on the spec and a circuit necessary for realizing it are utilized. Further, the page mode after a counter check is realized by a means to prevent the reset action of a refresh system signal by a chip enable reset such as the addition of a latch circuit 11 to a sequence circuit 1 used for the mode decision of the counter check mode. On the defect analysis and evaluation of a design and a trial early stage, the row side, namely, a refresh action system, and the column side, namely, a data control system, are separated. Thus, the evaluation in the design trial early stage, the estimation of a defect cause at the time of the analysis of the defect, etc., the specification of a defective place, etc., can be easily executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a test method for a semiconductor memory constituted by MO3 type field effect transistors, and particularly to a test method for a semiconductor memory constituted by a one-transistor type dynamix cell, which is easy to use. This paper relates to a test method for a static ram and a pin-compatible static ram.

[Conventional technology]

The goal of the Fragmented Static RAM is to use dynamic cells to achieve the same degree of integration as the Dynamic RAM, while simplifying the complicated refresh operation control unique to dynamic cells, so that it can be handled like a static RAM. It is a dynamic ram that has a lower cost advantage over a static ram, and its position is said to be intermediate between a dynamic ram and a static ram.

Therefore, since the basic memory cell is a dynamic type, a refresh operation is necessary, and the characteristics of a dynamic RAM such as an increase in current consumption associated with it are suppressed, and the key is to suppress the characteristics of a dynamic RAM and bring it closer to a static RAM. This is the first required characteristic.

In order to satisfy this characteristic, the pseudo static RAM uses pins that are not used in the static RAM and the ff (output enable) pin, and uses them as refresh control pins! Various refresh modes are set by using the timing and activation width of this pin.

In particular, the self-refresh mode, which is achieved only by keeping the m pin activated for a long time, corresponds to the standby state of a static RAM, and is the biggest difference from a general-purpose dynamic RAM. This self-refresh mode requires an internal address counter that is configured with a binary counter, etc., and is automatically incremented or decremented, and an internal timer that automatically generates refresh timing.
This mode is entered by keeping the pin activated for a certain period of time.

This internal address counter, similar to the one adopted for the Cas-Before-Las refresh mode installed in a general-purpose dynamic RAM, is internally assigned to a row address and is used to select the word line that is the gate control line of the dynamic cell. You only need the equivalent of the external address to perform
It is not required for addresses corresponding to column addresses.

Conventionally, in pseudo-static RAM, a counter check mode is set to test the internal address counter used in the self-refresh mode described above, and a check is made to see if the internal address generated by the internal address counter is operating normally. ing.

FIG. 6 shows a timing diagram of this counter check mode.

As shown in this figure, first activate the RFSH pin and store the internally generated counter address as the row address, then activate the CE pin and input an arbitrary column address from the outside to select the selected cell. The internal counter operation is tested by determining and performing read and write operations.

This input timing is a mode that is prohibited during normal random access read and - ascending,
This mode is strictly for product testing.

FIG. 5 shows an example of a block diagram for implementing this counter check mode.

This diagram only shows the memory refresh operation section and address control section. As shown in this block diagram, the RFS that is used in the back-to-back refresh mode of a general-purpose dynamic circuit
A sequential circuit between H and σ is required, and γ-r is activated first.2. Furthermore, a first sequential circuit 51 generates a signal φcc that is activated when σd is activated successively.
and this signal φC generated in the counter check mode.
By using C, the counter check mode is realized by means for preventing new changes in the address signal φA input to the row address generation circuit 52. The counter check mode operation will be explained below with reference to the block diagram shown in FIG. 5 and the timing chart 1- in FIG. 6.

Basically, the internal signal φRF that controls the refresh operation
is an external pin that controls refresh.
E- two systems of signals φ□, φ. When φ1 is activated, the internal row address generated by the internal counter is input to the row address generation circuit 52, and when φC is activated, the data on the external address input pin is input to the row address generation circuit 52.

The row address control circuit 53 is controlled by the main clock φRF for refresh control, and the timing is y-system,
It is determined by internal signals φR1φC of each Ur system. Furthermore, the column address is controlled only by the rr system, regardless of the r-system, which controls only the refresh operation.

At time to in FIG. 6, when m- is activated, ? in FIG. Initial stage circuit 54 activates internal signal φ8. This operation enables the internal address counter, opens the switch SWl on the internal address side, and inputs the signal φ having internal address data to the row address generation circuit. At this time, the switch SW2 on the external address side is not open because U'' is not activated.

The row address generation circuit 52 to which the internal signal φ is input,
The signal φ1. which is generated by the logical sum of φC and φC. It is activated by the output φAX of the row address control circuit 53 controlled by , and generates the output address φIAX.

At time t1, when σ is activated as an external address input timing pulse, the U-cho first stage circuit 55 outputs φ
C is activated. The control system on the column side is unrelated to the state of RF S H, so it operates as usual, and while activating the column address control signal φAY, column decoder control signal φDA, etc., output column address φI based on external address data.
Generate A'〆.

On the other hand, regarding the row address, the output row address φIAX based on the internal address has already been output, and the refresh operation of the cells on the designated word line is being performed. For this reason, the operation of inputting an external address and newly outputting the external row address as an output row address is no longer necessary, and it is also inconvenient in terms of checking the internal counter. come. Therefore,
Using the timing of the counter check mode, that is, the output signal φcc of the sequential circuit 51 that occurs when m is activated and σ- is activated while m is continuously activated, This prevents generation of the input signal φS to the address changeover switch SW2.

At time t2, when RFSH and σr are both activated and both row and column addresses have been taken in, when T or OE is activated, the row address from the internal address counter 56 and the column whose output is the external address input data are activated. Memory cell array 5 specified by address φIAY
This means that a write or read operation can be performed on the selected cell No. 7.

When σr is inactivated at time t5, the output signal φRF of the refresh-related main clock generation circuit 58 is reset, and the word line 1 row address φIAX and the like are reset. Furthermore, when m is deactivated at time t6, signal φ is activated.

The memory is set to 1. Return to previous original state.

FIG. 7 shows a specific example of a sequential circuit and its generation timing, and FIG. 8 shows a specific example of a row address system circuit. During normal pulse refresh operation by RFSH, signal 6 is activated and becomes high level, and signal φ
Since C becomes a low level, φcc maintains a low level, and the output signal φS of SW3 maintains a low level, and the row address generation circuit is connected to the row address generation circuit through the transistor of SWI, which uses the signal φ1, which is the activated output signal of the internal address counter, as a gate control signal. The output signal φA is obtained. On the other hand, the main clock φRF activated by the RM side signal φR enables the row address control circuit, and outputs the output signal φAX.
is at a high level, the row address generation circuit is activated and outputs an output signal φIAX.

In addition, when reading, writing, or refreshing is performed using the normal σ cycle, the σT system signal φ is used. is high level, R[system signal φ. Since is at a low level, φcc remains at a low level in this case as well. For this reason, the switch SW3 formed by the inverter I5 and the NOR 01 in FIG. Data. The activation signal φAX of the row address generation circuit is enabled by the φRF signal generated by activation of the σ-type signal φC.

In the counter check mode, the latch circuit formed by the NAND circuits N1 and N2 in the sequential circuit diagram of the seventh section is set by the φR signal which is activated first, and the NAND circuit N3 is enabled. Furthermore, activation of ff causes φ. When the signal becomes high level,
All the inputs of the NAND circuit N3 become high level, and the output signal φCC becomes high level for the first time. This signal φc
Since c is at high level, the output signal φS of the SW3 circuit
maintains a low level, and address φ9. φIAX
This means that the data will no longer be destroyed. With such a circuit, the conventional pseudo-static RAM checks the internal address counter.

[Problem to be solved by the invention]

The conventional pseudo-static RAM check mode described above utilizes the prohibited timing in the specifications, and
It is used only to check the internal address counter used in the refresh operation, and has the disadvantage that checking on the CAS side of the general-purpose dynamic RAM, that is, the side that controls data, cannot be performed as an independent mode.

Conventionally, this type of pseudo-static RAM has focused on compatibility with static RAM, and has often had the same pin arrangement and package, and has also used a synchronous single address input method to control the chip. Since there is only one knee (chip enable) pin, it has become impossible to realize a page mode using a multi-address method using time separation of row and one column addresses as in conventional general-purpose dynamic RAMs.

Therefore, during evaluation at the initial stage of design prototyping, failure analysis, etc., it is often inconvenient to estimate the cause of the failure, identify the location of the failure, etc.

Although it has a cell structure and peripheral circuit configuration similar to a general-purpose dynamic RAM, the external pins are the same as a static RAM, so it is inherently equipped with a page mode that fixes the column address and changes only the row address at will. Because of this, the separation between the dynamic RAM-specific refresh operation and the data input/output control operation is not made clear, making analysis in the event of a defect taking a long time or becoming extremely difficult. Such inconveniences are occurring.

[Means to solve the problem]

The page mode test after the counter check of the present invention is as follows:
W, ?, which was also necessary to realize the conventional counter check mode. : A sequential circuit that determines the T input timing and enters the counter check mode, and a means to newly import an external address when σr is activated in the counter check mode to prevent word switching during sensing. In addition, in the conventional pseudo-static RAM, it means the end of the counter check mode, and the reset of the CE which starts resetting the refresh system such as resetting the word, deactivating the sense amplifier, balancing the digit line, and precharging. Sometimes, the level of the word line,
It has means for maintaining the sense amplifier activated state.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

Figure 1 is a block diagram of an embodiment of the present invention. φCC is an output signal of a sequential circuit as a means to prevent refresh system errors due to reset of 6 units.
Latch R] Σ] "This φc until the shoulder resets.
It has a latch circuit 11 that holds the activated state of the c signal,
This makes it possible to implement page mode after counter check mode.

As can be seen from the block diagram of the conventional circuit shown in FIG. 5 and the conventional φCC signal generation sequential circuit 51 shown in FIG. 7. This was done by inactivating either r.

The mode reset by the automatic reset signal φRR when activated by =RFSH, which is unique to the pseudo-static RAM, is also performed by the signal φ. It cannot be executed because it is blocked by switch SW4 controlled by C.

In contrast to this conventional circuit, by not resetting φCC when σr is deactivated, and by preventing an attempt to take in an external address again when rr is activated again, and by continuing to prevent the automatic reset path. [ controls only the column side, and this counter check mode is canceled only by resetting m.

FIG. 2 shows one specific embodiment of a counter check page mode signal generation circuit including a latch circuit. π]
-f wing - The output φcc is in the initial reset state due to the synchronization signal φa, and the output φcc is then in the initial reset state, and then the σr synchronization signal φ. φ by activating in the order of . . is activated and maintained in the activated state by a latch circuit composed of NANDN5 and N6 that uses its own material as an input signal. After activating in the order of R (I-1σ), it is used as a mode latch signal for counter check page mode, regardless of the state of C, to prevent external address capture when U is activated, and to automatically reset. It is possible to block the bus and implement a counter check page mode.

FIG. 4 shows a timing chart of the counter check page mode of the present invention.

FIG. 3 shows a second concrete example of a counter check page mode signal generating circuit different from that shown in FIG.

As a latch circuit, R-FSH as a reset signal
NAND circuits N5 and N that use synchronization signal φ8 as an input signal
It is an R3 F/F consisting of 8, and the first
Similar to the embodiment of this circuit in , the output signal th of this circuit
cc is activated in the order of nm and σr, and once it enters counter check mode, even if U-cho toggles,
``Unless the 7th floor is reset, it will remain active and the counter check page mode will be possible.

〔Effect of the invention〕

As explained above, the present invention provides a counter check mode in a pseudo-static RAM that utilizes the input order mode of external control pins, which has been prohibited by the existing specifications, and is necessary to realize the counter check mode. In addition, it is possible to add a latch circuit to the sequential circuit used to determine the mode of counter check mode.
Page mode after counter check is realized by means of preventing the reset operation of refresh signals due to reset.
The row side, that is, the refresh operation system, and the column side, that is,
This has the effect of increasing efficiency by separating the data control system and making it possible to mass-produce highly efficient pseudo-static rams in a short period of time.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the counter check page mode of the present invention;
The figure shows a first embodiment of a specific circuit for realizing the present invention, FIG. 3 shows a second embodiment of a specific circuit example, and FIG. 4 is a time chart of the counter check page mode of the present invention. , Fig. 5 is a block diagram for realizing the counter check mode in a conventional pseudo static RAM, Fig. 6 is a timing chart for the conventional counter check mode, and Fig. 7 is a block diagram for realizing the conventional counter check mode. Specific Example of Sequential Circuit FIG. 8 shows a specific example of a row address system circuit used in both the present invention and the conventional example. 1.51...Sequential circuit, 2,52...Row address generation circuit, 3,53...Row address control circuit, 4゜54
...! Initial circuit, 5.55...C] Revised initial circuit, 6,
56...Internal address counter, 7, 57...Memory array, 8.58...Refresh system main clock generation circuit, 1...Latch circuit.

Claims (1)

[Claims] Using a dynamic one-transistor cell, the external control pin is the same as the static RAM, and the write and read operations are controlled by the first external controller as a single address input method without time-separating the row and column addresses. In a pseudo-static RAM performed by a control chip enable pin, a second external control refresh pin and the first external control pin are used to automatically perform a refresh operation specific to a dynamic RAM, which is prohibited by the specifications. A semiconductor memory testing method characterized by setting a mode using input timing and realizing a page mode by separating operations on the row side and column side.