JPH0286744U - - Google Patents
Info
- Publication number
- JPH0286744U JPH0286744U JP16587088U JP16587088U JPH0286744U JP H0286744 U JPH0286744 U JP H0286744U JP 16587088 U JP16587088 U JP 16587088U JP 16587088 U JP16587088 U JP 16587088U JP H0286744 U JPH0286744 U JP H0286744U
- Authority
- JP
- Japan
- Prior art keywords
- parallel
- shift register
- latch circuit
- line head
- cpu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
Description
第１図はブロツク説明図、第２図は説明図、第
３図は説明図、第４図は説明図、第５図は従来技
術の説明図である。
２……シフトレジスタ、４……ラツチ回路、６
……作画ドツト、８……トランジスタアレー、１
０……シフトレジスタ、１２，１４……シフトレ
ジスタ、１６……ＣＰＵ、１８〜２５……シフト
レジスタ、２６……ラツチ回路、２８，３０，３
２……シフトレジスタ、６０……トランジスタア
レー、６２……作画ドツト。
1 is an explanatory diagram of a block, FIG. 2 is an explanatory diagram, FIG. 3 is an explanatory diagram, FIG. 4 is an explanatory diagram, and FIG. 5 is an explanatory diagram of the prior art. 2...Shift register, 4...Latch circuit, 6
...Drawing dot, 8...Transistor array, 1
0... Shift register, 12, 14... Shift register, 16... CPU, 18-25... Shift register, 26... Latch circuit, 28, 30, 3
2...Shift register, 60...Transistor array, 62...Drawing dot.
Claims (1)
したパラレル作画データに基づきトランジスタア
レーを駆動し、作画ドツトをオンオフして印字を
行うようにしたラインヘツドに、ＣＰＵのパラレ
ル作画データを転送する装置において、前記ＣＰ
Ｕのパラレル出力バスのそれぞれにシリアルイン
・パラレルアウト型のシフトレジスタを接続し、
該各シフトレジスタの対応する出力端を前記ラツ
チ回路の入力側にパラレルに接続したことを特徴
とするラインヘツドにおけるデータ転送装置。 In an apparatus for transferring parallel drawing data from a CPU to a line head which drives a transistor array based on parallel drawing data latched by a latch circuit having parallel input/output terminals and turns on and off printing dots to perform printing, the CPU
Connect a serial-in/parallel-out type shift register to each of the U's parallel output buses,
A data transfer device at a line head, characterized in that a corresponding output end of each shift register is connected in parallel to an input side of the latch circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16587088U JPH0286744U (en) | 1988-12-22 | 1988-12-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16587088U JPH0286744U (en) | 1988-12-22 | 1988-12-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0286744U true JPH0286744U (en) | 1990-07-10 |
Family
ID=31452748
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16587088U Pending JPH0286744U (en) | 1988-12-22 | 1988-12-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0286744U (en) |
-
1988
- 1988-12-22 JP JP16587088U patent/JPH0286744U/ja active Pending
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