JPH0286230U - - Google Patents

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Publication number
JPH0286230U
JPH0286230U JP16599788U JP16599788U JPH0286230U JP H0286230 U JPH0286230 U JP H0286230U JP 16599788 U JP16599788 U JP 16599788U JP 16599788 U JP16599788 U JP 16599788U JP H0286230 U JPH0286230 U JP H0286230U
Authority
JP
Japan
Prior art keywords
transistor
parasitic capacitance
circuit
charging
limiting resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16599788U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP16599788U priority Critical patent/JPH0286230U/ja
Publication of JPH0286230U publication Critical patent/JPH0286230U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の一実施例による寄生容量の
高速充電回路を示す回路図、第2図は第1図の制
御回路8の一実施例を示す回路図、第3図は第1
図の高速充電回路の各電位を示す波形図、第4図
は従来の寄生容量充電回路を示す回路図、第5図
は第4図の各電位を示す波形図である。 図において、6はトランジスタ、7は電流制限
抵抗、8はトランジスタON/OFF制御回路を
示す。なお、図中、同一符号は同一、又は相当部
分を示す。
FIG. 1 is a circuit diagram showing a high-speed charging circuit for parasitic capacitance according to an embodiment of this invention, FIG. 2 is a circuit diagram showing an embodiment of the control circuit 8 of FIG. 1, and FIG.
FIG. 4 is a circuit diagram showing a conventional parasitic capacitance charging circuit, and FIG. 5 is a waveform diagram showing each potential of the high-speed charging circuit shown in FIG. In the figure, 6 is a transistor, 7 is a current limiting resistor, and 8 is a transistor ON/OFF control circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] プリント基板上の信号ラインに接続された充電
電流供給用のトランジスタおよび電流制限用の抵
抗と、上記トランジスタのON/OFFのタイミ
ングを制御する制御回路を備えたことを特徴とす
る寄生容量の高速充電回路。
Fast charging of parasitic capacitance, characterized by comprising a charging current supplying transistor and a current limiting resistor connected to a signal line on a printed circuit board, and a control circuit controlling ON/OFF timing of the transistor. circuit.
JP16599788U 1988-12-21 1988-12-21 Pending JPH0286230U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16599788U JPH0286230U (en) 1988-12-21 1988-12-21

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16599788U JPH0286230U (en) 1988-12-21 1988-12-21

Publications (1)

Publication Number Publication Date
JPH0286230U true JPH0286230U (en) 1990-07-09

Family

ID=31452988

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16599788U Pending JPH0286230U (en) 1988-12-21 1988-12-21

Country Status (1)

Country Link
JP (1) JPH0286230U (en)

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