JPH028502B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention provides, for example, a 2n phase-PSK (Phase Shift
Keing) [n=1, 2,...] This relates to a synchronous regeneration circuit for generating synchronous subcarriers used for signal demodulation in a PCM communication system receiver.

[Technical background of the invention and its problems]

In the PSK-PCM communication system, a signal is expressed as a phase component of a signal carrier wave, so in order to demodulate the signal, a phase detector and a subcarrier for signal demodulation that has the same frequency as the signal carrier wave and a specific phase difference are required. is necessary. A system for performing signal demodulation by subcarrier generation is conceptually shown in FIG. 1.

In FIG. 1, a PSK-PCM input signal is introduced to an input terminal 11, and this input signal is demodulated in a phase detector 12 as a code output proportional to the phase difference with the subcarrier. The sign output is led to the output terminal 13 and is also input to the switching circuit 14 . In the switching circuit 14, the information component of the code output is removed, and an output corresponding to the phase difference between the signal carrier wave and the signal demodulation subcarrier wave is generated.
Noise components are removed from this output through a filter 15, and the output is applied as a control signal to a control terminal of a voltage controlled oscillator 16. This causes the voltage controlled oscillator 16 to generate a stable subcarrier.

The switching circuit 14 required in the above system will be further explained, including its surroundings. To simplify the explanation, demodulation of a 4-phase PSK-PCM signal will be explained as an example. It will also be explained that a two-phase PSK-PCM signal demodulation system can be obtained by partially modifying the four-phase PSK-PCM signal demodulation system.

Figure 2 shows a four-phase system using the system shown in Figure 1.
FIG. 2 is a block diagram showing a PSK-PCM signal demodulation circuit. 20 is a 4-phase-PSK-PCM signal input terminal,
21 and 22 are first and second phase shifters, 23 is a switching circuit, 24 is a filter, 25 is a voltage controlled oscillator,
26 is a phase shifter.

The oscillation output of the voltage controlled oscillator 25, that is, the subcarrier, has approximately the same frequency as the carrier of the 4-phase PSK-PCM signal, and its oscillation phase is controlled by the output of the filter 14.

In the first phase detector 21, the phase difference between the subcarrier CW1 from the voltage controlled oscillator 25 and the input signal is detected, and the phase detection output is guided to the output terminal 27 as a code signal.

Further, in the second phase detector 22, the phase difference between the input signal and the subcarrier CW2 obtained by shifting the phase of the subcarrier CW1 by π/2 radians by the phase shifter 26 is detected, and the phase detection output is It is led to the output terminal 28 as a code signal.

Furthermore, the first and second phase detectors 21 and 2
The output of No. 2 is also input to the first and second input terminals 23A and 23B (see FIG. 3) of the switching circuit 23.

In the switching circuit 23, a phase error signal having a period of π/2 radian is formed based on the outputs of the first and second phase detectors 21 and 22.

(This will be further explained in FIG. 4) Furthermore, this phase error signal is passed through a filter 2 for removing noise.
4 to the control terminal of the voltage controlled oscillator 25 to control the phase of the subcarrier. The first and second phase detectors 21 and 22 can each obtain an output proportional to the cosine cos θ of the phase difference θ between the two input signals.

Next, a specific example of the switching circuit 23 will be explained with reference to FIG. The switching circuit 23 is composed of gate circuits 31, 32, 33, 34, inverters 36, 37, and an OR circuit 35, as shown in FIG. The output of the first phase detector 21 is connected to the input terminal 2
The signal is input directly to the gate circuit 31 via 3A and is used as a control signal for the gate circuit 34, and is also input to the gate circuit 32 after passing through the inverter 36 and is used as a control signal for the gate circuit 33.

The output of the second phase detector 22 is connected to the input terminal 23
The signal is input directly to the gate circuit 33 via B and is used as a control signal for the gate circuit 32, and is also input to the gate circuit 34 after passing through the inverter 37 and is added to the control terminal of the gate circuit 32. The gate circuits 31 to 34 are conductive only when the control signal is positive. The outputs of each gate circuit 31 to 34 are combined by an OR circuit 35 and then input to a filter 24.

Next, the operation of the demodulation circuit shown in FIGS. 2 and 3 will be explained with reference to FIG. 4. FIG. 4 shows the signal waveform of each part with the phase difference θ on the X axis (horizontal axis) and the amplitude V on the Y axis (vertical axis).

The input signal phase-modulated based on the digital code is phase-compared with the output of the voltage-controlled oscillator 25 by the first phase detector 21, and a signal a1 proportional to the cosine cos θ of their phase difference θ is detected. Further, in the second phase detector 22, the input signal is compared with the signal phase-shifted by π/2 radians by the phase shifter 26, so a signal a2 proportional to the sine of the phase difference θ - sin θ is detected. .

As mentioned above, the gate operation in the switching circuit 23 is performed so that the control signal is conductive only during the positive period, so if the period is shown with diagonal lines, it will show the relationship between the input signal and the gate operation based on the control signal. is as shown in FIG. 4b. That is, for example, the gate circuit 31 is made conductive for a period of θ=-π/2 to 0 and θ=π to 3π/2 by the control signal of the signal a2, and forms the output signal C1.

Further, the gate circuit 32 uses a signal obtained by inverting the signal a1 by the inverter 36 as an input signal, and uses a signal obtained by inverting the signal a2 by the inverter 37 as a control signal. Therefore, the gate circuit 32
=0 to 3π/4 to form the output signal c2. Similarly, gate circuits 33 and 34
form output signals c3 and c4, respectively, and these signals are combined in an OR circuit 35 to form an output signal c5, that is, a phase error signal c5. Expressing this phase error signal c5 mathematically, c5=sign(a2)・a1+sign(−a1)・a2∝sign
(cosθ) sin [θ−π/4sign(sin2θ)] However, sign(X)=+1(X>0)=−1(X<0), which shows that it is a periodic function of π/2 radian. Therefore, no matter which of the four phases the input signal is in, the phase error signal c5 is at the same level. For example, the phase difference θ is 2i-1/4π (i=0, ±1, ±2... ) by Δθ (−π/4<θ<π/4), this level becomes a signal proportional to sinΔθ.

After the noise component is removed from the phase error signal c5 through the filter 18, the phase error signal c5 is sent to the voltage controlled oscillator 2.
4. In the oscillator 24, the oscillation position is controlled so that the phase error signal c5 becomes zero level in the control direction indicated by the arrow, so that θ=
2i-1/4 Stable at i=0, ±1, ±2, etc. depending on the initial conditions. In this way, subcarriers for demodulating 4-phase PSK-PCM signals can be accurately generated.

By the way, if the signals c1 and c2 are not formed, that is, if the gate circuits 31 and 32 are removed or the connection to the OR circuit 35 is cut off, the OR circuit 3
From 5, only signals c3 and c4 are combined, and the phase error signal c5 is as follows: c5=sign(-a1)a2∝sign(cosθ)sinθ However, sign(X)=+1 (X>0) =-1(X <0). In this way, the phase error signal has a period of π radians, and the oscillator 25 stabilizes at θ=iπ, i=0, ±1, ±2, . . . and becomes a subcarrier for two-phase demodulation. Also, 2
A phase demodulated output is obtained at output terminal 28.

As described above, we have shown how the switching circuit is configured and operates in 4-phase and 2-phase PSK-PCM signal demodulation. To extend this to 2n phase and 4n phase,
The methods disclosed in Japanese Patent Publication No. 53-4789 and Japanese Patent Application Laid-Open No. 48-8453 are used.

The switching circuit 23 shown in FIG. 3 is shown in FIG. 5 with some modifications. Further, FIG. 6 shows a 4n-phase demodulation circuit using the switching circuit 40 of FIG. 5, and FIG. 7 shows a 2n-phase demodulation circuit.

The switching circuit 40 in FIG.
The output terminals of 2 are made common, and the gate circuits 33 and 3 are
4 output terminals are common, output terminals 23C, 23D
It has been established. In the circuits shown in FIGS. 6 and 7, the voltage controlled oscillator 25 and the filter 24 are placed in a common feedback loop, and phase detectors and switching circuits are arranged in parallel in multiple stages.

6 and 7, 41a to 41h are phase detectors, 40a to 40d are switching circuits as shown in FIG. 5, 42 is a combining circuit, and 43a to 43g are phase shifters. In the case of FIG. 6, the switching circuit 40a~
Each of the two output terminals of 40d is connected to the combining circuit 42, but in the case of FIG. 7, only one output terminal of each is connected to the combining circuit 42.

Next, the switching circuit 40 shown in FIG.
We will explain how conventional circuits have been implemented when PSK-PCM signals are input, along with their problems.

Conventionally, the switching circuit 40 as shown in FIG. 5 can be realized by combining discrete elements, or as shown in FIG. 8, operational amplifiers 45, 46, inverters 47, 48, AND circuits 49, 50 ,5
1, 52, and OR circuits 53, 54 are combined to form a circuit configuration.

However, such a configuration has the following problems.

(a) A DC offset occurs in each logic circuit and element, the output level shifts, an error occurs in the oscillation frequency of the voltage controlled oscillator 25, and a signal demodulation error occurs.

(b) Manufacturing costs increase due to an increase in the number of parts, power consumption is high, and reliability is poor.

(c) Since individual logic circuits and elements have different temperature coefficients, depending on the temperature, DC offset may occur, resulting in demodulation errors.

(d) The difference in gain between the two operational amplifiers may cause an output deviation, causing the output level to shift and disrupting signal demodulation.

(e) If a digital element as shown in FIG. 8 is used, a phase error output linearly proportional to the position error cannot be obtained, and the control accuracy of the voltage controlled oscillator is reduced.

(f) If digital elements are used as they are, operational amplifiers 45, 46, phase detectors 41a to 41h,
It is difficult to match with analog elements such as the oscillator 25, and it is difficult to integrate it into a one-chip IC.

(g) A delay occurs at the oscillator control end due to phase shift between the input and output of the amplifier due to the frequency characteristics of the operational amplifier.

(h) The gate control signal is an inverted signal that has passed through an inverter, and instantaneous pulses (whisker-like) may occur due to a shift in gate control timing, which may cause malfunction.

As mentioned above, the conventional switching circuits have various problems, and it is difficult in practice to use the switching circuits 23 and 40 in a high frequency 2n phase-PSK-PCM signal demodulation circuit.

[Purpose of the invention]

This invention was made to eliminate the above-mentioned conventional drawbacks, and aims to provide a synchronous regeneration circuit that is suitable for IC implementation, suitable for PSK-PCM signal demodulation, and capable of obtaining accurate phase difference output. .

[Concept of the invention]

As shown in FIGS. 11a and 9, this invention improves detection accuracy by using a double-balanced differential amplifier as a switching circuit for phase error detection, and improves the detection accuracy of a voltage controlled oscillator. This ensures accurate control.

[Embodiments of the Invention] Examples of the present invention will be described below with reference to the drawings.

FIG. 9 shows an example, in which 4-phase-PSK
- Shows the switching circuit of the PCM signal demodulation circuit.

In FIG. 9, 65 and 66 are input terminals for phase detection output. Next 67, 68, 69, 70,
Reference numeral 71 denotes first to fifth bias power input terminals. Furthermore, 72 is an output terminal for obtaining a control voltage to be applied to the control terminal of the voltage controlled oscillator via a filter.

The input signal from the first phase detector as shown in FIG. 2 is supplied via input terminal 65 to the bases of transistors Q1 and Q2. Transistors Q1 and Q2 are paired with transistors Q3 and Q4 to form a differential amplifier, and transistors Q3 and Q
A first bias power input terminal 6 is connected to the base of 4.
7 is connected. The emitters of transistors Q1 and Q4 are connected to a first constant current source 61, and the emitters of transistors Q2 and Q3 are connected in common through resistors R1 and R2, respectively.
is connected to a constant current source 62. The collector of transistor Q2 is connected to the common emitter of transistors Q9 and Q10 of differential amplifier structure, and the collector of transistor Q3 is also connected to the common emitter of transistors Q11 and Q12 of differential amplifier structure. The second bias power input terminal 68 is connected to the common base of the transistors Q10 and Q11.

Next, the collectors of transistors Q9 and Q12 are connected to a fourth bias current input terminal 70, and the collectors of transistors Q10 and Q11 are connected to a fifth bias power input terminal 71 via a resistor R9. It is connected to the output terminal 72.

The base of the transistor Q9 is connected to the third bias power input terminal 69 via the resistor R5, and the collector of the transistor Q8 is connected to the base of the transistor Q12 via the resistor R6. bias power input terminal 69
is connected, and the collector of transistor Q5 is also connected.

The above transistors Q1 to Q4, Q9 to Q1
2 and resistors R1, R2, R5, R6, constant current source 6
1,62, the symmetrical circuit includes transistors Q5 to Q8, Q13 to Q16, resistors R3, R4, R7, R8, constant current source 63,
64. A signal from the second phase detector is input to the common base of the transistors Q5 and Q6 via the input terminal 66.

Here, the voltage V ₁ of the first bias power supply input terminal 67 is set to be equal to the amplitude center value of the outputs of the first and second phase detectors. The base level of transistors Q9, Q12, Q13, and Q16 depends on the base level of transistors Q1, Q4, Q5, _{and Q8} . The voltage drops by the voltage drop across the resistors R5, R6, R7, and R8 connected to the transistors Q10, Q11, Q14, and Q15.
A voltage equal to the center potential of the two potentials of the bases of transistors Q9, Q12, Q13, and Q16.
V ₂ (second bias power supply input terminal). Voltage V ₃ is selected so that the above conditions can be set. Further, the voltage V ₄ at the fourth bias power input terminal 70 is the current supply power for the entire circuit, and the voltage at the fifth bias power input terminal 71 is
_V5 is the output setting power supply of the circuit, and resistor R9 is the output setting resistor. The voltages V ₄ and V ₅ may be common, and the resistor R9 may be divided into symmetrical circuit parts. Further, the voltages V ₁ to V ₅ are set at potentials such that the transistors in the circuit do not operate in the saturation or cut-off region.

Next, resistors R1 to R4 are connected to transistors Q2 and Q
This is to ensure the output linearity of the differential amplifiers Q3, Q6, and Q7. Depending on the input amplitude,
Output linearity can be maintained even without the resistors R1 to R4, but in this case, the resistors R1 to R4 may be deleted.

The operation of each part of the circuit described above will be further explained.

A differential amplifier circuit constituted by transistors Q2 and Q3 and resistors R1 and R2 constant current source 62 has a first
The output a1 from the phase detector is input, an inverted amplified output -Ka1 is generated at the collector of the transistor Q2, an amplified output Ka1 is generated at the collector of the transistor Q3, and these are transmitted to the emitters of the transistors Q10 and Q11, respectively. Here K is the amplification coefficient of this amplifier. Similarly, transistors Q6, Q
7. A differential amplifier circuit composed of resistors R3, R4, and a constant current source 64 receives the output a2 from the second phase detector as input, and sends the inverted amplified output to the emitter of the transistor Q14 - Ka2 to the emitter of the transistor Q15. Transmits amplified output Ka2.

A differential amplifier circuit composed of transistors Q1 and Q4 and a constant current source 61 outputs the output of the first phase detector.
If a1 is a1>V ₁ , transistor Q1 is conductive,
Transistor Q4 becomes non-conductive, and if a1<V ₁ , transistor Q4 becomes conductive, transistor Q1
becomes non-conductive. The collector of transistor Q1 is connected to the base of transistor Q13 and resistor R7, and the collector of transistor Q4 is connected to the base of transistor Q16 and resistor R8. Therefore, only when the transistor Q1 is conductive, the resistor R7 is connected from the power supply voltage _V3 side.
A conductive path to the constant current source 61 is formed through the resistor R7, and a potential drop occurs at the resistor R7, and the transistor Q13
The base potential v _13B of is v _13B <V ₂ . If the transistor Q1 is in a conductive state, the transistor Q4 is in a non-conductive state, and there is no potential drop across the resistor R8 from the power supply voltage _V3 side, and the base potential _v16 of the transistor Q16 becomes _v16B = _V3 > _V2. Become. Conversely, when transistor Q1 is non-conductive and transistor Q4 is conductive, v _13B >V ₂ and v _16B <V ₂ . Base potentials of transistors Q14 and Q15 v _14B and v _15B
is v _14B = v _15B = V ₂ , so transistor Q
In the differential amplifier circuit composed of Q13 and Q14,
When V _14B >v _13B , that is, when transistor Q1 is conductive, transistor Q14 is conductive, and −Ka2, which is an inverted amplification of the output from the second phase detector, is generated at the collector of transistor Q14.

Similarly, in the differential amplifier circuit composed of transistors Q15 and Q16, when v _15B > v _16B , that is, transistor Q4 is conductive, transistor Q15 is conductive, and a second phase detector is connected to the collector of transistor Q15. amplified the output of
Ka2 occurs. Since the collectors of transistors Q14 and Q15 are connected to each other, the input a1 from the first phase detector to transistor Q1 and
Collector output G1 of transistors Q14 and Q15
The relationship is that if a1>V1, the output G1=-Ka2 If a1<V1, the output G1=Ka2.

Similarly, a differential amplifier circuit consisting of transistors Q5 and Q8 constant current source 63, and a resistor R5,
The input/output relationship between R6 and the two differential circuits of transistors Q9 and Q10 and transistors Q11 and Q12, that is, the input a2 from the second phase detector and the transistors Q10 and Q11.
The relationship with the output G2 generated at the collector of is as follows: if a2>V1, G2=Ka1; if a2<V1, G2=-Ka1.

Using the analysis of the circuit operations of each part explained above, the operation of this switching circuit for demodulating four-phase PSK-PCM signals will be explained with reference to FIG. 1st
In Figure 0, the phase difference θ is plotted on the X-axis and the amplitude V is plotted on the Y-axis.

The phase of the input signal that has been phase modulated based on the digital code is compared with the output of the voltage controlled oscillator in a first phase detector, and the cosine of their phase difference θ is cos θ.
A signal a1 proportional to is detected. In addition, in the second phase detector, a signal obtained by phase-shifting the output signal of the voltage controlled oscillator by π/2 radians by a phase shifter;
The input signals are phase-compared, and the sine of the phase difference θ −sinθ
A signal a2 proportional to is detected. (Figure 10a
(See) These signals a1 and a2 are input to input terminals 65 and 66 of the switching circuit shown in FIG. The outputs G1 and G2 of this switching circuit have a form as shown in FIG. 10b. Taking output G1 as an example, by controlling input a1, it outputs -Ka2 which is inverted amplification of input a2 at θ=-π/2 to π/2, and input a2 is inverted and amplified at θ=π/2 to 3/2π. Outputs amplified Ka2. The square wave shown in the figure represents the control state by input a1. These outputs
G1 and G2 are combined by circuit wiring to form a phase error signal such as output G3, which is transmitted to the filter via the output terminal 72. Expressing this phase error G3 mathematically, G3=G1+G2=sign(-a)・Ka2+sign(a2)・Ka1
∝sign(cosθ)sin [θ−π/4sign(sin2θ)] However, sign(X)=+1(X>0) =−1(X<0) This is explained in the switching circuit in Figure 3 above. It has the same format as the phase error output signal c5. Therefore, when this circuit is used as a switching circuit as shown in Fig. 3, the voltage controlled oscillator outputs four phases -
Subcarriers for PSK-PCM signal demodulation can be generated accurately.

In addition, when used for demodulating two-phase PSK-PCM signals, if only output G1 is taken out as output, G1 = sign (-a1) · Ka2 ∝ sign (cos θ) sin θ where sign (X) = +1 ( X>0)=-1(X<0), which corresponds to the phase error output signal c5 when the switching circuit is first modified for two-phase use. Therefore, even in the case of two-phase PSK-PCM signal demodulation, accurate subcarriers can be obtained by using this circuit. 2n phase,
In order to use it for demodulating 4n-phase PSK-PCM signals, this circuit can be applied to the switching circuit of the system shown in FIGS. 6 and 7.

[Other embodiments of the invention]

The basic circuit of the switching circuit according to the present invention is of the form shown in FIG. 11a. Here, constant current source 6
1,62 transistors Q1-Q4, Q9-Q1
2. Resistance R1, R2 and resistance R5, R6, resistance R
9. Bias power input terminals 68 to 71 are shown according to the circuit of FIG. The resistor R9 may be divided for each circuit block, or may be provided all at once for the entire basic circuit used. Further, the power supply voltages V ₄ and V ₅ may be the same. Furthermore, even if the inputs exclude resistors R1 and R2, transistors Q2 and Q3
The resistors R1 and R2 may be removed as long as linearity can be maintained in the output of the differential amplifier circuit configured by the above. T1 to T6 are used as terminals.

When the above basic circuit is shown in terms of signal input/output relationships, it can be shown as a block as shown in FIG. 11b. The circuit of FIG. 9 is shown using the basic circuit 80 shown in FIG. 11b, and as shown in FIG. terminal T5b,
Terminal T4a and terminal T3b, terminal T5a and terminal T2
b, the terminal T6a and the terminal T6b are connected to each other. When two basic circuits 80a and 80b are used, similar operational functions can be obtained even with the connection shown in FIG. 11d. Note that the first
The configuration shown in Figure 1c and d is for 4n-phase PSK-PCM signal demodulation, but in the case of 2n-phase PSK-PCM signal demodulation, the output of the basic switching circuit that receives input from the first phase detector What is necessary is to prevent the information from being transmitted to the filter. The above circuit is convenient to integrate and is also flexible in use, as shown in Figures 11c and d.

〔Effect of the invention〕

According to the present invention described above, it is possible to obtain an inverted output and a normal output using a differential amplifier, and the problem of DC offset can be solved, and in terms of manufacturing, it is easy to use an IC, and the number of parts can be reduced. ,Also,
It is possible to provide a synchronous regeneration circuit that is easy to match with analog elements and can obtain accurate phase output.

[Brief explanation of drawings]

Fig. 1 is a configuration explanatory diagram showing a phase detection method using subcarriers, Fig. 2 is a configuration explanatory diagram of a 4-phase PSK-PCM signal demodulation circuit, and Fig. 3 is a configuration explanatory diagram showing the switching circuit of Fig. 2. , FIG. 4 is a signal waveform diagram shown to explain the operation of the switching circuit of FIG.
The figure is a configuration explanatory diagram showing a switching circuit applied to a 2-phase PSK-PCM signal demodulation circuit, and Figure 6 is a 4n-phase -
FIG. 7 is a configuration explanatory diagram showing a PSK-PCM signal demodulation circuit. FIG. 8 is a configuration explanatory diagram showing an example of a conventional switching circuit. Figure 10 is a circuit diagram showing an embodiment of the present invention, Figure 10 is a signal waveform diagram shown to explain the operation of the circuit in Figure 9, Figures 11a and 11b.
are circuit diagrams and block diagrams showing the basics of the present invention.
1c and 11d are diagrams each showing an example of the use of the block shown in FIG. 1b. 12, 41a to 41h...phase detector, 14,
23, 40a to 40d...Switching circuit, 15, 24
... Filter, 15, 25 ... Voltage controlled oscillator,
26, 43a to 43g...phase shifter, Q1 to Q16
...transistor, R1 to R8...resistance.

Claims (1)

[Claims] 1. A voltage controlled oscillator, a plurality of phase detectors to which an input signal based on the PSK method is applied to one input terminal of each, and a voltage controlled oscillator to the other input terminal of each of the plurality of phase detectors. means for setting and inputting oscillation outputs from an oscillator so that their phases are different from each other; a switching circuit to which the outputs of the plurality of phase detectors are input and detecting a phase error between the respective input signals; and the switching circuit. A synchronous regeneration circuit comprising at least a filter that smooths the output of the first phase detector and applies the output to the control terminal of the voltage controlled oscillator, wherein the switching circuit is configured to smooth the output of the first phase detector and apply the output to the control terminal of the voltage controlled oscillator. a second transistor, a third and a fourth transistor to whose bases a first bias power supply is applied; and a third and fourth transistor connected to their common emitters such that said first and fourth transistors form a first differential amplifier. a first constant current source,
a second constant current source connected to the common emitter side of the second and third transistors so as to form a second differential amplifier; a second constant current source whose emitters are commonly connected to the collectors of the second transistors; The emitters are commonly connected to the collectors of the fifth and sixth transistors forming the third differential amplifier, and the fourth transistor.
a seventh and eighth transistor forming a differential amplifier; a second bias power supply connected to the bases of the sixth and seventh transistors; and a resistor connected to the bases of the fifth and eighth transistors, respectively. a third bias power supply connected via the fifth and eighth bias power supplies;
A first basic circuit comprising a fourth bias power supply connected to the collector of the transistor, and means for deriving an output from a common collector of the sixth and seventh transistors, and a second basic circuit having a similar structure. a second basic circuit into which the output of the phase detector is input and whose output is combined with the output of the first basic circuit;
The bias power supply voltage is set to an intermediate value of the output amplitude of the phase detector, and the second bias power supply voltage is set to an intermediate value of the binary voltages that the bases of the fifth and eighth transistors can take. Features a synchronous playback circuit. 2. In the first and second basic circuits, the collector of the first transistor of the first basic circuit is connected to the base of a fifth transistor constituting the second basic circuit, and The base of the fifth transistor constituting the circuit is connected to the collector of the fourth transistor constituting the second basic circuit, and the collector of the fourth transistor constituting the first basic circuit is connected to the collector of the fourth transistor constituting the second basic circuit. The base of the eighth transistor forming the basic circuit is connected to the base of the eighth transistor forming the basic circuit, and the base of the eighth transistor forming the first basic circuit is connected to the collector of the first transistor forming the second basic circuit. A synchronous regeneration circuit according to claim 1, characterized in that: 3 In the first and second basic circuits, the collector of the first transistor forming the first basic circuit is connected to the base of the eighth transistor forming the second basic circuit, and the collector of the first transistor forming the first basic circuit is connected to the base of the eighth transistor forming the second basic circuit. The base of the fifth transistor constituting the basic circuit is connected to the collector of the first transistor constituting the second basic circuit, and the collector of the fourth transistor constituting the first basic circuit is connected to the collector of the first transistor constituting the second basic circuit. 2
The base of the eighth transistor forming the first basic circuit is connected to the base of the fifth transistor forming the basic circuit, and the base of the eighth transistor forming the first basic circuit is connected to the collector of the fourth transistor forming the second basic circuit. A synchronous regeneration circuit according to claim 1, characterized in that: 4. The synchronous regeneration circuit according to claim 1, wherein the first and second basic circuits are each independently integrated circuits. 5. The synchronous regeneration circuit according to claim 1, wherein the first and second basic circuits are integrally integrated. 6 The number of the plurality of phase detectors is n (n is an integer), and the number of switching circuits using the first and second basic circuits is n/2. The synchronous regeneration circuit described in item 1.