JPH0284450U - - Google Patents

Info

Publication number
JPH0284450U
JPH0284450U JP16367388U JP16367388U JPH0284450U JP H0284450 U JPH0284450 U JP H0284450U JP 16367388 U JP16367388 U JP 16367388U JP 16367388 U JP16367388 U JP 16367388U JP H0284450 U JPH0284450 U JP H0284450U
Authority
JP
Japan
Prior art keywords
circuit
output
input
light emitting
emitting element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16367388U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP16367388U priority Critical patent/JPH0284450U/ja
Publication of JPH0284450U publication Critical patent/JPH0284450U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図及び第2図はこの考案実施例の回路図、
第3図は従来例の回路図である。 5……受光素子、6……増幅回路、8……整流
回路、10……基準電圧、9……比較回路、11
……レベル判別回路、12……スイツチ回路。
Figures 1 and 2 are circuit diagrams of the embodiment of this invention;
FIG. 3 is a circuit diagram of a conventional example. 5... Light receiving element, 6... Amplifying circuit, 8... Rectifying circuit, 10... Reference voltage, 9... Comparing circuit, 11
...Level discrimination circuit, 12...Switch circuit.

補正 平1.3.31 図面の簡単な説明を次のように補正する。Correction: Heisei 1.3.31 The brief description of the drawing has been amended as follows.

【図面の簡単な説明】 第1図及び第2図はこの考案実施例の回路図、
第3図は従来例の回路図である。 5……受光素子、6……増幅回路、8……整流
回路、10……基準電圧、9……比較回路、11
……レベル判別回路、12……スイツチ回路。
[Brief Description of the Drawings] Figures 1 and 2 are circuit diagrams of the embodiment of this invention;
FIG. 3 is a circuit diagram of a conventional example. 5... Light receiving element, 6... Amplifying circuit, 8... Rectifying circuit, 10... Reference voltage, 9... Comparing circuit, 11
...Level discrimination circuit, 12...Switch circuit.

Claims (1)

【実用新案登録請求の範囲】 入力パルス信号を光信号に変換する発光素子
3を含む送信回路と、前記発光素子3の光信号を
受光して電気信号に変換する受光素子5を含む受
信回路を具備する光伝送回路において、受信回路
が次の構成を具備することを特徴とする。 (1) 前記受光素子5の出力を一方の入力とす
る増幅回路6、 (2) 前記増幅回路6出力に接続された整流回
路8、 (3) 前記整流回路8出力を一方の入力に、基
準電圧10を他方の入力とし、前記増幅回路6の
他方の入力に出力を接続した比較回路。 入力パルス信号を光信号に変換する発光素子
3を含む送信回路と、前記発光素子3の光信号を
受光して電気信号に変換する受光素子5を含む受
信回路を具備する光伝送回路において、受信回路
が次の構成を具備することを特徴とする。 (1) 前記受光素子5の出力を一方の入力とす
る増幅回路6、 (2) 前記増幅回路6出力に接続された整流回
路8、 (3) 前記整流回路8出力を一方の入力に、基
準電圧10を他方の入力とした比較回路、 (4) 前記整流回路8の出力に接続されたレベ
ル判別回路11、 (5) 前記レベル判別回路11の出力により前
記比較回路9出力を前記増幅回路6の他方の入力
若しくはアースに選択的に接続するスイツチ回路
12。
[Claims for Utility Model Registration] A transmitting circuit including a light emitting element 3 that converts an input pulse signal into an optical signal, and a receiving circuit including a light receiving element 5 that receives the optical signal of the light emitting element 3 and converts it into an electrical signal. The optical transmission circuit is characterized in that the receiving circuit has the following configuration. (1) An amplifier circuit 6 which has the output of the light receiving element 5 as one input, (2) A rectifier circuit 8 connected to the output of the amplifier circuit 6, (3) A reference circuit with the output of the rectifier circuit 8 as one input. A comparator circuit having a voltage 10 as the other input and an output connected to the other input of the amplifier circuit 6. In an optical transmission circuit comprising a transmitting circuit including a light emitting element 3 that converts an input pulse signal into an optical signal, and a receiving circuit including a light receiving element 5 receiving the optical signal of the light emitting element 3 and converting it into an electrical signal, The circuit is characterized by having the following configuration. (1) An amplifier circuit 6 which has the output of the light receiving element 5 as one input, (2) A rectifier circuit 8 connected to the output of the amplifier circuit 6, (3) A reference circuit with the output of the rectifier circuit 8 as one input. (4) a level discrimination circuit 11 connected to the output of the rectifier circuit 8; (5) an output of the comparator circuit 9 connected to the output of the level discrimination circuit 11; A switch circuit 12 selectively connects to the other input or to ground.
JP16367388U 1988-12-16 1988-12-16 Pending JPH0284450U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16367388U JPH0284450U (en) 1988-12-16 1988-12-16

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16367388U JPH0284450U (en) 1988-12-16 1988-12-16

Publications (1)

Publication Number Publication Date
JPH0284450U true JPH0284450U (en) 1990-06-29

Family

ID=31448603

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16367388U Pending JPH0284450U (en) 1988-12-16 1988-12-16

Country Status (1)

Country Link
JP (1) JPH0284450U (en)

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