JPH0284437U - - Google Patents
Info
- Publication number
- JPH0284437U JPH0284437U JP16270288U JP16270288U JPH0284437U JP H0284437 U JPH0284437 U JP H0284437U JP 16270288 U JP16270288 U JP 16270288U JP 16270288 U JP16270288 U JP 16270288U JP H0284437 U JPH0284437 U JP H0284437U
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- current limiter
- base
- emitter
- output terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Description
第１図はこの考案の一実施例を示すブロツク図
、第２図は従来の技術を説明するためのブロツク
図、第３図Ａ，ＢはＣＭＯＳデイバイスの持つサ
イリスタ構造を説明するための図、第４図Ａ，Ｂ
はカレントリミツタの特性を説明するための図で
ある。
図中１は電源、２はフの字特性を持つカレント
リミツタ、３は複数のキヤパシタ、４は第１の抵
抗、５は第１のトランジスタ、６は第２の抵抗、
７は第３の抵抗、８は第２のトランジスタ、９は
負荷回路である。なお図中同一符号は同一又は相
当部分を示す。
FIG. 1 is a block diagram showing an embodiment of this invention, FIG. 2 is a block diagram for explaining the conventional technology, and FIGS. 3A and B are diagrams for explaining the thyristor structure of a CMOS device. Figure 4 A, B
is a diagram for explaining the characteristics of a current limiter. In the figure, 1 is a power supply, 2 is a current limiter with fold-back characteristics, 3 is a plurality of capacitors, 4 is a first resistor, 5 is a first transistor, 6 is a second resistor,
7 is a third resistor, 8 is a second transistor, and 9 is a load circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
つカレントリミツタ、上記カレントリミツタの出
力端子とアースラインとの間に接続される複数の
キヤパシタ、エミツタ端子を上記カレントリミツ
タの出力端子に接続されコレクタ端子が負荷回路
の電源ラインに接続されエミツタとベースを第１
の抵抗で接続される第１のトランジスタ、上記カ
レントリミツタの出力端子に接続されるベース端
子とアースラインとの間に第２の抵抗が接続され
エミツタ端子が接地されコレクタ端子が第３の抵
抗を介して上記第１のトランジスタのベースに接
続される第２のトランジスタとを備えたことを特
徴とするラツチアツプ保護回路。 A current limiter with a fold-back characteristic that is powered by an external power supply, multiple capacitors connected between the output terminal of the current limiter and the earth line, and an emitter terminal connected to the output terminal of the current limiter. The collector terminal is connected to the power supply line of the load circuit, and the emitter and base are connected to the first
A second resistor is connected between the base terminal connected to the output terminal of the current limiter and the ground line, the emitter terminal is grounded, and the collector terminal is connected to the third resistor. a second transistor connected to the base of the first transistor via a latch-up protection circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16270288U JPH0284437U (en) | 1988-12-15 | 1988-12-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16270288U JPH0284437U (en) | 1988-12-15 | 1988-12-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0284437U true JPH0284437U (en) | 1990-06-29 |
Family
ID=31446767
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16270288U Pending JPH0284437U (en) | 1988-12-15 | 1988-12-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0284437U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018181004A1 (en) | 2017-03-28 | 2018-10-04 | リンテック株式会社 | Gas barrier laminate |
-
1988
- 1988-12-15 JP JP16270288U patent/JPH0284437U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018181004A1 (en) | 2017-03-28 | 2018-10-04 | リンテック株式会社 | Gas barrier laminate |