JPH028326B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a logic control device constituted by a semiconductor integrated circuit or the like, and particularly relates to a logic control device installed inside the logic control device, for example, when the power is turned on. This invention relates to an initial setting circuit used for reset.

[Conventional technology]

FIG. 6 shows a logic control device used for switching recording and playback modes of a tape recorder. This logic control device consists of a main circuit section 2 made up of a semiconductor integrated circuit, and additional circuits such as capacitors externally connected to this main circuit section.

That is, in the main circuit section 2, the power-on circuit 4 is formed with terminals 8 and 10, and the terminal 8
A power supply 20 is connected to the terminal 10 through a time constant circuit 16 and a power switch 18 consisting of a resistor 12 and a capacitor 14, and a capacitor 22 is connected to the terminal 10, and the power supply 20 is connected to the terminal 10 through the power switch 18. ing.

Therefore, the power-on circuit 4 supplies power to the control circuit 24 and the clock oscillator 26 based on the turning on of the power switch 18, and
Using the fact that the voltage rises with a predetermined time _constant via the time constant circuit 16, as shown in FIG. When _th is reached, an initialization signal is generated and applied to the control circuit 24.

The control circuit 24 includes a plurality of logic circuits such as flip-flop circuits, and when the power is turned on, an initial setting signal is applied from the power-on circuit 4 to initialize the various logic circuits. In other words, the various logic circuits included in the control circuit 24 start operating when the power supply 20 is turned on, but the initial settings maintain the logic conditions of each logic circuit in an appropriate state to prevent malfunctions. It is something we do for the purpose of doing so.

The control circuit 24 also includes a motor pause input terminal 28, an AF mute terminal 30,
Motor drive output terminals 32, 34, grounding terminal 36, plunger output terminals 38, 40 for tape direction switching mechanism, motor speed control output terminal 42, recording/playback switch connection terminal 4
4, etc. are formed, and various logic outputs such as motor control outputs are generated based on control inputs such as recording/playback switching inputs.

Terminals 46 and 48 of clock oscillator 26
A resistor 50 and a capacitor 52 for setting an oscillation time constant are connected to the clock oscillator 26.
generates a clock signal with an oscillation frequency set by a time constant determined by resistor 50 and capacitor 52.

[Problem that the invention seeks to solve]

If a dedicated circuit for initial settings, such as a power-on circuit, is installed in such a logic control device, the number of circuits increases, and setting the operating timing and initial setting timing is difficult, resulting in improper timing errors. This may cause malfunction due to initial settings.

Therefore, the present invention aims to realize initial setting with a simple configuration and to achieve highly reliable initial setting.

[Means for solving problems]

That is, the present invention provides a logic control device including a clock oscillator, which includes a time constant setting capacitor installed in the clock oscillator, a reference voltage setting circuit that instantaneously generates a reference voltage in response to power-on, and a reference voltage setting circuit that instantly generates a reference voltage when power is turned on. It is equipped with a comparator that compares the reference voltage set by the voltage setting circuit with the rise of the charging voltage of the capacitor and generates an output when the charging voltage of the capacitor is higher than the reference voltage, and the output of the comparator is connected to the logic circuit. This is used as an initial setting signal.

[Effect]

Therefore, the present invention uses a comparator to compare the rise of the voltage of the time constant setting capacitor installed in the clock oscillator when the power is turned on with the reference voltage, and uses the comparison output as the initial setting output. .

〔Example〕

Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings.

FIG. 1 shows an embodiment of an initial setting circuit for a logic control device according to the present invention, and the same parts as in the logic control device shown in FIG. 6 are given the same reference numerals.

In FIG. 1, the initial setting circuit 54 is constructed by using a reference voltage setting circuit 55 forming a part of the clock oscillator 26 and a capacitor 52 for setting an oscillation time constant, and adding a comparator 56 thereto. There is.

The clock oscillator 26 is connected to the reference voltage setting circuit 5.
5, a comparator 58, switch circuits 60, 62, a transistor 63, resistors 64, 66, and a capacitor 52 externally connected via a terminal 48.

The reference voltage setting circuit 55 includes a plurality of resistors 68 installed between the positive potential line and the ground line.
It is composed of a voltage dividing circuit consisting of 70, 72, 74, and 76, and the resistors 74 and 76 are installed for the initial setting circuit 54. That is, this reference voltage setting circuit 55 divides the voltage Vcc applied between the positive potential line and the ground line when the power switch 18 is closed by a predetermined resistance ratio, and sets the upper limit reference for oscillation. Voltage Vr is set at the connection point between resistor 68 and resistor 70, and reference voltage _V1 for initial setting is set at the connection point between resistor 72 and resistor 74. Resistors 70, 7 of this reference voltage setting circuit 55
A transistor 63 connected between terminals 2, 74, and 76 constitutes a hysteresis circuit.

The terminal voltage of the capacitor 52 is applied to the non-inverting input terminal (+) of the comparator 56 of the initial setting circuit 54, and the reference voltage V _I is applied to its inverting input terminal (-).

Additionally, a comparator 56 is connected between the terminals of the resistor 76.
After generating the initial setting output, a transistor 78 is configured as a switching element that constitutes a hysteresis circuit that prevents the output of the comparator 56 from inverting unless the power is removed and the power is turned on again. comparator 5
6 outputs are added.

Based on the above configuration, its operation will be explained with reference to FIG.

When the power switch 18 is closed, the reference voltages V _r and V _I are set in the reference voltage setting circuit 55 , and a charging current flows through the capacitor 52 via the switch circuit 60 and the resistor 64 . Reference voltage
Since V _r and V _I are set by a resistor voltage divider circuit, they rise instantaneously, whereas the terminal voltage of the capacitor 52 rises with a time constant determined by the capacitance of the capacitor 52 and the resistance value of the resistor 64. In this case, the switch circuit 60 is configured to open at the inverted output of the comparator 58. In other words, when the power is turned on,
Since the charging voltage of the capacitor 52 is lower than the reference voltage V _r set at the inverting input terminal (-) of the comparator 58, the comparator 58 generates a non-inverting output and becomes a low level output, so the switch circuit 60 Closed.

At this time, transistor 63 also becomes non-conductive. Also, when comparator 56 produces a non-inverting output and is a low level output, transistor 78 is also non-conducting.

In A of FIG. 2, A _p indicates the transition of the terminal voltage due to charging of the capacitor 52 when the power is turned on.
That is, when the charging of the capacitor 52 progresses and its terminal voltage exceeds the reference voltage _VI , the comparator 56 becomes
As shown in Figure 2C, an inverted output (H) is generated,
This becomes the initial setting output IR for the logic circuit of the control circuit 24.

When this initialization output IR occurs, transistor 78 becomes conductive and resistor 76
The reference voltage V _I is short-circuited through the resistors 74, 7
Since the voltage is set by the voltage drop from 6 to approximately only the voltage of the resistor 74, it is lower than when the power is turned on. As a result, the inverted output state of the comparator 56 is maintained, and its initial setting output IR is not canceled unless the current is turned off and the power is turned on again. This provides a hysteresis effect.

Even after the initial setting output IR is generated, the capacitor 52 is further charged, and when its terminal voltage exceeds the reference voltage V _r , the comparator 58 is inverted, and its inverted output is connected to the base of the switch circuit 62 and the transistor 63. added to. That is, transistor 63 conducts with this inverted output, and the reference voltage
V _r changes from the value set by the voltage drop across resistors 70, 72, 74 and the saturation voltage of transistor 78 to the voltage drop across resistor 70 and the saturation voltage of transistor 78.
The voltage drops to the value set by the saturation voltage.

Further, the switch circuit 62 is configured to be closed by the inverted output of the comparator 58.
When the switch circuit 62 is closed by the inverted output of the switch circuit 62 and the resistor 66
A discharge circuit is constructed through the. In this case, the capacitor 52 is discharged with a discharge time constant determined by the capacitance of the capacitor 52 and the resistance value of the resistor 66.

As the discharge of the capacitor 52 progresses and its terminal voltage becomes lower than the reference voltage V _r , the comparator 58 inverts and generates a non-inverting output (H), and the capacitor 5
2 becomes a charged state, and the transistor 63
becomes non-conductive, so the reference voltage V _r shifts to the higher side.

That is, when the capacitor 52 is in a charging state, the reference voltage V _r is set to the high side, and the comparator 58
When V r is reversed, the reference voltage V _r is changed to a lower side and the capacitor 52 becomes discharged, and as shown in FIG. A clock signal CK is generated in the comparator 58 as shown in FIG. In A of FIG. 2, V _H indicates the higher side of the reference voltage V _r and V _L indicates the lower side of the reference voltage V _r .

With this configuration, the initial setting circuit 54 can be configured using a part of the clock oscillator 26, and the circuit configuration can be simplified and the initial setting output IR can be generated before clock oscillation occurs.
There is no need to individually set the timing between the two, and highly reliable operation timing and initial setting timing can be obtained.

3 to 5 show other embodiments of the charging/discharging circuit for the capacitor 52 of the above embodiment. In the embodiment described above, a charging or discharging circuit for the capacitor 52 was constructed using the switch circuits 60, 62 and the resistors 64, 66.
In the embodiment shown in the figure, a constant current circuit constitutes a charging circuit or a discharging circuit, and a capacitor 52
The charging and discharging of the battery is switched by the output of the comparator 58.

In the circuit shown in FIG. 3, a charging circuit 600 and a discharging circuit 620, which are switched in response to the output of the comparator 58, are attached to the capacitor 52. That is, the charging circuit 600 is composed of transistors 80, 82, 84 and a resistor 86, and a control input terminal 88 formed at the base of the transistor 84 is connected to the comparator 5 of the circuit shown in FIG.
The inverted signal of the clock signal output CK of No. 8 is added as a control input. And transistor 8
0 and 82 constitute a current mirror circuit, and a transistor 84 constitutes a switch that generates and releases a constant current according to the output of the comparator 58.

Further, the discharge circuit 620 includes transistors 90,
92, 94 and a resistor 96, and a control input terminal 98 formed in the transistor 90 has the output CK of the comparator 58 as well as the control input terminal 88.
The inverted signal of is added as a control input. Transistors 92 and 94 constitute a current mirror circuit, and transistor 90 receives the output of comparator 58.
It constitutes a switch that generates and releases constant current according to CK.

According to such a configuration, when the terminal voltage of the capacitor 52 is lower than the reference voltage V _r , the comparator 58
generates a non-inverted output, and the inverted output serves as the control input, so that both control input terminals 88 and 98 are at a high level, transistor 84 is conductive, and transistor 90 is non-conductive. At this time, a constant charging current flows through the capacitor 52 from the transistor 82, and the terminal voltage of the capacitor 52 increases due to charging.

In this case, the power supply voltage is V _cc and the transistor 84
Let the base-emitter voltage be V _BE84 and the saturation voltage be
When V _SAT84 and the resistance value of the resistor 86 are R ₈₆ , the constant current I flowing through the capacitor 52 is I=(Vcc−V _BE84 +V _SAT84 )/R ₈₆ .

Also, the terminal voltage of the capacitor 52 is the reference voltage
When V _r is reached, the comparator 58 generates an inverted output, and its inverted signal CK becomes the control input to the control input terminals 88 and 98.
98 are both at a low level. In other words, the operations of transistors 84 and 90 are opposite to those during charging, with transistor 84 being non-conducting and transistor 9 being non-conducting.
0 transitions to a conductive state. At this time, a discharge current equivalent to the constant current I flows from the capacitor 52 to the transistor 94, and the terminal voltage of the capacitor 52 decreases over time due to the discharge.

Therefore, charging and discharging of the capacitor 52 is performed in the same manner as in the previous embodiment.

The circuit shown in FIG. 4 shows a modified array of the discharge circuit 620 of the embodiment shown in FIG.
0,102,104, transistor 1
An inverted signal of the output CK of the comparator 58 is applied as a control input to a control input terminal 106 formed at the base of the comparator 58. Transistor 99 constitutes a constant current source, and a constant bias voltage V _B1 is applied to its base. transistor 100,
Reference numeral 102 constitutes a current mirror circuit, and transistor 104 constitutes a switch circuit that is switched to a non-conducting state to discharge the capacitor 52 and a charged state to the capacitor 52 when the comparator 58 generates an inverted output. are doing.

With this configuration, the capacitor 52 can be discharged with a constant current, similar to the embodiment shown in FIG.

Further, in the circuit shown in FIG. 5, the charging circuit 600 and the discharging circuit 620 are connected to the transistors 108 and 11.
The inverted signal of the output CK of the comparator 58 is applied as a control input to a control input terminal 118 formed at the base of the transistor 116. Transistors 108 and 110 constitute a constant current source, and a constant bias input V _B2 is applied to the base thereof. Further, the transistors 112 and 114 constitute a current mirror circuit, and the emitter area of the transistor 114 is the same as that of the transistors 108, 110,
112 and 116, and if the constant current flowing through the transistor 110 is I, then a constant current 2I, which is twice as large as that of the transistor 112 and 116, flows through the transistor 114.

Therefore, when control input terminal 118 is maintained high, transistor 116 becomes conductive and the circuit shown in FIG. 5 functions as charging circuit 600. That is, when the transistor 116 becomes conductive, the transistor 114 becomes non-conductive, and a constant current I flows from the transistor 110 to the capacitor 52.
The capacitor 52 is charged.

Also, the terminal voltage of the capacitor 52 is the reference voltage.
When V _r is reached and the inverted output of comparator 58 occurs, control input terminal 118 goes low, transistor 116 becomes non-conductive and transistor 114 becomes conductive, so that the circuit shown in FIG. It functions as a circuit 620.

At this time, the transistor 114 has a constant current of 2
Since I flows, the discharge current from the capacitor 52 is absorbed into the constant current I from the transistor 110, and the capacitor 52 is discharged with the same constant current I as the constant current I flowing during charging.

According to such a configuration, charging and discharging can be performed with a simple circuit configuration, and the charging current and discharging current can be controlled with high precision.

〔Effect of the invention〕

As explained above, according to the present invention, since a part of the clock oscillator is used, the circuit configuration can be simplified, and the initial setting output can be generated before the clock oscillation occurs. There is no need to individually set the timing between the two, and highly reliable operation timing and initial setting timing can be achieved.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the initial setting circuit of the logic control device of the present invention, FIG. 2 is a timing chart showing its operation, and FIG. 3 is a diagram of the charging/discharging circuit in the embodiment shown in FIG. A circuit diagram showing another embodiment,
Fig. 4 is a circuit diagram showing another embodiment of the discharge circuit, Fig. 5 is a circuit diagram showing another embodiment of the charging/discharging circuit in the embodiment shown in Fig. 1, and Fig. 6 is a logic control device. FIG. 7 is an explanatory diagram showing the operation of the power-on circuit. 2... Main circuit section of logic control device, 24... Control circuit having a plurality of logic circuits, 26...
Clock oscillator, 54...Initial setting circuit, 78...
...A transistor that constitutes a hysteresis circuit.

Claims (1)

[Scope of Claims] 1. In a logic control device including a clock oscillator, a capacitor for setting a time constant installed in the clock oscillator, a reference voltage setting circuit that instantaneously generates a reference voltage in response to turning on the power, and a comparator that compares the reference voltage set by the reference voltage setting circuit with the rise of the charging voltage of the capacitor and generates an output when the charging voltage of the capacitor is higher than the reference voltage; An initial setting circuit for a logic control device, characterized in that it is used as an initial setting signal for a circuit. 2. The reference voltage setting circuit according to claim 1, wherein a hysteresis circuit is installed in the reference voltage setting circuit to reduce the reference voltage according to the output of the comparator and suppress output reversal of the comparator. Initial setting circuit for logic control unit.