KR0168080B1 - Latch circuit having the stable temperature character - Google Patents

Abstract

Provides a latch circuit used as an oscillation control circuit of a switched mode power supply (SMPS).

The latch circuit includes a bistable circuit 10 having first and second control terminals and first and second bias terminals and having two stable states; A first switching transistor (Q3) connected to the collector and the first bias terminal of the bistable circuit, the emitter being connected to the first control terminal of the bistable circuit, and selectively turning on the bistable circuit; A bias circuit (30) for biasing the base of the first switching transistor; A capacitor C1 coupled between the first control terminal and a first bias level of the bistable circuit; Gate means (11 and 12) for receiving a voltage and a clock signal across the capacitor and outputting a switching signal having a low level only when the voltage across the capacitor is low level and the clock signal is high level; An output circuit 20 which receives the switching signal, outputs an output signal having a phase opposite to the switching signal to the outside, and simultaneously supplies the output signal to the bias circuit. The bias circuit (30) includes a bias resistor (R6); A first transistor Q4 connected to the base of the first switching transistor and an emitter connected to the second bias level; The collector is connected to the base of the first transistor, the emitter is connected to the first bias level via the bias resistor, and includes a second transistor Q5 that receives an output signal to the base.

Description

Latch circuit with stable temperature characteristics

1 is a circuit diagram of a conventional latch circuit,

2 is a circuit diagram of the latch circuit of the present invention,

3 is an output waveform diagram of the circuits of FIGS. 1 and 2.

* Explanation of symbols for main parts of the drawings

10: complementary bistable circuit 20: output circuit

The present invention relates to a latch circuit, and more particularly, to a latch circuit used in a circuit for controlling the operation of a constant voltage circuit such as a switching mode power supply in a pulse width modulation method.

In a switched mode power supply, the input power voltage is converted into a periodic waveform, then controlled and rectified to output a supply voltage having a constant magnitude. In particular, in one example of such a switching mode power supply, a latch circuit that receives a clock signal having a constant frequency and outputs one pulse having a constant duty ratio for each clock period is used as the oscillator control circuit.

1 shows a conventional latch circuit. The latch circuit of FIG. 1 generates and outputs a pulse having a constant width while the clock signal is at a high level so that an oscillator (not shown) oscillates according to the pulse, and the transistors Q1 and Q2. Complementary bistable circuit 10, a first switching transistor (Q3), a capacitor (C1), an inverter 11 for inverting an external input signal, OR gate 12, and an output circuit 20) and resistors R1, R2, R3, and R4.

When the clock signal input to the inverter 11 is at the low level, the OR gate 12 outputs a high level and thus the transistor Q7 is turned on. At this time, the base voltage of the transistor Q4 becomes low level and the transistor Q4 is turned off. As a result, the emitter voltage and the output voltage Va of the transistor Q3 become low level. That is, when the clock signal is low, the low level output voltage Va is output. On the other hand, the transistors Q1 and Q2 are both turned on to maintain the latch state by the positive feedback.

Next, we will look after the clock signal transitions from low to high. At this time, since the inverter 11 outputs a low level, both input signals of the OR gate 12 go low, the OR gate 12 outputs a low level, and the transistor Q7 is turned off. . Accordingly, the base voltage of the transistor Q4 is at a high level, the transistor Q4 is turned on, and the output voltage Va is at a high level. Since the transistor Q3 is operated in the saturation region, the emitter-collector voltage (the emitter-base voltage of the transistor Q2) becomes small, so that the transistor Q2 is turned off and the transistors Q1 and Q2 are turned off. The latch is released. At this time, the current flowing through the transistor Q3 charges the capacitor C1.

When the capacitor C1 is charged and the voltage across the capacitor C1 becomes high level, the OR gate 12 outputs a high level, whereby the transistor Q7 is turned on and the transistor Q4 is turned off. Therefore, the output voltage Va is at a low level, and one clock is completely generated through the output signal.

However, when the emitter voltage of the transistor Q3 becomes larger than the base voltage Vref− (R ₅ I _B4 + V _BE4 + V _BE3 ) of the transistor Q3 due to the charging of the capacitor C1, the transistor Q3. Is turned off and transistor Q2 can be turned on, and if the voltage across resistor R3 is greater than 0.7 V, then the transistors Q1 and Q2 are also latched. The charge charged in the capacitor C1 is discharged through the transistor Q1.When the voltage across the capacitor C1 falls to a low level, the OR gate 12 outputs a low, the transistor Q7 is turned off and the transistor Q4 is turned on so that the high level output signal Va can be output again, and as shown in FIG. 3, two or more pulses can be generated for one clock signal.

In particular, the circuit of FIG. 1 has the characteristic that operation becomes more unstable as temperature changes. Let's look at the temperature characteristics of the circuit. The resistors R1, R2, R3, R4, and R5 connected to each active element to determine the bias state of the circuit exhibit positive characteristics with respect to temperature, and the switching-on voltage (V _BE ) of the base-emitter of each transistor. ) Shows negative characteristics with respect to temperature and usually has a temperature characteristic of about -2mV / ℃. Therefore, when the temperature increases, the transistors Q1 can be turned on even when the base potential of the transistor Q1, that is, the voltage across the resistor R3 is less than 0.7V, thereby causing the transistors Q1 and Q2 to latch more. Done. As a result, the output voltage Va changes to high, thereby increasing the number of pulses included in the output signal.

As described above, in the latch circuit of FIG. 1, there is a problem that a malfunction occurs when the surrounding environment of the apparatus is higher than room temperature.

It is therefore an object of the present invention to provide a latch circuit that performs stable operation even if the temperature changes.

In order to achieve the above object, the latch circuit of the present invention comprises: a complementary bistable circuit having first and second control terminals and first and second bias terminals and having two stable states; Connected to the first bias terminal of the collector and the complementary bistable circuit, the emitter is connected to the first control terminal of the complementary bistable circuit, and selectively turns on the complementary bistable circuit. A first switching transistor; A bias circuit for biasing the base of the first switching transistor; A capacitor having one terminal connected to the first control terminal of the complementary bistable circuit, and the other terminal connected to a first bias level; Accepts a voltage across the capacitor and a clock signal, outputs a switching signal having a low level only when the voltage across the capacitor is low and the clock signal is high, and inverts the clock signal to invert the clock signal Gate means for supplying a signal to the second control terminal of the complementary bistable circuit; An output circuit which accepts the switching signal and outputs an output signal having a phase opposite to the switching signal to the outside and is supplied to the bias circuit, the bias circuit comprising: a bias resistor; A first transistor having a collector connected to the base of the first switching transistor and an emitter connected to a second bias level; The collector is connected to the base of the first transistor, the emitter is connected to the first bias level through the bias resistor, characterized in that it comprises a second transistor for receiving the output signal to the base.

Next, the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram of a latch circuit according to the present invention. In FIG. 2, the same reference numerals are used for elements corresponding to those in FIG.

The latch circuit of FIG. 2 includes a complementary bistable circuit 10, an inverter 11, an OR gate 12, a first switching transistor Q3, an output circuit 20, and a bias circuit 30. ), Resistors R1, R2, R3, and R6, and capacitor C1.

In the complementary bistable circuit 10, the collector of transistor Q1 is supplied with reference voltage Vref through resistor R1, and the emitter of transistor Q1 is grounded. In addition, the collector of transistor Q1 is connected to the base of transistor Q2, and the base of transistor Q1 is connected to the collector of transistor Q2. The collector of transistor Q2 is grounded through resistor R3, and the emitter of transistor Q2 is connected to one terminal of resistor R2 and the collector of transistor Q3. The reference voltage Vref is applied to the other terminal of the resistor R2.

The complementary bistable circuit 10 has two stable states. That is, when Q1 is on, Q2 is on, and when Q1 is off, Q2 is off.

The collector of the first switching transistor Q3 is connected to the emitter of the transistor Q2, and the emitter is connected to the base of the transistor Q2 and one terminal of the capacitor C1. The other terminal of capacitor C1 is grounded.

The first switching transistor Q3 switches the complementary bistable circuit 10 according to the voltage applied to the base thereof. That is, since the collector-emitter voltage of the transistor Q3 is the same as the emitter-base voltage of the transistor Q2, the emitter of the transistor Q2 is turned on when the first switching transistor Q3 is turned on and is in the saturation region. The base-to-base voltage has a very small value (approximately 0.2V), so transistor Q2 is turned off. When the first switching transistor Q3 is not in the saturation region and the emitter-base voltage of the transistor Q2 has a value larger than 0.7V, the transistor Q2 is turned on. At this time, the transistor Q1 is also turned on so that the complementary bistable circuit 10 maintains a latched state. On the other hand, when the first switching transistor Q3 is turned on, the current flowing through the first switching transistor Q3 charges the capacitor C1.

The inverter 11 receives the clock signal, inverts it, and outputs the inverted clock signal. One input terminal of the OR gate 12 is connected to the emitter of the transistor Q3, and the other input terminal is connected to the output terminal of the inverter 11. The output terminal of the inverter 11 is also connected to the base of the transistor Q1.

The output circuit 20 includes a second switching transistor Q7, a transistor Q4, and a current limiting resistor R5. The base of the second switching transistor Q7 is connected to the output terminal of the OR gate 12, and the emitter is grounded. A power supply voltage Vcc is applied to the collector of the transistor Q4, and its base is connected to the collector of the second switching transistor Q7 and one terminal of the resistor R5. The other terminal of resistor R5 is connected to the reference voltage level Vref. The emitter potential of the transistor Q4 is output as the output voltage Va. When the second-switching transistor Q7 is in an off state, a high level is applied to the base of the transistor Q4 and the transistor Q4 is saturated, and the output voltage Va becomes a high level of Vref-Vbe. . On the other hand, when the second switching transistor Q7 is in the on state, a low level is applied to the base of the transistor Q4 and the transistor Q4 is turned off, so that the output voltage Va becomes a low level.

On the other hand, in the bias circuit 30, the collector of the transistor Q5 is connected to the base of the first switching transistor Q3. The reference voltage Vref is supplied to the emitter of the transistor Q5, and the base of the transistor Q5 is connected to the collector of the transistor Q6. The emitter of transistor Q6 is grounded through resistor R6, and the base of transistor Q5 is connected to the emitter of transistor Q4.

The operation of the latch circuit according to the present invention will be described below.

When the clock signal input to the inverter 11 is at the low level, the OR gate 12 outputs a high level and thus the transistor Q7 is turned on. At this time, the base voltage of the transistor Q4 goes low and the transistor Q4 is turned off. As a result, the output voltage Va becomes a low level. That is, when the clock signal is low, the low level output voltage Va is output.

On the other hand, since the inverter 11 outputs high at this time, the transistor Q1 is turned on. When transistor Q1 is turned on, the base potential of transistor Q2 is at a low level, and transistor Q2 is also turned on. Accordingly, the strong transistors Q1 and Q2 are both turned on to maintain the latch state by the positive feedback.

Next, we will look after the clock signal transitions from low to high. At this time, the inverter 11 outputs a low level. If the emitter potential of transistor Q3 is at low level, both input signals of OR gate 12 go low, so OR gate 12 outputs low level and transistor Q7 is turned off. Accordingly, the base voltage of the transistor Q4 becomes high level, the transistor Q4 is turned on, and the output voltage Va becomes high level.

When transistor Q4 is turned on, transistors Q6 and Q5 are turned on. At this time, since a high voltage of Vref-V _{CE, sat, Q4} is applied to the base of the first switching transistor Q3, the first switching transistor Q3 is also turned on to be in a saturation region. Since the first switching transistor Q3 becomes smaller the emitter-collector voltage (the emitter-base voltage of the transistor Q2), the transistor Q2 is turned off and the latches of the transistors Q1 and Q2 are released. At this time, the current flowing through the transistor Q3 charges the capacitor C1. When the voltage across the capacitor C1 exceeds a predetermined level due to the charging of the capacitor C1, the OR gate 12 outputs high to turn on the transistor Q7. As a result, the output voltage Va transitions to the low level.

As described above, the latch circuit of FIG. 2 generates and outputs a pulse having a constant width while the clock signal is at a high level so that the oscillator (not shown) oscillates according to the pulse.

On the other hand, in the circuit of FIG. 2, the capacitor C1 is charged so that the voltage across the capacitor C1, that is, the emitter potential of the first switching transistor _Q3 is greater than Vref-V _{CE, sat, Q4} -V _{BE, Q3} . In this case, the first switching transistor Q3 may be turned off and the transistor Q2 may be turned on. However, since the voltage across the capacitor is increased in comparison with the related art (a difference between V _BE and V _{CE, sat,} that is, increased by about 0.5V _, compared with the conventional case), such a turn-on phenomenon of the transistor Q2 does not appear very easily. Accordingly, the parasitic latching of the transistors Q1 and Q2 is less likely to occur, and the possibility of generating two or more pulses for a clock signal of one cycle becomes small. In particular, the circuit of FIG. 2 has a characteristic that the operation becomes more stable when the temperature changes.

Figure 3 shows the output waveforms of the conventional circuit and the circuit according to the present invention when the temperature is above room temperature and the spherical pulse is applied to the two-wall terminals. In the conventional art, several output pulses are generated for one cycle of clock pulses. In the circuit according to the present invention, it can be seen that only one pulse is displayed at a time in a high level section of a signal applied to an input terminal.

As described above, the present invention improves the temperature characteristics of a conventional latch circuit, and when used as a control circuit of a discontinuous mode oscillator such as a switched mode power supply (SMPS), a stable and reliable operation can be obtained.

Claims (4)

A complementary bistable circuit (10) having first and second control terminals and first and second bias terminals and having two stable states; Connected to the first bias terminal of the collector and the complementary bistable circuit, the emitter is connected to the first control terminal of the complementary bistable circuit, and selectively turns on the complementary bistable circuit. A first switching transistor Q3; A bias circuit (30) for biasing the base of the first switching transistor; A capacitor C1 having one terminal connected to the first control terminal of the complementary bistable circuit and the other terminal connected to a first bias level; Accepts a voltage across the capacitor and a clock signal, outputs a switching signal having a low level only when the voltage across the capacitor is low and the clock signal is high, and inverts the clock signal to invert the clock signal Gate means (11 and 12) for supplying to the second control terminal of the complementary bistable circuit; In the latch circuit having an output circuit (20) for receiving the switching signal and outputting an output signal having a phase opposite to the switching signal to the outside and to the bias circuit, the bias circuit (30) A bias resistor R6; A first transistor (Q4) having a collector connected to the base of the first switching transistor and an emitter connected to a second bias level; A collector connected to the base of the first transistor, an emitter connected to the first bias level through the bias resistor, and a second transistor Q5 receiving the output signal to the base; Latch circuit. The complementary bistable circuit of claim 1, wherein a collector is connected to the first control terminal, the second bias level is connected to the second control terminal through a predetermined first bias means, and a base is connected to the second control terminal. A third transistor having an emitter coupled to the first bias level; An emitter is connected to the first bias terminal, biased to the second bias level via a predetermined second bias means, a base is connected to the first control terminal, and a collector is connected to the second control terminal. And a fourth transistor to be used. 2. The apparatus of claim 1, wherein the gate means comprises: an inverter configured to receive and invert the clock signal to output an inverted clock signal; And an OR gate for accepting and ORing the output of the inverter and the voltage across the capacitor. 2. The apparatus of claim 1, wherein the output circuit comprises: a second switching transistor, the gate of which receives the switching signal and whose emitter is connected to the first bias level; A current limiting resistor connected to the second bias level and the collector of the second switching transistor; And a fifth transistor having a collector connected to a power supply voltage level, a base connected to a collector of the second switching transistor, and an emitter connected to the bias circuit.