JPH0282653A - Field-effect transistor and semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enable an ultra-high speed operation of theoretically maximum speed without depending upon the mobility of carriers in a semiconductor used by specifying the gate length in a field-effect transistor. CONSTITUTION:Gate length Lg in a field-effect transistor is selected as shown in formula I. Transconductance gm takes a maximum value by the saturated velocity of carriers, and the ultra-high speed operation of theoretically maximum speed is acquired without depending upon the mobility of carriers. In formula, q represents unit charge, mu a mobility of carriers, ns a concentration of a two-dimensional carrier gas constituting a channel, (d) a channel depth, epsilon a dielectric constant of a semiconductor and Vs a saturated velocity of carriers. In a semiconductor integrated circuit device, the transconductance gm of the field-effect transistor can be arranged at a theoretically maximum value determined by the saturated velocity of carriers by selecting the gate length Lg of the field- effect transistor as shown in formula II. Each field-effect transistor is formed to the same shape, thus allowing the increase of the degree of integration and density.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a field effect transistor and a semiconductor integrated circuit device, and in particular to a field effect transistor using two-dimensional electron gas or two-dimensional hole gas as a channel, and its field effect transistor. The present invention relates to a semiconductor integrated circuit device constituted by effect transistors.

[Summary of the invention]

The field effect transistor according to the present invention has a gate length of L9.
When , q is the unit charge and μ is the chiaria). This makes it possible to achieve the theoretically highest ultra-high speed operation, regardless of the mobility of carriers in the semiconductor used.

In the semiconductor integrated circuit device according to the present invention, a plurality of field effect transistors each having a different polarity and/or made of different types of semiconductor are formed on a single semiconductor substrate, and when the gate length of the field effect transistor is L9, . As a result, the operating speeds of field effect transistors configured with different polarities and/or different types of semiconductors can be made equal to the theoretically highest speed independent of carrier mobility, and each field effect transistor can have the same shape. be able to.

[Conventional technology]

The gate length of a MOSFET in currently mainstream silicon (Si) MOS LSI is about 1 μm.

When the gate length is on this order of magnitude, the operating speed of this MOSFET is controlled by the mobility of carriers in Si. However, the mobility of electrons in Si is lower than that of gallium arsenide (G
The mobility of electrons in aAs) is about 115, which is small. Therefore, the 51M03FET is made of GaAs ME S F
ET and AlGaAs/GaAs HE M T(l
light Electron Mobility Tr
It is inferior in high-speed performance compared to high-mobility transistors using GaAs such as MOS transistors. Also,
Even in ultra-highly integrated 51M03LSr, such as 16M bit class dynamic RAM, which is considered to become mainstream in the future, the gate length of the MOS FET is approximately 0.25μ.
It is about m. Even when the gate length is around this level, MOSF
The operating speed of ET is controlled by the mobility of carriers in Si, and therefore, in terms of high speed, it is still inferior to high mobility transistors using GaAs.

On the other hand, the mobility of holes in Si is a fraction of that of electrons.
The degree is small. In addition, compound semiconductors with a direct transition type band structure such as GaAs generally have a small effective mass of electrons and therefore have high mobility, so they are expected to be semiconductor materials for high-speed devices. In compound semiconductors with n-type FET (n-channel FET) and p-type FET (p-channel FE) that uses holes.
T) to configure a complementary FET with low power consumption, if the n-type FET and p-type FET are of the same shape, the transconductance glI of the p-type FET is one order of magnitude higher than that of the n-type FET. It also gets worse. In order to compensate for this drawback, the gate width (channel width) of the p-type FET must be n
It becomes necessary to take measures such as making the gate width wider than the gate width of the type FET.

Problems to be solved by Invention C] As mentioned above, not only in the past but also in the coming years, 51M
The operating speed of the 03FET is controlled by the mobility of carriers in Si, and therefore it is considered that no revolutionary improvement in operating speed can be expected.

Furthermore, when configuring a complementary FET as described above, making the gate width of the p-type FET wider than the gate width of the n-type FET is disadvantageous in terms of integration density when attempting to achieve high integration. Not only that, but it is also inconvenient when designing LSI.Also, wiring resistance and stray capacitance are
ET, these are sources of extrinsic delay.

Therefore, an object of the present invention is to provide a field effect transistor that can realize ultra-high speed operation at the theoretically highest speed, regardless of carrier mobility.

Another object of the present invention is to make it possible to align the operating speeds of field effect transistors configured with different polarities and/or different types of semiconductors to the theoretically highest speed independent of carrier mobility, and furthermore, each field effect transistor An object of the present invention is to provide a semiconductor integrated circuit device that can have the same shape.

[Means to solve the problem]

Now, consider a SiMOSFET as shown in FIG. In FIG. 3, reference numeral 101 indicates a p-type Si substrate, and reference numeral 10
2 is a gate insulating film such as a SiO2 film, and reference numeral 10
3 is a gate electrode, 104 is a two-dimensional electron gas constituting a channel, 105 is a source, and 106 is a drain.

The saturated drain current 14s of the 51M03FET shown in FIG. 3 is expressed by the following equation, assuming that the source series resistance R8=0.

I o=βv, t”(+, sL −1
) where β=ε'u W9/d L9.

However, ε is the dielectric constant of the semiconductor (St in this case), μ is the mobility of carriers (electrons in this case), W9 is the gate width, and d
is the channel depth (=thickness of gate insulating film 102+thickness of two-dimensional electron gas 104). In addition, vfiL is the electric field F at which the carrier drift speed reaches the saturation speed ■5,
and gate length g, it is expressed as V, , -F,L. This electric field F8 is given by F,=V, with saturation velocity ■ and mobility μ.

/μ. Furthermore, 'J, -V, V
otr=qnsd/ε. However, ■9 is the gate voltage, ■. , f is the threshold voltage, q is the unit charge (absolute value of electron charge), and ns is the concentration (surface concentration) of the two-dimensional electron gas 104.

Transconductance g+ of the above 51M03FET
a can be obtained by partially differentiating equation (1) with respect to (■9). That is, σ ■9 - β ■9 (t + v9 'z /V, t" ) - ""dL.

It is a general one that can also be applied to FETs such as εT. Note that the same equation as this equation (2) is TEEE
Transactions on Electron
Devices vol, ED-33, no, 5.
pp, 625-632. It is also guided in MAY 1986.

gIll of a conventional FET with a large gate length is (2)
It can be considered that it is equivalent to changing L9 → ω in the equation, and in this case, the second term in parentheses in equation (2) disappears, and here, in the last equal sign, F, = V, / The relationship of μ was used.

In the end, the transconductance g7 can be expressed as...------(2). This formula (2) is 51M03FE
Not only T (for example, HEM using GaAs =...
−・−・−(3) As is clear from equation (3), in the conventional FET, assuming that W is constant, μ and L.

,n, determines g. Therefore, μ of Si is GaA
The disadvantage of being smaller than s etc. is reflected in gl.

Next, in equation (2), if →0, then ()
The first term in disappears, quWq n, eV, L.

The result is L9 9 μn, d. As is clear from equation (4), gm is d, ■5
Determined only by Therefore, in this case, no matter how small μ is, this drawback is not reflected in gs. In addition, g, 5
It is g1.

(4) In 2, d can be reduced to, for example, several tens of people or less. Furthermore, 5 is almost the same between Si and GaAs, and is actually larger in Si than in GaAs (see FIG. 7). This makes it easier than the HEMT mentioned above. It can be seen that it is possible to realize a 51M03FET with high resistance. The conditions for this are (2)
The second term in parentheses of the equation is larger than the first term.

In other words, the condition is that . (5) Transforming the second is a condition.

Next, we will specifically consider the value of which satisfies equation (6).

Figure 4A to 4th diagram are transconductance g,%
The result of calculating the relationship between and the gate length L9 is the mobility μ
is shown as a parameter. The calculation is d=1
The experiment was carried out for the case of 0.30 people and n5=101!1013 cm-t. For example, typical conditions as shown in Figure 4C, d = 30 people, n = + l Q 12
Considering c, -2, μ=500c+fi/Vs, gn
is determined by ■1, and it can be seen that the range of is Lg≦500 people. Therefore, by setting Lg≦500 people, the theoretically highest gl can be obtained, which leads to H
51M03FE capable of faster operation than EMT etc.
T can be realized. As can be seen from FIGS. 4A to 4, the value of L9 at which g, glue, and dependence disappear increases as nl increases and as μ increases.

Next, FIGS. 5A and 5B show F using GaAs.
Regarding the case where a Dirac-delta doped layer (a monoatomic layer impurity doped layer with two-dimensional expansion, hereinafter referred to as δ doped layer) is formed at a depth of 100 nm from the surface of the GaAs layer in ET. Using equation (2), g
The results of calculating the relationship between l and L9 are shown. Here, FIG. 5A shows a case where the carriers generated from the δ-doped layer are electrons, and FIG. 5B shows a case where the carriers generated from the δ-doped layer are genuine cards. Also, the concentration n of two-dimensional electron gas or two-dimensional hole gas formed in the δ-doped layer
8, 1013 cm-'' (peak concentration (volume concentration) 1019c13) was used as a typical value, and the depth d of the channel consisting of two-dimensional electron gas or two-dimensional hole gas was 100 people. Furthermore, from Figure 6,
The electron mobility μ at this time. and the hole mobility μ, μ, = 1000cJ/VS, μp = 100
ci/V s and ivy. The value obtained from FIG. 7 was used as the saturation speed V of the rear and -'i-+ rear.

In addition, FIGS. 6 and 7 show S, M, Sze, Ph
ics of Sem1conductor De
Vices, New York: Wiley, 1
This is an excerpt from 981.

Figure 7 does not show data on the saturation velocity of holes in GaAs (5), but when comparing the effective mass of holes in GaAs l Si, there is almost no difference, and the shape of the valence band is similar to that in Si. Since GaAs is almost the same,
The V of holes in GaAs is considered to be approximately equal to the V of holes in Si. Therefore, if we look at ■, we can assume that electrons and holes are unchanged. From this, in the calculations in Figures 5A and 5B, V s =1 x 10'cm/s
I took it.

As seen from Figures 5A and 5B, L1=IX
lO' In humans, gl when using holes is small, about 1/10 of gl when using electrons, but L, < 1000
In humans, g has almost the same value whether electrons or holes are used.

In Figures 5A and 5B, when L<1000 people, the dependence disappears because g6 is (2) (
), that is, g□ is expressed by equation (4).

In this way, the limit frequency f of the FET when gl is expressed by equation (4) is the capacitance between the gate electrode and the channel, C
Let g be the minimum value of εW, L, /d hole mobility μ. That is,
μ*=min(μ7.μp).

The above discussion has been about FETs using GaAs, but similar arguments can also be made about, for example, St.

The present invention has been devised based on the above considerations.

That is, the field effect transistor according to the present invention is expressed as follows, where Lg is the gate length. From equation (7), since ■8 is almost the same for electrons and holes, it can be seen that both FETs using electrons and FETs using holes operate at the theoretically highest speed determined by ■3. . The condition for eliminating the L9 dependence of g described above is expressed by the following equation, which is similar to equation (6).

Here, μ* is the electron mobility μ7 and.

Further, in the semiconductor integrated circuit device according to the present invention, when a plurality of field effect transistors each having a different polarity and/or made of different types of semiconductor are formed on a single semiconductor substrate, and the gate length of the field effect transistor is It is.

Here, μ* indicates the type of different semiconductor, i=1.2, -・
・If expressed as −1N, and the mobility of electrons in each semiconductor and the mobility of the genuine plate as μ7′ and μp′, then g*=
win (μll', g, ',------, p.

μD' + '--------・, μfi'+ μ
N).

[Effect]

In the field effect transistor according to the present invention configured as described above, the gate length is selected as shown in equation (9), so the transconductance g1 is the highest value determined by the carrier saturation speed, and the carrier does not depend on the mobility of Therefore, it is possible to achieve the theoretically highest ultra-high speed operation regardless of the carrier mobility in the semiconductor used.

Furthermore, in the semiconductor integrated circuit device according to the present invention configured as described above, since the gate length of the field effect transistor is selected as shown in equation (10), the device is configured with different polarities and/or different types of semiconductors. It is possible to adjust the transconductance g1 of the field effect transistor to the theoretical maximum value determined by the carrier saturation speed. As a result, the operating speeds of the field effect transistors can be made equal to the theoretical maximum speed independent of carrier mobility. Further, each field effect transistor can have the same shape. Therefore, higher integration density can be achieved by this amount.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

Figure 1A and Figure 1B are 51 according to Example I of the present invention.
M03FET is shown.

As shown in FIGS. 1A and 1B, in the 51M03FET according to this embodiment (2), an insulating film 2 such as a discolored Si0g film with a film thickness of about 700 mm is formed on a P-type Si substrate 1, for example. It is formed.

This insulating film 2 has an opening 2a formed therein. Reference numeral 3 indicates a gate insulating film such as a SiO□ film having a thickness of about 30 mm. Reference numeral 4 indicates a gate electrode made of metal such as tungsten (W). The width of this gate electrode 4, that is, the gate length L9, is selected to a value that satisfies equation (9). Specifically, for example, =500 people. Further, in the Si base +&1 in the opening 2a, for example, an n-type source region 5 and drain region 6 are formed in self-alignment with the gate electrode 4. Pad electrodes 7.8 are formed on these source regions 5 and drain regions 6, respectively. Further, a pad electrode 9 is also formed at one end of the gate electrode 4.

Next, 51M0 according to the embodiment
An example of a method for manufacturing a 3FET will be described.

As shown in FIG. 2A, first, an insulating film 2 is formed on the entire surface of a p-type Si substrate 1 by, for example, a thermal oxidation method or a CVD method.

Next, as shown in FIG. 2B, a predetermined portion of this insulating film 2 is removed by etching to form an opening 2a.

Next, as shown in FIG. 2C, an insulating film 3 such as a SiO□ film is formed on the entire surface by, for example, a CVD method, and then a film such as W, for example, is formed on this insulating film 3 by, for example, a sputtering method or a vapor deposition method. A metal film 10 is formed. Thereafter, a raw material gas such as alkylnaphthalene is introduced into a high vacuum evacuated sample chamber of an electron beam irradiation device (not shown), and the beam diameter is set on the metal film 10 in the raw material gas atmosphere in this sample chamber. A narrowly focused electron beam 11 is irradiated in a predetermined pattern. The acceleration voltage of this electron beam 11 is, for example, about 6 kV, and the beam current is, for example, 20 μA.
That's about it. Further, the pressure of the raw material gas atmosphere is, for example, 10-S to 10-8 Torr, and typically 10-S to 10-8 Torr.
7 Torr.The raw material gas is decomposed by the irradiation of the electron beam 11, and a hydrocarbon-based substance is generated on the metal film 10, thereby forming an ultra-fine resist made of this hydrocarbon-based substance. 12 is formed. This resist 12 has excellent dry etching resistance.

Next, using this resist 12 as a mask, the metal film 10 is
Then, the insulating film 3 is anisotropically etched in the direction perpendicular to the substrate surface by reactive ion etching (RIE) using, for example, a CFa-based etching gas, and as shown in the second diagram, equation (9) is obtained. A gate electrode 4 having an extremely fine width and a satisfactory gate length is formed. After this, resist 1
2 is removed by etching.

Next, after forming an n-type impurity film such as phosphorus (P) on the entire surface by, for example, plasma CVD method,
The entire surface is irradiated with a pulsed laser beam (wavelength 308 nm) from an eCl excimer laser. The surface layer of the semiconductor substrate 1 is instantaneously heated to a high temperature by the irradiation with this pulsed laser beam, and as a result, this n-type impurity is deposited in the semiconductor substrate 1 which is in direct contact with the above-mentioned n-type impurity film. It is extremely shallow and highly doped. As a result, as shown in FIG. 2, a source region 5 and a drain region 6 having a very shallow depth of, for example, 100 mm and having a high impurity concentration are formed in self-alignment with the gate electrode 4. Note that this impurity doping method is
L I M P I D (Laser Induce
dMelting of Predeposited
This is called the Impurity Doping method. Further, these source region 5 and drain region 6 can also be formed by a method other than the above-mentioned LIMPID method, for example, by a low energy ion implantation method.

After this, as shown in FIG. 1A and FIG. 1B, pad electrodes 7.8.9 are formed to form the desired StMO3FET.
complete.

According to this embodiment (2), the gate length L9 is (
9) Since it is selected to satisfy (2), it is possible to obtain the theoretically highest transconductance (g) determined by the saturation velocity (2) of carriers in Si. As a result, even though Si is used, which has a lower electron mobility than GaAs, it is possible to achieve ultra-high-speed operation comparable to IT7, and 51M03FE with higher performance than HEMT.
T can be realized.

Figures 8A and 8B show a complementary MO3FET according to Example H of the present invention.

As shown in FIGS. 8A and 8B, in the complementary MO3FET according to Example H, for example, p-type Si
On the substrate 1 is an n-channel MO3F having the same structure as in Example I.
ETQ is formed.

Further, an n-well 13 is formed in the Si substrate 1. In this n-well 13 at the opening 2b formed in the insulating film 2, a gate electrode 14 made of a metal such as W, a source region 15 formed in self-alignment with the gate electrode 14, and a drain region 16
A p-channel M OS FET Q z is formed. Reference numerals 17, 18, and 19 indicate pad electrodes. These n-channel MOS FET Q
+ and p-channel MO3FETQ, the complementary M
O3FET is configured. Figure 9 shows this complementary MOS
The equivalent circuit of FET is shown. In addition, in FIG. 9, V
DD is the power supply voltage, V in is the gate input voltage, V ou
t is the output voltage.

In this Example H, an n-channel MO3FETQ,
gate length L on and p-channel MO3FETQ2
The gate length L 91P of both is selected to be the same value that satisfies equation (10). However, μ* in equation (10)
is p*-rsin Cun", gp") -
Use usi. Gate length L that satisfies formula (10) 9
1'l, L-spO value, specifically, for example, about 500 people have discoloration. Also, the gate width Wgi of the n-channel MO3FETQ+ and the gate width W of the p-channel MOSFETQ2. are also chosen to have the same value.

Next, an example of a method for manufacturing the complementary MOSFET according to Example H configured as described above will be described.

As shown in FIGS. 8A and 8B, first, the Si substrate 1
After forming the n-well 13 by, for example, ion implantation,
An insulating film 2 is formed on a Si substrate l.

Next, openings 2a and 2b are formed in this insulating film 2.

Next, after forming a gate insulating film 3 on the entire surface, a metal film such as W, for example, is formed on this gate insulating film 3. Next, in the same manner as in Example I, these metal films and gate insulating film 3 are sequentially patterned into a predetermined shape to form a gate electrode 4.14 having an extremely fine width. Next, n-well 1
For example, with the surface of the portion 3 covered with a mask, Example I
For example, an n-type source region 5 and drain region 6 are formed in self-alignment with the gate electrode 4 by the LIMPID method described above. Next, the gate electrode 1 is formed by the LIMPID method using a p-type impurity such as boron (B), for example.
For example, a P' type source region 15 is formed in a self-aligned manner with respect to 4.
and a drain region 16. Thereafter, pad electrodes 7,8,9,17,18,19 are formed to complete the intended complementary MO3FET.

According to this embodiment (■), the gate length L an of the n-channel MO3FETQ and the gate length L gp of the P-channel MO3FET Q2 are both selected to satisfy equation (10), so that the gate length L an of the n-channel MO3FETQ
, and p-channel MOS FETQ2 both have the theoretically highest transconductance g, determined by the saturation speed v5. Therefore, these n-channel MO3
Both FETQ and p-channel MO3FETQZ operate at extremely high speeds at their theoretical maximum speeds. This makes it possible to realize a complementary MO3FET capable of extremely high-speed operation. In addition, as already mentioned, conventionally, in order to increase the speed of complementary MO3FET, p-channel M
Since it is necessary to increase the gate width of the OS FET, the shape of the p-channel MO3FET is different from that of the n-channel MOS.
Although it had to be considerably larger than the FET, according to this embodiment, the p-channel MOS FET
T Q z gate width n channel MO3FETQI
can be made the same as the gate width. That is, p-channel MO3FETQ2 is replaced with n-channel MO3FETQ,
It can be made into the same shape. This makes it possible to improve the integration density of complementary MO3FETs.

Disaster Management±1 FIG. 10 shows an embodiment (2) of the present invention. This example ■ is
Complementary FET composed of FETs using GaAs
This is an example in which the present invention is applied to.

As shown in FIG. 10, in this embodiment
．． 22 are formed, and n-type AIX Ga+-x As (0< x
<1) Layer 23 and n-type A1. A Ga+-x As layer 24 is formed. 25.26 are Schottky gate electrodes, 27.28 are source electrodes, and 29.26 are Schottky gate electrodes.
30 indicates a drain electrode. These GaAs layers 21,
The n-type Ga, -XAs layer 23, the Schottky gate electrode 25, the source electrode 27, and the drain electrode 29 constitute an n-type FET (HEMT) using electrons. This n-type FET has 1XGa, -X to the n-type
Electrons supplied from the As layer 23 cause this n-type A1.
A two-dimensional electron gas 31 formed in the GaAs layer 21 near the interface with the Ga1-XAs layer 23 is used as a channel. On the other hand, the GaAs layer 22 is P-type AFXGa.

8, the S layer 24, Schottky gate electrode 26, source electrode 28, and drain electrode 30 provide p
A type FET is constructed. This p-type FET is p
A two-dimensional hole gas 3 formed in the GaAs layer 22 near the interface with the p-type Al, 1Gal-x As layer 24 by holes supplied from the As layer 24.
2 is used as the channel. The above n-type FET and this p
type FET, a complementary type FET similar to that shown in FIG.
is configured.

In this embodiment (■), the gate length of the n-type FET is
, and the gate length of the p-type FET are both (1
0) are selected to be the same value that satisfies the formula.

However, μ* in equation (10) is expressed as B* = min (
gn””tt, G a A *) −u,
G II A I is used.

Next, an example of a method for manufacturing the complementary FET according to the embodiment (2) constructed as described above will be described.

As shown in FIG. 1O, first, a semi-insulating GaAs substrate 20 is
undoped GaAs layer 21 and n-type AIX on the entire surface of
The Ga, -XAs layer 23 is formed by, for example, molecular beam epitaxy (
The layers are sequentially formed by MBE) or metal organic chemical vapor deposition (MOCVD). Next, these n-type AIX Ga+
After etching and removing predetermined portions of the -x8S layer 23 and the GaAs layer 21, the n-type A1 remaining by etching is removed.
．． The surface of the tGa, □As layer 23 is covered with a mask, and in this state, the undoped GaAs layer 22 and the n-type A1. Ga, -8As layer 2
form 4. Next, these n-type A1. Ga,
Predetermined portions of the As layer 24 and the GaAs layer 22 are removed by etching to form the shape shown in FIG. Thereafter, Schottky gate electrodes 25, 26, source electrodes 27, 28, and drain electrodes 29, 30 are formed to complete the intended complementary FET.

In this embodiment (2), the gate length of the n-type FET is g.

and the gate length L 99 of the p-type FET is (10
), these n-type F
Both the ET and the p-type FET have a theoretically highest transconductance gffi determined by the saturation velocity of electrons or holes in GaAs.

Therefore, both of these n-type FETs and p-type FETs operate at extremely high speeds at their theoretical maximum speeds.

As a result, a complementary FET capable of ultra-high-speed operation can be realized as in the embodiment (2). Furthermore, as in the embodiment (2), since the p-type FET can have the same shape as the n-type FET, the integration density of the complementary FETs can be improved accordingly.

In this Example 2, the depth d of the channel formed by the two-dimensional electron gas or the two-dimensional hole gas is:
The gate length L is selected to be about 1/3 or less of the gate length Lgn, L, . This means that the channel depth d is the gate length L 91'
This is because if it is about 1/3 or more of l, Lllll, the channel will not close when the FET should be turned off.

Actual drawing ItsuV FIG. 11 shows Embodiment 2 of the present invention. This example ■ is
This is an example in which the present invention is applied to an optoelectronic integrated circuit (OEIC) in which Si-based elements and GaAs-based elements are integrated on a single St substrate.

As shown in FIG. 11, in the 0EIC according to this embodiment (2), a part of the Si substrate 1 is made of GaAs/AlGaAs.
A layer 33 is formed. Then, on the Si substrate 1, there are 5
A 1M03FET circuit 34 is formed and GaAs/AlG
The aAs layer 33 includes a GaAsFET circuit 35 and a laser diode array or photodetector array 3.
6 is formed. Reference numeral 37 indicates wiring.

FIG. 12 shows an example of the circuit configuration of a laser diode array. In FIG. 12, symbol LD is a laser diode, symbol R2 is a resistor, and symbol Q:l is a normally-off Ga
AsFET is shown. The laser diode LD is, for example, a GaAs/AlGaAs double heterojunction laser. In addition, the gate of GaAsFETQ,
51M03FET forming the 51M03FET circuit 34
Gate voltage output from■. is applied. GaAs
F E T Gate voltage to the gate of Qz■. FIG. 13 shows the relationship between the input and the laser light output from the laser diode LD. Next, FIG. 14 shows an example of the circuit configuration of the photodetector array. In Figure 14,
Symbol R2 is a resistor, and symbol Q4 is normally-off GaAs.
FET, the reference numeral indicates a photodiode. The output V out of the inverter consisting of these resistors R2 and GaAs FET Q4 is amplified by a 51M03 FET circuit 34. Symbol R3 is a resistor, symbol Q is 51M03F
51M03FET of ET circuit 34 is shown. Laser light power L' to photodiode D and GaAs FET
Gate voltage to the gate of Q4■. ■ Input and output. u
The relationship with L is shown in FIG.

In this embodiment (2), the gate length of the 51M03FET constituting the 51M03FET circuit 34 and the GaAsF
The gate length of the GaAsFET constituting the ET circuit 35 is:
The value is selected to satisfy equation (10). in this case,(
10) As μ* in the equation, Si MOSFET and G
Assuming that there are n-type and p-type aAsFETs, μ*=tsin(μ781.μ93L, μ
GmAl, μGaAl)-μ.

GmAl is used.

According to this example (■), the 51M03FET is also GaAsF
ET also has the theoretically highest transconductance g1 determined by the saturation speed V, and therefore these 51M03F
ETs and GaAsFETs can theoretically be operated at very high speeds.

Moreover, these 51M03FET and GaAsFE
Since all Ts can have the same shape, an 0EIC with high integration density can be realized.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications can be made based on the technical idea of the present invention.

For example, the present invention can also be applied to FETs using semiconductors other than St and GaAs (eg, germanium (Ge)'). Further, the present invention also provides, for example, Ga
Schottky gate type FET using As.

That is, it can also be applied to GaAs MESFETs. In this case, as already mentioned, the channel depth d needs to be about 1/3 or less of the gate length. For example, if the gate length is about 1000 7, the channel depth d needs to be about 300 degrees of color change. Gate length is 50
For cases below 0 degrees of color change, the channel depth d should be less than about 150 degrees of color change. In such a case,
It is necessary to use a δ-doped layer. FIG. 16 shows an example. In this FIG. 16, a semi-insulating GaAs layer 20
δ-doped layers 38 and 39 are formed at depths d, , and d from the surface of the undoped GaAs layer 21 formed thereon. Specifically, d, d2 are, for example, 10 people and 30 people, respectively. In this case, the δ-doped layer 38 is
This is for supplying electrons to the surface of the GaAs layer 21. On the other hand, a two-dimensional electron gas formed in the δ-doped layer 39 forms a channel. In FIG. 16, reference numeral 40 indicates a Schottky gate electrode, and reference numeral 41.
42 indicate a source electrode and a drain electrode, respectively.

〔Effect of the invention〕

As described above, according to the field effect transistor according to the present invention, it is possible to realize ultrahigh-speed operation at the theoretically highest speed, regardless of the mobility of carriers in the semiconductor used.

Further, according to the semiconductor integrated circuit device of the present invention, the operating speeds of field effect transistors configured with different polarities and/or different types of semiconductors can be made to be the theoretically highest speed independent of carrier mobility. Moreover, each field effect transistor can have the same shape.

[Brief explanation of the drawing]

FIG. 1A is a plan view showing a 51M03FET according to Example 1 of the present invention, FIG. 1B is a sectional view taken along the XX line of FIG. 1A, and FIGS. 2A to 2E are the views shown in FIG. A and FIG. 1B are cross-sectional views showing an example of the manufacturing method of the 51M03FET in the order of steps, FIG. 3 is a perspective view showing the model used to calculate transconductance, and FIGS. 4A to 4 are diagrams showing various conditions. FIG. 5A is a graph showing the relationship between the transconductance and gate length of a GaAs-based FET that uses electrons generated from the δ-doped layer. Figure 5B shows GaA using holes generated from the δ-doped layer.
A graph showing the relationship between transconductance and gate length of an s-based FET. Figure 6 is a graph showing the relationship between carrier mobility in GaAs and impurity concentration. Figure 7 is a graph showing the relationship between carrier drift velocity and electric field. FIG. 8A is a plan view showing a complementary FET according to Example 2 of the present invention, FIG. 8B is a cross-sectional view taken along the Y-Y line of FIG. 8A, and FIG. A circuit diagram showing an equivalent circuit of the complementary FET shown in FIGS. 8A and 8B, FIG. 10 is a sectional view showing a complementary FET according to the embodiment (2) of the present invention, and FIG. 11 is a circuit diagram showing the complementary FET according to the embodiment (2) of the present invention. Fig. 12 is a circuit diagram showing an example of the configuration of the laser diode circuit of the 0EIC shown in Fig. 11, and Fig. 13 shows the gate input and laser light output in the laser diode circuit shown in Fig. 12. 14 is a circuit diagram showing an example of the configuration of the photodetector system circuit of the 0EIC shown in FIG.
FIG. 5 is a waveform diagram showing the relationship between laser beam power, gate power, and output in the photodetector circuit shown in FIG. 14, and FIG. 16 is a sectional view for explaining the present invention in detail. Explanation of main symbols in the drawings 1: Si substrate, 4.14: Gate electrode, 25.
26: Schottky gate electrode, 5.15: source region, 6.16: drain region. 11'j 551M05FET Figure 1A a

Claims (1)

[Claims] 1. When the gate length is L_9, L_9<qμn_sd/εV_s where q is unit charge, μ is carrier mobility, n_s is the concentration of two-dimensional carrier gas constituting the channel, and d is A field effect transistor characterized in that the channel depth, ε is the dielectric constant of the semiconductor, and V_s is the saturation velocity of carriers. 2. A plurality of field effect transistors made of different polarities and/or different types of semiconductors are formed on a single semiconductor substrate, and the gate length of the field effect transistor is set to L_9.
When, L_9<qμ*n_sd/εV_s where q is the unit charge, μ* is the minimum value of carrier mobility, n_s is the concentration of the two-dimensional carrier gas constituting the channel, d is the channel depth, A semiconductor integrated circuit device characterized in that ε is a dielectric constant of a semiconductor, and V_s is a saturation velocity of carriers.