JP2676819B2 - Field effect transistor and semiconductor integrated circuit device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor and a semiconductor integrated circuit device, and more particularly to a field effect transistor using a two-dimensional electron gas or a two-dimensional hole gas as a channel and this electric field. The present invention relates to a semiconductor integrated circuit device including an effect transistor.

[Summary of the Invention]

The field effect transistor according to the present invention has a gate length of L _g
When It is. This makes it possible to realize theoretically the highest speed ultra-high speed operation regardless of the mobility of carriers in the semiconductor used.

In the semiconductor integrated circuit device according to the present invention, a plurality of field effect transistors composed of different polarities and / or different semiconductors are formed on a single semiconductor substrate, and when the gate length of the field effect transistor is L _g , It is. As a result, the operating speed of the field effect transistor composed of different polarities and / or different kinds of semiconductors can be adjusted to the theoretical maximum speed independent of carrier mobility, and each field effect transistor has the same shape. be able to.

[Conventional technology]

The gate length of the MOSFET in the currently mainstream silicon (Si) MOS LSI is about 1 μm. At this gate length, the operating speed of this MOSFET is dominated by the mobility of carriers in Si. However, the mobility of electrons in Si is about 1/5 of the mobility of electrons in gallium arsenide (GaAs). For this reason, Si MOSFETs are GaAs MESFETs and AlGaAs
/ GaAs Compared to high mobility transistors using GaAs such as HEMT (High Electron Mobility Transistor), it is inferior in terms of high speed. Moreover, even in ultra-highly integrated Si MOS LSIs such as 16M-bit class dynamic RAM, which is expected to become the mainstream in the future, the gate length of MOSFET is about 0.25μ.
m. Even with such a gate length, the operating speed of the MOSFET is dominated by the mobility of carriers in Si,
Therefore, in terms of high speed, it is still inferior to the high mobility transistor using GaAs.

On the other hand, the mobility of holes in Si is a fraction of the mobility of electrons.
About small. In addition, a compound semiconductor having a direct transition band structure such as GaAs generally has a small effective mass of electrons,
Therefore, since it has high mobility, it is expected as a semiconductor material for high-speed devices, but in the compound semiconductor having this direct transition band structure, the hole mobility is considerably smaller than the electron mobility. As described above, since the mobility of holes in both si and GaAs is smaller than the mobility of electrons, an n-type FET (n-channel FET) that uses electrons and a p-type FET (p-channel FET) that uses holes are used. When a low power consumption complementary FET is constructed by combining and,
If it has the same shape as T, the transconductance g _m of the p-type FET is about one digit worse than that of the n-type FET. In order to compensate for this drawback, it is necessary to take measures such as making the gate width (channel width) of the p-type FET wider than the gate width of the n-type FET.

[Problems to be solved by the invention]

As described above, Si M
The operating speed of OSFET is dominated by the mobility of carriers in Si, so it is considered that innovative improvement in operating speed cannot be expected.

In addition, when the complementary FET is formed as described above, the p-type F
Making the gate width of the ET wider than the gate width of the n-type FET is not only disadvantageous in terms of integration density when high integration is intended, but also inconvenient for LSI design. Further, since the wiring resistance and the stray capacitance are different between the n-type FET and the p-type FET, these cause an external delay.

Therefore, the object of the present invention is not to depend on the mobility of carriers,
An object of the present invention is to provide a field effect transistor that can realize an ultra-high speed operation that is theoretically the highest speed.

Another object of the present invention is to adjust the operating speed of a field effect transistor composed of different polarities and / or different kinds of semiconductors to a theoretical maximum speed that does not depend on carrier mobility, and yet each field effect transistor. It is an object of the present invention to provide a semiconductor integrated circuit device that can have the same shape.

[Means for solving the problem]

Now consider a Si MOFSET as shown in FIG. In FIG. 3, reference numeral 101 is a p-type Si substrate, and reference numeral 102 is, for example, SiO _2.
A gate insulating film such as a film, 103 is a gate electrode, 1
Reference numeral 04 indicates a two-dimensional electron gas that constitutes a channel, reference numeral 105 indicates a sword, and reference numeral 106 indicates a drain.

Saturation drain current I of Si MOSFET shown in Fig. 3
Assuming that the source series resistance R _s = 0, _ds is expressed by the following equation.

Here, β = εμW _g / dL _g . Where ε is the dielectric constant of a semiconductor (here Si), μ is the mobility of carriers (here electrons), W _g is the gate width, d is the channel depth (= thickness of gate insulating film 102 + two-dimensional electron gas). Thickness of 104). In addition, V _sl is the carrier drift velocity is the saturation velocity V
_{With the} electric field F _s reaching _s and the gate length L _g , V _sl = F _s L _g
It is expressed as This electric field F _s has a saturation velocity V _s and a mobility μ
Is expressed as F _s = V _s / μ. Furthermore, V _g ′ = V _g −V
_off = qn ₄ d / ε. Where V _g is the gate voltage, V _off is the threshold voltage, q is the unit charge (absolute value of electronic charge), n _s
Is the concentration (area concentration) of the two-dimensional electron gas 104.

The transconductance g _m of the above Si MOSFET is
It can be obtained by partially differentiating the equation (1) with respect to V _g . That is, Here, in the last equal sign, the relationship of F _s = V _s / μ was used.

After all, the transconductance g _m is It can be expressed as. The expression (2) is a general expression that can be applied not only to the Si MOSFET but also to an FET such as HEMT using GaAs. In addition, the same formula as this formula (2) is the IEEE Transactions on Electro
n Devices, vol.ED-33, no.5, pp.625-632, MAY 1986.

It can be considered that g _{m of the} conventional FET having a large gate length L _g is equal to that of L _g → ∞ in the equation (2). In this case, the second term in {} of the equation (2) is Disappear Becomes As is clear from the equation (3), in the conventional FET, when W _g is considered to be constant, g _m is determined by β, L _g , and n _s . Therefore, the defect that μ of Si is smaller than that of GaAs is reflected in g _m .

Next, when L _g → 0 in the equation (2),
The first term in {} disappears, Becomes As is clear from the equation (4), g _m is determined only by d and V _s . Therefore, in this case, even if μ is much smaller, this drawback is still not reflected in g _m, a ^{_{g m ≦ ▲ g 0 m ▼}} .

In the equation (4), d can be reduced to, for example, about several tens of liters or less. Also, V _s is almost the same between Si and GaAs, but Si is higher than GaAs (see FIG. 7). Because of this, rather than the already mentioned HEMT
It can be seen that a Si MOSFET with high g _m can be realized. The condition therefor is that the second term in {} of the equation (2) is larger than the first term.

That is, Is the condition. By transforming equation (5),
After all Is the condition.

Next, the value of L _g satisfying the expression (6) will be specifically considered.

FIGS. 4A to 4D show the results of calculation of the relationship between the transconductance g _m and the gate length L _g , using the mobility μ as a parameter. Calculation is d = 10, 30
Å, n _s = 10 ¹² , 10 ¹³ cm ^-2 . For example, a typical condition as shown in FIG. 4C, that is, d =
Considering 30 Å, n _s = 10 ¹² cm ^-2 , μ = 500 cm ² / Vs, g _m is V
_It can be seen that the range of L _g determined by _s is L _g 500 Å. Therefore, by setting L _g 500 Å, the theoretically highest g _m can be obtained, which makes it possible to realize a Si MOSFET that can operate at a higher speed than HEMT and the like. As can be seen from FIGS. 4A to 4D, the value of L _{g at which} g _m does not depend on L _g is larger as n _s is larger and μ is larger.

Next, FIGS. 5A and 5B show FETs using GaAs.
At 100 Å depth from the surface of the GaAs layer, a Dirac-delta doped layer (a monoatomic layer impurity-doped layer having a two-dimensional spread, hereinafter referred to as a δ-doped layer)
The results obtained by calculating the relationship between g _m and L _g using equation (2) in the case of forming Here, FIG. 5A shows the case where the carriers generated from the δ-doped layer are electrons, and FIG. 5B shows the case where the carriers generated from the δ-doped layer are holes. The concentration n _s of the two-dimensional electron gas or the two-dimensional hole gas formed at the δ-doped layer is 10 ¹³
cm ⁻² (10 ¹⁹ cm ^{−3 in} peak concentration (volume concentration)) was used as a typical value, and the depth d of the channel made of the two-dimensional electron gas or the two-dimensional hole gas was 100 Å in all cases. Further, from FIG. 6, the electron mobility μ _n and hole mobility μ _{p at} this time are μ _n = 1000 cm ² / Vs, μ _p = 100 cm ² / V
I took s. The value obtained from FIG. 7 was used as the carrier saturation velocity V _s . 6 and 7 show SMSze, Physics of Semiconductor Devices, N
Excerpts from ew York: Wilev, 1981. Fig. 7 does not show data of the saturation velocity V _s of holes in GaAs, but it is almost the same when comparing the effective mass of holes in GaAs and Si, and the shape of the valence band is also in Si. from the fact that GaAs is also almost unchanged, V _s of holes in GaAs is the hole in the Si
It is considered to be almost equal to V _s . Therefore, it can be considered that neither electrons nor holes change in terms of V _s . From this, V _s = 1 × 10 ⁷ cm / s in the calculation of FIGS. 5A and 5B.

As can be seen from FIGS. 5A and 5B, L _g = 1 ×
In 10 ⁵ Å, g _m when using holes is g when using electrons
_Although it is as small as about 1/10 of _m , when L _g <1000 Å, g _m has almost the same value regardless of whether electrons or holes are used.
In Figure 5 A and Figure 5 B, L _g <at 1000Å of g _m L _g
The dependence disappears because g _m is the second value in {} in the equation (2).
It corresponds to what is determined by the term, that is, g _m is expressed by the equation (4). Thus, the limit frequency f of the FET when g _m is expressed by the equation (4) is C _g when the capacitance between the gate electrode and the channel is C _g. It is represented by From equation (7), since V _s is almost the same for both electrons and holes, it can be seen that both FETs using electrons and FETs using holes operate at theoretically the highest speed determined by V _s. . The above condition that the L _g dependence of g _m is no longer
It is expressed by the following equation similar to equation (6).

Here, the minimum value of the electron mobility μ _n and the hole mobility μ _p is used as μ *. That is, μ *
= Min (μ _n , μ _p ).

The above is the discussion on the FET using GaAs, but the same discussion holds for Si, for example.

The present invention has been made based on the above study.

That is, the field-effect transistor according to the present invention has a gate length L _g , It is.

Further, in the semiconductor integrated circuit device according to the present invention, a plurality of field effect transistors composed of different polarities and / or different kinds of semiconductors are formed on a single semiconductor substrate, and when the gate length of the field effect transistor is L _g , It is.

Here, μ * is the type of heterogeneous semiconductor, i = 1, 2, ...
, N, and electron mobility and hole mobility in each semiconductor are represented by μ _n ⁱ and μ _p ⁱ , respectively, μ * = min (μ _{n
^{1, μ p 1, ......,}} μ n i, μ p i, ......, μ n N, is a μ _p ^N).

[Action]

In the field effect transistor according to the present invention configured as described above, since the gate length L _g is selected as shown in equation (9), the transconductance g _m becomes the maximum value determined by the saturation speed of carriers, It does not depend on the mobility of the carrier. Therefore, theoretically the ultra-high speed operation of the highest speed can be realized regardless of the mobility of carriers in the semiconductor used.

Further, in the semiconductor integrated circuit device according to the present invention configured as described above, since the gate length L _g of the field effect transistor is selected as shown in the expression (10), it is configured by different polarities and / or different semiconductors. The transconductance g _m of the generated field effect transistor can be set to a theoretically maximum value determined by the saturation speed of carriers. As a result, the operating speed of each field-effect transistor can be adjusted to the theoretical maximum speed that does not depend on the carrier mobility. Further, each field effect transistor can have the same shape. Therefore, high integration density can be achieved by this amount.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Example I FIGS. 1A and 1B show Si according to Example I of the present invention.
Shows a MOSFET.

As shown in FIGS. 1A and 1B, this Example I
In Si MOFSET in, for example, p-type Si substrate 1
An insulating film 2 such as a SiO ₂ film having a film thickness of about 700 Å is formed on top of this. An opening 2a is formed in this insulating film 2. Reference numeral 3 indicates a gate insulating film such as a SiO ₂ film having a film thickness of about 30 Å. Reference numeral 4 indicates a gate electrode made of a metal such as tungsten (W). The width of the gate electrode 4, that is, the gate length L _g is selected to a value that satisfies the expression (9). Specifically, for example, L _g = 500
Å. In the Si substrate 1 in the opening 2a, for example, an n ⁺ type source region 5 and a drain region 6 are formed in self-alignment with the gate electrode 4.
Pad electrodes 7 and 8 are formed on the source region 5 and the drain region 6, respectively. A pad electrode 9 is also formed on one end of the gate electrode 4.

Next, the Si MOS according to Example I configured as described above
An example of the method of manufacturing the FET will be described.

As shown in FIG. 2A, first, the insulating film 2 is formed on the entire surface of the p-type Si substrate 1 by, for example, the thermal oxidation method or the CVD method.

Next, as shown in FIG. 2B, a predetermined portion of the insulating film 2 is removed by etching to form an opening 2a.

Next, as shown in FIG. 2C, after an insulating film 3 such as a SiO ₂ film is formed on the entire surface by, for example, a CVD method, a W film is formed on the insulating film 3 by, for example, a sputtering method or an evaporation method.
To form a metal film 10. After that, a source gas such as alkylnaphthalene is introduced into a sample chamber evacuated to a high vacuum of an electron beam irradiation device (not shown), and the metal film 10 is placed in the source gas atmosphere in the sample chamber.
The electron beam 11 whose beam diameter is narrowed is irradiated to a predetermined pattern. The acceleration voltage of the electron beam 11 is, for example, about 6 kV, and the beam current is, for example, about 20 μA. The pressure of the source gas atmosphere is, for example, 10 ⁻⁵ to 10 ⁻⁸ Torr.
And is typically 10 ^-7 Torr. This electron beam 11
The source gas is decomposed by the irradiation to generate a hydrocarbon-based substance on the metal film 10, whereby a resist 12 having an extremely fine width made of this hydrocarbon-based substance is formed. This register 12 has excellent dry etching resistance.

Next, using the resist 12 as a mask, the metal film 10 and the insulating film 3 are anisotropically etched in a direction perpendicular to the substrate surface by, for example, a reactive ion etching (RIE) method using a CF ₄ -based etching gas, As shown in FIG. 2D, a gate electrode 4 having an extremely fine width and having a gate length L _g satisfying the expression (9) is formed. After that, the resist 12 is removed by etching.

Next, after forming a film of an n-type impurity such as phosphorus (P) on the entire surface by, for example, plasma CVD method, for example, Xe
Pulsed laser beam (wavelength by Cl excimer laser
308 nm) is applied to the entire surface. The surface layer of the semiconductor substrate 1 is instantaneously heated to a high temperature by the irradiation of the pulsed laser beam, and as a result, the n-type impurity is extremely shallow in the semiconductor substrate 1 in direct contact with the film of the n-type impurity described above. Moreover, it is highly doped. As a result, as shown in FIG. 2E, the source region 5 and the drain region 6 having an extremely shallow depth of about 100 Å and a high impurity concentration,
Are formed in self-alignment with the gate electrode 4. It should be noted that such an impurity doping method is used for the LIMPID (Laser
Induced Melting of Predeposited Impurity Doping)
It is called the law. The source region 5 and the drain region 6 can also be formed by a method other than the above LIMPID method, for example, a low energy ion implantation method.

Thereafter, as shown in FIGS. 1A and 1B, pad electrodes 7, 8 and 9 are formed to complete the target Si MOSFET.

According to this Example I, since the gate length L _g is selected so as to satisfy the equation (9) as described above, the theoretically highest transconductance determined by the saturation velocity V _s of the carriers in Si. You can get the resistance g _m . As a result, it is possible to realize ultra-high-speed operation at about 1 THz even though Si, which has a lower electron mobility than GaAs, is used. it can.

Example II FIGS. 8A and 8B show a complementary MOSFET according to Example II of the present invention.

As shown in FIGS. 8A and 8B, this Example II
In the complementary MOSFET by, for example, a p-type Si substrate 1
An n-channel MOSFET Q ₁ having the same configuration as that of the first embodiment is formed on the top. An n well 13 is formed in the Si substrate 1. Then, in the n well 13 in the opening 2b formed in the insulating film 2, a gate electrode 14 made of a metal such as W and a source region 15 formed in self-alignment with the gate electrode 14 and A p-channel MOSFET Q _{2 including the} drain region 16 is formed. Reference numeral 17,
Reference numerals 18 and 19 denote pad electrodes. These n-channel MOSFETs
Q ₁ and p-channel MOSFET Q ₂ form a complementary MOSFET. FIG. 9 shows an equivalent circuit of this complementary MOSFET. In FIG. 9, V _DD is the power supply voltage, V _in is the gate input voltage, and V _out is the output voltage.

In this Example II, the gate length L _gn of the n-channel MOSFET Q ₁ and the gate length L _gp of the p-channel MOSFET Q ₂ are both set to the same value that satisfies the expression (10). However, μ * in the equation (10) is μ * = min (μ _n ^si , μ _p ^si ) =
Use μ _p ^si . Gate lengths L _gn and L _gp that satisfy equation (10)
The value of is, for example, about 500Å. Also, n
Gate width W _gn of channel MOSFET Q ₁ and p-channel MOSFE
The gate width W _{gp of} TQ ₂ is also selected to be the same value.

Next, an example of a method of manufacturing the complementary MOSFET according to the embodiment II configured as described above will be described.

As shown in FIGS. 8A and 8B, first, the Si substrate 1
After forming the n-well 13 by, for example, ion implantation,
The insulating film 2 is formed on the substrate 1. Next, openings 2a and 2b are formed in this insulating film 2. Next, after forming the gate insulating film 3 on the entire surface, a metal film such as W is formed on the gate insulating film 3. Next, the metal film and the gate insulating film 3 are sequentially patterned into a predetermined shape in the same manner as in Example 1 to form gate electrodes 4 and 14 having an extremely fine width. Next, with the surface of the n well 13 covered with a mask, for example, the n ⁺ type source region 5 and drain region 6 are self-aligned with the gate electrode 4 by the LIMPID method described in the first embodiment. Form. Next, for example, a p ⁺ type source region is self-aligned with the gate electrode 14 by the LIMPID method using a p-type impurity such as boron (B).
15 and drain region 16 are formed. After that, pad electrodes 7, 8, 9, 17, 18, and 19 are formed to complete the intended complementary MOSFET.

According to this Example II, since the gate length L _gn of the n-channel MOSFET Q ₁ and the gate length L _gp of the p-channel MOSFET Q ₂ are both selected to satisfy the equation (10), these n-channel MOSFET Q 1 _{Both the 1-} and p-channel MOSFET Q ₂ have the theoretically highest transconductance g _m determined by the saturation speed V _s . Therefore, these n-channel MOSFETs
Both Q ₁ and p-channel MOSFET Q ₂ operate at ultra-high speeds at theoretically highest speeds. As a result, it is possible to realize a complementary MOSFET capable of ultra-high speed operation. Further, as described above, conventionally, in order to increase the speed of the complementary MOSFET, it is necessary to increase the gate width of the p-channel MOSFET.
Inevitably, the gate width of the p-channel MOSFET Q ₂ can be made the same as that of the n-channel MOSFET Q ₁ according to this Example II, although it must be considerably larger than that of the SFET. That is, p-channel MOSFET Q ₂ is replaced with n-channel MOSFET
Can have the same shape as Q ₁ . As a result, the integration density of complementary MOSFETs can be improved.

Example III FIG. 10 shows Example III of the present invention. This Example III
Is an embodiment in which the present invention is applied to a complementary FET composed of a FET using GaAs.

As shown in FIG. 10, in this embodiment III, undoped GaAs layers 21 and 22 are formed on a semi-insulating GaAs substrate 20, and n-type Al _x Ga is formed on these GaAs layers 21 and 22, respectively.
_{A 1-x} As (0 <x <1) layer 23 and a p-type Al _x Ga _1-x As layer 24 are formed. Reference numerals 25 and 26 are Schottky gate electrodes, reference numerals 27 and 28 are source electrodes, and reference numerals 29 and 30 are drain electrodes. The GaAs layer 21, the n-type Al _x Ga _1-x As layer 23, the Schottky gate electrode 25, the source electrode 27, and the drain electrode 29 form an n-type FET (HEMT) using electrons. This n-type FET is formed in the GaAs layer 21 near the interface with the n-type Al _x Ga _1-x As layer 23 by the electrons supplied from the n-type Al _x Ga _1-x As layer 23. The dimensional electron gas 31 is used as a channel. On the other hand, GaAs layer 22, p-type Al _x Ga _1-x As
The layer 24, the Schottky gate electrode 26, the source electrode 28, and the drain electrode 30 form a p-type FET using holes. The p-type FET is formed in the GaAs layer 22 near the interface with the p-type Al _x Ga _1-x As layer 24 by the holes supplied from the p-type Al _x Ga _1-x As layer 24. The two-dimensional hole gas 32 is used as a channel. The n-type FET and the p-type FET described above form a complementary FET similar to that shown in FIG.

In this Example III, the gate length L _gn of the n-type FET and the gate length L _gp of the p-type FET are both set to the same value satisfying the expression (10). However, μ * in equation (10)
Uses μ * = min (μ _n ^GaAs , μ _p ^GaAs ) = μ _p ^GaAs .

Next, an example of a method of manufacturing the complementary FET according to the embodiment III configured as described above will be described.

As shown in FIG. 10, first, an undoped GaAs layer 21 and an n-type Al _x Ga _1-x As layer 23 are formed on the entire surface of the semi-insulating GaAs substrate 20, for example, by molecular beam epitaxy (MBE) method or metal organic chemical vapor phase. Sequentially formed by growth (MOCVD) method. Next, after removing the predetermined portions of the n-type Al _x Ga _1-x As layer 23 and the GaAs layer 21 by etching, the n-type Al _x Ga left by the etching is removed.
The surface of the _1-x As layer 23 is covered with a mask, and in this state, MBE method or MO
Undoped GaAs layer 22 and p-type Al _{x on the} entire surface by the CVD method
The Ga _1-x As layer 24 is formed. Next, these p-type Al _x Ga _1-x A
Predetermined portions of the s layer 24 and the GaAs layer 22 are removed by etching to obtain the shape shown in FIG. After this, the Schottky gate electrodes 25, 26, the source electrodes 27, 28 and the drain electrode 29,
Form 30 to complete the desired complementary FET.

In this Example III, the gate length L _gn of the n-type FET and the gate length L _gp of the p-type FET are both selected to satisfy the expression (10), so that these n-type FET and p-type FET F
Both ETs have theoretically the highest transconductance g _m determined by the saturation velocity V _s of electrons or holes in GaAs. Therefore, both these n-type FET and p-type FET operate at theoretically the highest speed and at ultra-high speed. As a result, similar to Example II, the complementary PET that enables ultra-high-speed operation
Can be realized. Moreover, as in Example II,
Since the p-type FET can have the same shape as the n-type FET,
Therefore, the integration density of complementary FETs can be improved accordingly.

In this Example III, the depth d of the channel formed by the two-dimensional electron gas or the two-dimensional hole gas was d.
Is selected to be about 1/3 or less of the gate lengths L _gn and L _gp . This is because the channel depth d is about 1 / of the gate lengths L _gn and L _gp.
This is because if it is about 3 or more, the channel will not close when the FET should be turned off.

Example IV FIG. 11 shows Example IV of the present invention. This Example IV
It is an embodiment in which the present invention is applied to an optoelectronic integrated circuit (OEIC) in which Si-based elements and GaAs-based elements are integrated on a single Si substrate.

As shown in FIG. 11, in the OEIC according to Example IV, a GaAs / AlGaAs layer 33 is formed on a part of the Si substrate 1. Then, the Si MOSFET circuit 34 is formed on the Si substrate 1, and the GaAs / AlGaAs layer 33 has the GaAs FET circuit 35 and the laser diode array or photodetector array.
36 are formed. Reference numeral 37 indicates wiring.

FIG. 12 shows a circuit configuration example of a laser diode array. In FIG. 12, LD is a laser diode, R ₁ is a resistor, and Q ₃ is a normally-off GaAs FET. The laser diode LD is, for example, a GaAs / AlGaAs double heterojunction laser. Further, the gate voltage V _G output from the Si MOSFETs forming the Si MOSFET circuit 34 is applied to the gate of the GaAs FET Q ₃ . FIG. 13 shows the relationship between the input of the gate voltage V _G to the gate of the GaAs FET Q ₃ and the laser light output L from the laser diode LD. Next,
Figure 14 shows the circuit configuration of the photo detector array.
In FIG. 14, reference symbol R ₂ is a resistor, reference symbol Q ₄ is a normally-off GaAs FET, and reference symbol D is a photodiode. The output of the inverter consisting of these resistors R ₂ and GaAs FET Q ₄
V _out is amplified by the Si MOSFET circuit 34. Reference numeral R ₃ indicates a resistor, and reference numeral Q ₅ indicates a Si MOSFET of the Si MOSFET circuit 34. Laser light input L'to photodiode D and GaAs FETQ ₄
FIG. 15 shows the relationship between the input of the gate voltage V _G to the gate of and the output V _out .

In this Example IV, the gate length of the Si MOSFET that constitutes the Si MOSFET circuit 34 and the gate length of the GaAs FET that constitutes the GaAs FET circuit 35 are selected to satisfy the formula (10). In this case, as μ * in equation (10), Si MOS
If there are n-type and n-type FETs and GaAs FETs, μ * = min (μ _n ^si , μ _p ^si , μ _n ^GaAs ,
μ _p ^GaAs ) = μ _p ^GaAs is used.

According to this Example IV, both the Si MOSFET and the GaAs FET have theoretically the highest transconductance determined by the saturation speed V _s.
Having g _m , therefore these Si MOSFETs and GaAs FETs can be operated at ultra-high speeds at theoretically highest speeds.
Moreover, since these Si MOSFETs and GaAs FETs can have the same shape, an OEIC with high integration density can be realized.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications based on the technical idea of the present invention are possible.

For example, the present invention is directed to semiconductors other than Si and GaAs (for example,
It can also be applied to FETs using germanium (Ge). The present invention can also be applied to a Schottky gate type FET using GaAs, that is, a GaAs MESFET. In this case, as described above, the channel depth d needs to be about 1/3 or less of the gate length.
For example, if the gate length is about 1000Å, the channel depth d needs to be about 300Å. Gate length is 5
When it is about 00Å or less, the channel depth d must be about 150Å or less. In such cases, δ
It is necessary to use a doped layer. Figure 16 shows an example.
In FIG. 16, δ-doped layers 38 and 39 are formed at depths d ₁ and d ₂ from the surface of the undoped GaAs layer 21 formed on the semi-insulating GaAs layer 20. Specifically, d ₁ and d ₂ are, for example, 10Å and 30Å, respectively. In this case, the δ-doped layer 38 is for supplying electrons to the surface of the GaAs layer 21. On the other hand, a channel is formed by the two-dimensional electron gas formed at the δ-doped layer 39. In FIG. 16, reference numeral 40 is a Schottky gate electrode, and reference numerals 41 and 42.
Indicates a source electrode and a drain electrode, respectively.

〔The invention's effect〕

As described above, according to the field effect transistor of the present invention, it is possible to realize a theoretically highest speed of ultra-high speed operation regardless of the mobility of carriers in the semiconductor used.

Further, according to the semiconductor integrated circuit device of the present invention, the operating speed of the field effect transistor composed of different kinds of polarities and / or different kinds of semiconductors can be adjusted to a theoretical maximum speed independent of carrier mobility. Moreover, each field effect transistor can have the same shape.

[Brief description of the drawings]

1A is a plan view showing a Si MOSFET according to Example I of the present invention, FIG. 1B is a cross-sectional view taken along line XX of FIG. 1A, and FIGS. Sectional drawing which shows an example of the manufacturing method of Si MOSFET shown to FIG. 1A and FIG. 1B in process order,
FIG. 3 is a perspective view showing a model used for calculation of transconductance, and FIGS. 4A to 4D are graphs showing relations between transconductance and gate length calculated by various conditions. FIG. 5A is a graph showing the relationship between the transconductance and the gate length of a GaAs-based FET that uses electrons generated from the δ-doped layer, and FIG. 5B is a graph of a GaAs-based FET that uses holes generated from the δ-doped layer. Graph showing the relationship between transconductance and gate length, 6th
FIG. 8 is a graph showing the relationship between carrier mobility and impurity concentration in GaAs, FIG. 7 is a graph showing the relationship between carrier drift velocity and electric field, and FIG. 8A is a complementary type according to Example II of the present invention. FIG. 8B is a plan view showing the FET, and FIG.
FIG. 9 is a sectional view taken along line Y, FIG. 9 is a circuit diagram showing an equivalent circuit of the complementary FET shown in FIGS. 8A and 8B, and FIG. 10 is a complementary FET according to a third embodiment of the present invention. Sectional view shown, No. 11
12 is a perspective view showing an OEIC according to Embodiment IV of the present invention, FIG. 12 is a circuit diagram showing a configuration example of a laser diode system circuit of the OEIC shown in FIG. 11, and FIG. 13 is a laser diode system shown in FIG. FIG. 14 is a waveform diagram showing the relationship between the gate input and the laser light output in the circuit, FIG. 14 is a circuit diagram showing a configuration example of the photodetector system circuit of the OEIC shown in FIG. 11, and FIG.
FIG. 16 is a waveform diagram showing the relationship between laser light input, gate input and output in the photodetector system circuit shown in FIG. 16, and FIG. 16 is a sectional view for explaining a modification of the present invention. Description of main symbols in the drawings 1: Si substrate, 4, 14: gate electrode, 25, 26: Schottky gate electrode, 5, 15: source region, 6, 16: drain region.

Claims (2)

(57) [Claims] 1. When the gate length is L _g , A field effect transistor characterized by: 2. A plurality of field effect transistors composed of different polarities and / or different kinds of semiconductors are formed on a single semiconductor substrate, and when the gate length of the field effect transistor is L _g , And a semiconductor integrated circuit device.