JPH0282324A - In-circuit emulator - Google Patents

Abstract

PURPOSE:To guarantee a debugging microprocessor the stable operation and to prevent hindrance in the operation of a microcomputer system to which an in-circuit emulator is connected by providing a D flip flop and a phase control circuit. CONSTITUTION:A phase control circuit 8 generates a latch signal of such timing that the signal 7 can be latched in a D flip flop 2 after going to the high level of a signal TRREADY 4 and a signal READY 5 by which step out of debugging microprocessors 1a and 1b does not occur can be supplied. Thus, debugging microprocessors 1a and 1b are guaranteed to perform the stable operation, and the operation of the microcomputer system to which the in-circuit emulator is connected is not hindered.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a configuration method for an in-circuit emulator, and particularly to a circuit configuration for inputting input signals from outside the in-circuit emulator to a debugging microprocessor.

[Conventional technology]

There is a conventional in-circuit emulator that uses two debugging microprocessors in synchronization. In such cases, such as when the setup time is short when sampling the input signal, one debugging microprocessor receives the input as a high level, but the other debugging microprocessor receives the input as a low level, causing subsequent operations to deviate. Sometimes it happens. For this reason, the input signal input to the debugging microprocessor is latched by a clock signal or the like to ensure sufficient setup time and hold time for sampling by the debugging microprocessor.

FIG. 3 shows a latch circuit for external input signals in a conventional in-circuit emulator. In Figure 3, 1a
and 1b are debugging microprocessors that sample READY signal 5, one of the input signals, at the rising edge of the clock at the end of T2 of a bus cycle consisting of T1 state and T2 state. If a high level is sampled, that bus cycle is ended and the next T1 state is entered. When the low level is sampled, the wait state (TW) is entered, and the READY signal 5 is sampled again at the clock and rising edge of the end of TW. TR from outside the in-circuit emulator
Microprocessor l for direct debugging of EADY signal 4
If input to a, lb, TREAD at sampler
When the Y signal 4 changes, the debugging microprocessor 1a may sample a high level, and the debugging microprocessor 1b may sample a low level. In such a case, only the debugging microprocessor 1b has a wait cycle TW.
This causes the two debugging microprocessors to become out of sync, causing the in-circuit emulator to stop working. To prevent this, the TREADY signal 4 from outside the in-the-kit emulator is latched into the D flip-flop 2 at the rising edge of the latch signal 7, which is obtained by inverting the clock signal 6 by the inverter 3, and the R
Prevent the EADY signal 5 from changing at the Zamplinder point.

Since the TREADY signal 5 is latched 1/2 clock ahead of the sampling of the debugging microprocessors la and lb, the setup time and hold time are each 2 clocks before the sampling of the debugging microprocessors la and lb. A sufficient value of 1/2 clock can be secured. Therefore, the two debugging microprocessors 1a and 1b can operate stably without getting out of synchronization.

[Problem to be solved by the invention]

In the above-mentioned in-circuit emulator, the debugging microprocessors 1a and 1b have a two-chip configuration.
In order to prevent the two debugging microprocessors from operating differently due to the signal level changing when sampling the READY signal 5,
The TREADY signal 4 from the outside is
It is latched to flip-flop 2. Therefore, the operation of this chip and the in-circuit emulator differs. In other words, when the TREADY signal 4 becomes high level from the falling edge of the clock of T2 as shown in the timing chart of FIG. 4, the READY signal 5 output from the D flip-flop 2 becomes high level at the last sampling timing of T2. Because this is not the case, one clock worth of wait state TW is inserted.

Furthermore, as shown in Figure 5, if the high level of the TREADY signal 4 is input at a timing that is not maintained until the falling edge of the next clock, the TW state will continue forever because the high level cannot be latched into the D flip-flop 2. This will result in

As described above, depending on the timing design of the microcomputer system, there is a problem in that although it may work on an actual chip, it may not work correctly when an in-circuit emulator is connected.

[Means to solve the problem]

The in-circuit emulator of the present invention has a D flip-flop that latches a signal input from outside the in-circuit emulator and inputs it to a debugging microprocessor, and a latch signal to the D flip-flop from a clock signal input to the debugging microprocessor. It has a phase control circuit for generating.

Therefore, stable operation of the debugging microprocessor can be guaranteed, and the operation of the microcomputer system to which the in-circuit emulator is connected can be made unhindered.

〔Example〕

The present invention will be explained with reference to the drawings.

FIG. 1 shows a latch circuit for an external input signal in an in-circuit emulator of the present invention, and FIG. 2 shows an embodiment of the phase control circuit shown in FIG. This embodiment differs in that a phase control circuit 8 is provided in place of the inverter 3 that inverts the phase of the clock signal 6 in the conventional in-circuit emulator to generate the latch signal 7 of the D flip-flop 2.

The phase control circuit 8 generates a latch signal at a timing such that it can be latched into the D flip-flop 2 after the TREADY signal 4 becomes high level, and the debugging microprocessors 1a and 1b can supply the READY signal 5 without causing loss of synchronization. The aim is to make 7.

In FIG. 2, the clock signal 6 is input to phase comparators 8a,
The signal is input to a digital PLL circuit composed of a PF/AMP 8b, a VCO 8c, and a 10 frequency divider 8d. In this digital PLL circuit, the VCO 8c oscillates at a frequency ten times that of the clock signal 6, and applies pressure to the vCO clock signal 8f. The vCO clock signal 8f is divided into 1 by a 10 frequency divider 8d.
The clock signal 6 is divided into 1/0, and the phase comparator 8a outputs the clock signal 6.
The phase is compared with LPF/AMP 8b and the phase difference is LPF/AMP 8b.
Since it is fed back to the oscillation frequency of the VC○ 8c through the VC○ 8c, the ■CO clock signal 8f is always kept at 10 times the clock signal 6.

The counter 8e is cleared while the clock signal 6 is at high level, and when it becomes low level, it starts counting the CO clock signal 8f. When the count value reaches the set count number N, the latch signal 7 is changed to 1 of the VCO clock signal 8f.
Counting is stopped after the clock is set to high level.

FIG. 2 shows an example where the count number N is set to 3.

From the falling edge of clock signal 6 to VCO clock signal 8
A latch signal 7 is output at the rising edge of the third clock of f. By outputting such a latch signal 7,
The high level of the TREADY signal 4 can be latched into the D flip-flop 2 at the timing shown in FIG. Since sampling can be performed, it is possible to operate in the same cycle as the actual chip without entering an extra wait cycle. Second
In the figure, the count number N can be set to 2.3.4, but T for the latch signal 7 of the D flip-flop 2 is
Settings must be made such that the set-up time of the READY signal 4 is maintained and the set-up time of the READY signal 5 is maintained for sampling of the debugging microprocessors la and lb.

FIG. 6 shows a second embodiment of the phase control circuit of the in-circuit emulator of the present invention. In this example, digital P
The circuit is simplified by using a delay circuit instead of the LL circuit.

In FIG. 6, 8g is a delay circuit which outputs a signal obtained by adding a certain delay to the input. 8h is selector from A to D
One of them is selected and output to output Y. selector 8h
When input A is selected, the output latch signal 7 has the same timing as the conventional example in FIG.
The ADY signal 4 is latched into the D flip-flop 2 at the falling edge of the clock signal 6. When inputs B to D of selector 8h are selected, TRE is activated at a timing that takes the delay time of delay circuit 8g from the falling edge of clock signal 6.
Latch ADY signal 4.

In this embodiment, the latch signal 7 is not delayed by a certain phase of the p rough signal 6, but is delayed for a certain period of time. Therefore, if the frequency changes, the phase of the latch signal 7 with respect to the clock signal 6 will also change, but the circuit is simpler than a digital PLL circuit and does not require adjustment.

〔Effect of the invention〕

Since the in-circuit emulator of the present invention has a D flip-flop that latches a signal input from outside the in-circuit emulator and inputs it to the debugging microprocessor, multiple debugging microprocessors operating in synchronization sample the signal. The level of the input signal does not change in timing. Furthermore, since it has a phase control circuit that generates a latch clock to the D flip-flop from a clock signal input to the debugging microprocessor, it is possible to latch a signal input from outside the in-circuit emulator at an appropriate timing.

Therefore, it is possible to guarantee stable operation of the debugging microprocessor and to ensure that the operation of the microcomputer system to which the in-circuit emulator is connected is not hindered.

[Brief explanation of the drawing]

Figures 1 (A) and (B) are block diagrams and time charts of the in-circuit emulator of the present invention, and Figures 2 (A) and (B) are diagrams of an embodiment of the phase control circuit of Figure 1 and their time charts. Charts, Figures 3 (A) and (B) are diagrams of conventional in-circuit emulators and their time charts, Figures 4 and 5 are problems with conventional in-circuit emulators, and Figures 6 (A) and ( B) is a configuration diagram and a time chart of a second embodiment of the phase control circuit shown in FIG. 1. la, lb...debugging microprocessor, 2...D flip flow rough, 3...
Inverter, 4...TREADY signal, 5...
... READY signal, 6 ... clock signal, 7 ... latch signal, 8 ... phase control circuit, 8a ... phase comparator, 8b ... ...LP
F/AMP, 8 c --V C○, 8 d--・--
10 frequency divider, 8e...Counter, 8f...
・■CO clock signal, 8g...Delay circuit, 8
h...Selector.

Claims (1)

[Claims] In an in-circuit emulator that uses a debugging microprocessor, there is a flip-flop that latches a signal input from outside the in-circuit emulator and inputs it to the debugging microprocessor, and a flip-flop that uses a clock signal input to the debugging microprocessor to An in-circuit emulator comprising: a phase control circuit that generates a latch signal to the in-circuit emulator.