JPH0281518A - Self-running processing system - Google Patents
Self-running processing systemInfo
- Publication number
- JPH0281518A JPH0281518A JP63232420A JP23242088A JPH0281518A JP H0281518 A JPH0281518 A JP H0281518A JP 63232420 A JP63232420 A JP 63232420A JP 23242088 A JP23242088 A JP 23242088A JP H0281518 A JPH0281518 A JP H0281518A
- Authority
- JP
- Japan
- Prior art keywords
- input
- control data
- frequency
- phase difference
- integration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003672 processing method Methods 0.000 claims description 3
- 230000032683 aging Effects 0.000 abstract description 11
- 230000010354 integration Effects 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 5
- 230000010355 oscillation Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 230000003679 aging effect Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000008676 import Effects 0.000 description 1
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野コ
本発明は、ディジタル処理型位相同期発振器（以下ＤＰ
ＬＬと略）の動作に係り、特に（ＤＰＬＬ自走中の）発
振器のエージングに起因する定常位相誤差を抑圧するの
に好適な制御方法に関する。[Detailed Description of the Invention] [Industrial Field of Application]
The present invention relates to a control method suitable for suppressing steady-state phase errors caused by aging of an oscillator (during free-running DPLL).
［従来の技術］
従来のＤＰＬＬにおいて、入力断が発生した時の自走処
理は、ＮＴＴ研究実用化報告第２８巻７号（１９’７９
年）２６２ページに記載されているように、処理装置が
過去の発振器制御情報から演算した発振器制御情報を固
定して発振器を制御することにより行なっている。この
動作を第２図および第３図を用いて説明する。[Prior art] In a conventional DPLL, self-running processing when an input interruption occurs is described in NTT Research Practical Application Report Vol. 28, No. 7 (19'79).
As described on page 262 of 2010, this is done by fixing oscillator control information calculated from past oscillator control information by a processing device and controlling the oscillator. This operation will be explained using FIGS. 2 and 3.
第２図はＤＰＬＬの解析モデルであり、ＩＮは入力、Ｏ
ＵＴは出力、ＤＰＣは入力ＩＮと出力ＯＵＴの位相差φ
を検出する位相比較器、ＰＲＯは位相差φにＤＰＬＬの
ループ利得を掛ける比例回路、ＩＮＴは位相差φの値を
積分する積分回路、ＡＤＤは比例回路ＰＲＯと積分回路
ＩＮＴの出力を加算し、発振器の制御データを作る加算
器、ＤＣＸ○は加算器ＡＤＤの値により発振周波数を制
御できるディジタル制御発振器を示す。Figure 2 shows the DPLL analytical model, where IN is the input and O
UT is the output, and DPC is the phase difference φ between input IN and output OUT.
PRO is a proportional circuit that multiplies the phase difference φ by the loop gain of the DPLL, INT is an integral circuit that integrates the value of the phase difference φ, ADD is a proportional circuit that adds the outputs of the proportional circuit PRO and the integral circuit INT, An adder that creates control data for the oscillator, DCX○, indicates a digitally controlled oscillator whose oscillation frequency can be controlled by the value of the adder ADD.
第３図は従来のＤＰＬＬの処理装置の動作フローである
。入力ＩＮが入力されると第３図左半分の通常処理で示
すように処理装置は、ＤＰＣから出力された位相差φを
とりこむ。つぎに処理装置はＰＲＯにφを入力しＤＰＬ
Ｌのループ利得を掛け比例制御データを作成する。また
ＩＮＴにもφを入力して積分を行い、ＤＣＸＯのエージ
ングに起因する定常位相誤差の発生をキャンセルする積
分制御データを作成する。制御装置は比例制御データと
積分制御データをＡＤＤで加算してＤＣＸＯに入力する
ことで出力ＯＵＴの周波数を入力ＩＮと一致させる制御
を行う。一方、入力ＩＮが断となると、処理装置は第３
図有半分の自走処理で示すように、位相差φのとりこみ
、ＰＲＯ，ＩＮＴによる比例制御データおよび積分制御
データの作成を行れす、ＤＣＸＯの制御データを入力断
面従来技術では、自走中はＤＣＸＯの制御データが固定
され発振器の周波数経時変化（エージング）の補償につ
いて配慮されてない為、ＤＰＬＬの自走中に発振周波数
が変化する。このためＤＰＬＬの入力が回復し、再び周
波数同期をとる際、発振周波数を入力周波数に一致させ
る為、定常位相誤差が発生するという問題があった。FIG. 3 is an operational flow of a conventional DPLL processing device. When the input IN is input, the processing device takes in the phase difference φ output from the DPC, as shown in the normal processing in the left half of FIG. Next, the processing device inputs φ to PRO and DPL
Multiply the loop gain of L to create proportional control data. Furthermore, φ is also input to INT to perform integration, thereby creating integral control data that cancels the occurrence of a steady phase error caused by aging of the DCXO. The control device performs control to match the frequency of the output OUT with the frequency of the input IN by adding the proportional control data and the integral control data using ADD and inputting the result to the DCXO. On the other hand, if the input IN is disconnected, the processing device
As shown in the self-running process in the half shown in the figure, it is possible to import the phase difference φ and create proportional control data and integral control data using PRO and INT. Since the control data of the DCXO is fixed and no consideration is given to compensation for the aging of the oscillator frequency, the oscillation frequency changes during free running of the DPLL. For this reason, when the input to the DPLL is restored and frequency synchronization is established again, there is a problem in that a steady phase error occurs because the oscillation frequency is made to match the input frequency.
本発明の目的はＤＰＬＬが自走中でもエージングによる
周波数変動を補償し、定常位相誤差の発生を防ぐための
自走処理方法を提供することにあ上記目的は、入力断時
に処理装置が比例制御データを固定する一方、入力断直
前の位相差φの積分を継続して積分制御データを作成す
ることにより、ＤＣＸＯの制御データを修正して発振器
のエージングの影響をキャンセルすることで達成される
。An object of the present invention is to provide a free-running processing method for compensating for frequency fluctuations due to aging even when a DPLL is free-running, and preventing the occurrence of steady-state phase errors. This is achieved by fixing , while continuing to integrate the phase difference φ immediately before the input cutoff to create integral control data, thereby modifying the control data of the DCXO and canceling the effects of aging of the oscillator.
［作用］
エージングによりＤＣＸＯの出力周波数が変動した場合
、ＤＣＸＯの制御データを補正すれば、前の周波数を出
力できる。位相差にループ利得を掛けた比例制御データ
（ＰＲＯ出力■φ）の他に位相差を積分した積分制御デ
ータ（ＩＮＴ出力＝ｆφｄｔ）をＤＣＸＯに加えれば、
積分制御データがエージングによる周波数変化を補正す
るための制御データ補正分となるので、位相差φを変動
させることなくＤＣＸＯの制御データを補正し、出力周
波数を一定に保てる。すなわち、入力が断の際に、断直
前の位相差φを積分してＤＣＸＯ制御データを補正すれ
ば、エージングの影響はキャンセルされ、出力周波数も
一定に保てる。[Operation] When the output frequency of the DCXO fluctuates due to aging, the previous frequency can be output by correcting the control data of the DCXO. If you add integral control data (INT output = fφdt) that integrates the phase difference to the DCXO in addition to the proportional control data (PRO output ■φ) that is the phase difference multiplied by the loop gain,
Since the integral control data serves as control data correction for correcting frequency changes due to aging, the control data of the DCXO can be corrected without changing the phase difference φ, and the output frequency can be kept constant. That is, when the input is cut off, if the DCXO control data is corrected by integrating the phase difference φ immediately before the cutoff, the influence of aging can be canceled and the output frequency can also be kept constant.
［実施例］
以下、本発明の一実施例を第１図および第２図を用いて
説明する。[Example] An example of the present invention will be described below with reference to FIGS. 1 and 2.
第１図は本発明によるＤＰＬＬの処理装置の動作フロー
であり、第３図と同様に左半分は第２図で示すＤＰＬＬ
の解析モデルで示した入力ＩＮが入力された場合の通常
処理を示す。この通常処理は従来のＤＰＬＬの動作と同
じである。一方第１図の右半分は本発明による入力ＩＮ
が断となった場合の自走処理を示す、入力断となると、
処理装置は位相差φのとりこみ、およびＰＲＯによる比
例制御データの作成を行わず、ＰＲＯの出力を入力断直
前の値に固定する。一方、ＩＮＴでは入力断直前の位相
差φの積分を通常処理と同様に行うことで、ＤＣＸＯの
エージングに起因する発振周波数変動を補正する積分制
御データを作成する。FIG. 1 shows the operation flow of the DPLL processing device according to the present invention, and similarly to FIG. 3, the left half shows the DPLL processing device shown in FIG.
This shows normal processing when the input IN shown in the analysis model is input. This normal processing is the same as the operation of a conventional DPLL. On the other hand, the right half of FIG. 1 is the input IN according to the present invention.
When the input is disconnected, it shows the self-propelled processing when the
The processing device does not take in the phase difference φ or create proportional control data using PRO, but fixes the output of PRO to the value immediately before the input cutoff. On the other hand, in the INT, integration of the phase difference φ immediately before input cutoff is performed in the same manner as in normal processing, thereby creating integral control data for correcting oscillation frequency fluctuations caused by aging of the DCXO.
この固定された比例制御データとＩＮＴで作成された積
分制御データをＡＤＤで加算してＤＣＸＯに入力するこ
とで、入力ＩＮが断となった場合でも、出力ＯＵＴの周
波数を補正しながら自走処理を行う。本実施例によれば
、入力断によるＤＰＬＬの自走中でも、出力ＯＵＴの周
波数はエージングによる周波数変化を補正した値となる
ので、入力ＩＮとほぼ一致した周波数を維持できる。し
たがって、入力ＩＮが回復して再び通常処理により周波
数同期をとる際、定常位相誤差が発生しないという効果
がある。By adding this fixed proportional control data and the integral control data created by INT using ADD and inputting it to the DCXO, even if the input IN is disconnected, free-running processing can be performed while correcting the frequency of the output OUT. I do. According to this embodiment, even when the DPLL is free-running due to an input cutoff, the frequency of the output OUT is a value corrected for frequency changes due to aging, so that it is possible to maintain a frequency that substantially matches the frequency of the input IN. Therefore, when the input IN is recovered and frequency synchronization is again performed by normal processing, there is an effect that no steady phase error occurs.
［発明の効果］
本発明によれば、ＤＰＬＬの入力断時も発振器のエージ
ング効果をキャンセルできるので、定常位相誤差の発生
を防ぐ効果がある。[Effects of the Invention] According to the present invention, the aging effect of the oscillator can be canceled even when the input to the DPLL is cut off, so there is an effect of preventing the occurrence of a steady phase error.
【図面の簡単な説明】
第１図は本発明の一実施例である自走処理方法を示すデ
ィジタル処理型位相同期発振器の制御装置の動作フロー
図。
第２図はディジタル処理型位相同期発振器の解析モデル
を示す説明図、
第３図は従来のディジタル処理型位相同期発振器の制御
装置の動作フロー図である。
符号の説明
ＩＮ・・・入力、○ＵＴ・・・出力、ＤＰＣ・・・位相
比較器、φ・・・入出力の位相差、ＩＮＴ・・・積分回
路、ＰＲＯ・・・比例回路、ＡＤＤ・・・加算器、ＤＣ
Ｘ○・・・ディジタル制御発振器。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an operational flow diagram of a control device for a digital processing type phase-locked oscillator, showing a free-running processing method according to an embodiment of the present invention. FIG. 2 is an explanatory diagram showing an analytical model of a digitally processed phase-locked oscillator, and FIG. 3 is an operation flow diagram of a conventional control device for a digitally processed phase-locked oscillator. Description of symbols IN...Input, ○UT...Output, DPC...Phase comparator, φ...Input/output phase difference, INT...Integrator circuit, PRO...Proportional circuit, ADD...・Adder, DC
X○...Digital control oscillator.
Claims (1)
体の抑制を行う処理装置と、該処理装置により制御され
る発振器とで構成されるディジタル処理型位相同期発振
器において、該処理装置が該入力の断の場合に断以前の
位相差データに基いた積分演算を継続することにより、
該発振器の周波数変動の影響を抑圧することを特徴とす
る自走処理方式。1. In a digitally processed phase-locked oscillator that includes a phase comparator that detects a phase difference between input and output, a processing device that suppresses the entire device, and an oscillator that is controlled by the processing device, the processing device In the case of the input disconnection, by continuing the integral calculation based on the phase difference data before the input disconnection,
A free-running processing method characterized by suppressing the influence of frequency fluctuations of the oscillator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63232420A JPH0281518A (en) | 1988-09-19 | 1988-09-19 | Self-running processing system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63232420A JPH0281518A (en) | 1988-09-19 | 1988-09-19 | Self-running processing system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0281518A true JPH0281518A (en) | 1990-03-22 |
Family
ID=16938978
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63232420A Pending JPH0281518A (en) | 1988-09-19 | 1988-09-19 | Self-running processing system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0281518A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010062803A (en) * | 2008-09-03 | 2010-03-18 | Mitsubishi Electric Corp | Data transmission/reception device |
-
1988
- 1988-09-19 JP JP63232420A patent/JPH0281518A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010062803A (en) * | 2008-09-03 | 2010-03-18 | Mitsubishi Electric Corp | Data transmission/reception device |
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