JPH0277954A - Automatic memory rearrangement system - Google Patents

Abstract

PURPOSE:To realize the accesses with continuous address spaces without causing the system breakdown by setting the corresponding bit at a block selection register when an error detecting part detects a trouble of a certain memory block. CONSTITUTION:A block capacity calculating part 22 of a memory control part 2 calculates the capacity of each memory block. A block selecting part 21 decides a specific memory block to receive an access based on the address signal received from a bus master and outputs the decided signals (RAS 0-N) of a vertical address. In case an error detecting part detects a fault of a certain memory block, the corresponding bit is set at the faulty memory block of a block selection register 21. Thus a signal is outputted for invalidation of the memory block, and the part 22 outputs the capacity of the memory block as naught. Then a RAS selecting part 23 skips the faulty memory block to perform the allocation.

Description

[Detailed Description of the Invention] [Summary] To provide a control method that does not affect memory access time and does not require preparation of spare blocks, regarding control when a memory failure occurs in an information processing device. For the purpose of A block capacity calculation unit that calculates the effective capacity and outputs a capacity signal, and a block selection that selects and outputs a memory block that outputs a vertical address determination signal from the address signal on the memory bus and the capacity signal from the block capacity calculation unit. A block control register is set to invalidate a memory block in which a failure has been detected, the memory block is excluded, and the memory blocks are selected and rearranged to form a continuous address space.

[Industrial application field]

The present invention relates to memory rearrangement control in an information processing device, and particularly to an information processing device that separates a memory block in which a failure has occurred and rearranges it so that it has a continuous address space from both software and hardware.

Information processing devices in recent years have come to require large-capacity memories, but as the capacity increases, memory failure rates become a problem. In an apparatus having a large capacity of memory, it is problematic in terms of operation that the system goes down simply due to failure of some memory elements. For this reason, it is necessary to divide the memory into certain blocks and to separate and operate the block containing the failed element.

[Prior Art] The following are typical methods for separating a block in which a failure has occurred.

(11 Memory management unit (hereinafter abbreviated as MMU)
A method of converting addresses (converting logical addresses and physical addresses) using software to create a continuous address space.

(2) A method in which a spare memory block is prepared in advance and connected to the failed block by bank switching.

[Problem to be solved by the invention]

In the conventional method of isolating the faulty blocks mentioned above, (
The method using MMU (1) requires address translation, which slows down memory access, and has the disadvantage that mapping of logical addresses/physical addresses cannot be done freely in the virtual storage system, which is a limitation.

Further, the spare block method (2) causes waste in that unused memory must be installed even when no failure has occurred.

The problem to be solved by the present invention is to provide a memory rearrangement method that eliminates such conventional problems.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle of means for solving the above-mentioned problem.

In the figure, lo, 1+, 12. IN is a memory block divided into fixed capacity units.

Reference numeral 2 denotes a memory control unit, which controls access to the memory using a control signal output from a bus mask (device that has control of the bus) such as a CPU (central processing unit).

2-1 is an error detection section that checks for memory failure.

A block control register 21 outputs a control signal for invalidating a memory block according to the set contents.

22 is a block capacity calculation unit which calculates the effective capacity of each memory block and outputs a capacity signal.

Reference numeral 23 denotes a block selection unit, which generates vertical address determination signals (RASO, RASI, RAS2) from the address signal on the memory bus and the capacity signal from the block capacity calculation unit 22.
, --, --, RASN) is selected and output.

RAS0, RAS1, RAS2. -., RASN is a memory vertical address confirmation signal (a signal indicating the timing at which the vertical address signal should be read).

CAS is a memory lateral address confirmation signal (a signal indicating the timing at which the lateral address signal should be read).

MSO~m is a memory address, and the vertical and horizontal addresses are switched and outputted from the memory control unit 2.

EC is an error check signal.

[For production]

In the present invention, the block capacity calculation unit 22 of the memory control unit 2
calculates the capacity of each memory block, the block selection unit 22 determines which memory block to access based on the address signal from the bus mask, and outputs a vertical address determination signal (RASO to RASN). do.

If there is no failure in all memory sections, memory blocks #O, # are ordered from the one with the smallest address (or the one with the largest address).
1. #2 to #N are allocated consecutively.

When a failure in the memory block formed by the error detection unit 2-1 is detected, bit 7 of the block control register 21 corresponding to the memory block in which the failure has occurred is set.

As a result, a signal is issued to invalidate the memory block, the block capacity calculation unit 22 outputs the capacity of the memory block as zero, and the block selection unit 23 allocates the memory block. For example, if memory block #1 fails, address #0. Assign #2, #3 to #N.

Therefore, overall, the storage capacity is reduced by the large capacity of memory block #1, but even though there is memory that has failed both from the software and the hardware (bus mask), the continuous memory space (address Also, unlike the above-mentioned method using MMU, there is no loss in access time.

〔Example〕

The present invention will be explained in more detail below with reference to embodiments shown in FIGS. 2 and 3.

FIG. 2 is a diagram showing a system configuration of an embodiment of the present invention.

In the figure, 1 is a memory, and memory blocks i o, I I, 12.・-, corresponds to IN.

2 is a memory control section, which is the same as in FIG.

3 is a CPU, which controls the entire system.

A memory management unit (MMU) 4 performs conversion between virtual addresses and physical addresses and other memory management.

5 is a direct memory access control unit (DMAC);
It controls the transfer of data related to memory and input/output devices independently of the operation of PU3.

6 is a hard disk device, and 7 is a floppy disk device.

8 is a display/keyboard, and 9 is a printer.

FIG. 3 is a diagram showing the configuration of a memory control device in an embodiment of the present invention.

In the figure, a block control register 21 is a register that can be controlled by a program, and outputs a control signal (BLKn INH) that disables a specific memory block when set by the program.

22o to 22N are block capacity calculation units for each memory block, which calculate the capacity of each memory block and transmit the RASA3 selection unit/outside 3 quantity signal.

23 is a RAS selection unit, which receives address signals (SAO to SAM) from the bus master and block capacity calculation units 220 to
The RAS signal (Row Add
ress 5trobe, : selects the memory block to which the vertical address confirmation signal is to be output.

230 to 23N are intra-block RAS selection units, and RA
Selection signal of outside SA3 selection section 3 and block capacity calculation section 22
RAS signals within the block are selected/outputted by signals from o to 22N.

24 is a timing control section, which controls switching timings of various signals.

Reference numeral 25 denotes a memory address generation unit, which divides the address signals SAO to SAM from the bus mask into vertical (Row) addresses and horizontal (Colus+n) addresses to generate memory addresses (MAO to MAm).

RPRYOO, RPRYO1~RPRYnO, RPRY
nl is a capacity notification signal from each memory block,
In FIG. 4, each memory and block are shown with two wires, but the number can be varied depending on the type of memory. For example, when there are two, four types of memory mounting states can be represented as shown in Table 1.

RASOO, RASOL, RAS02, RAS03~
RASnO, RASnl.

RASn2. RASn3 is the memory selection signal RA
These are S signals, and four signals are allocated to each memory block. In this example, 2 Mbytes are controlled per RAS signal. Therefore, for the capacities of 2M bytes, 4M bytes, and 8M bytes indicated by the RPRY signal (capacity notification signal), RAS is applied to 1, 2, and 4 lines, respectively.
A signal is output.

Table 1 shows an example of memory capacity expression using capacity notification signals.
1 Table This memory control device accesses all memory during initial diagnosis (self-test before normal operation).

At this time, memory block #0 to memory block #4
Addresses are allocated consecutively in the order of N. The memory block in which a failure was detected in this memory test is stored, and after the test is completed, the bit of the corresponding memory block X is sent to the block control register. As a result, only the BLKxlNH signal of the corresponding memory block X becomes "0", and the RPRYxO and RPRYxl signals are cleared to 0, 0 by the AND gate of the block capacity calculation unit #X. Therefore, the corresponding memory section is recognized as having no memory installed, and is not selected by the RAS selection section.

As a result, this memory block #X is separated from the address space.

In this embodiment, a failure was detected through initial diagnosis and the failed block was isolated by register setting. However, a failure processing program is provided, and when a failure occurs, the memory contents can be transferred to a magnetic storage device or the like as needed. Alternatively, the faulty block may be separated after being evacuated to the previous location.

In another embodiment of the invention, initial diagnosis is performed by hardware and register setting is performed by hardware.

〔Effect of the invention〕

As explained above, according to the present invention, even if a part of a memory element fails, the system can be accessed as a continuous address space both in terms of software and hardware, without causing system downtime, and the access time can be reduced. Since no loss occurs and no spare memory is required, the system has the effect of improving system reliability at high speed and at low cost.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the principle of the invention, FIG. 2 is a diagram showing a system configuration of an embodiment of the invention, and FIG. 3 is a diagram showing the configuration of a memory control section according to an embodiment of the invention. be. In the drawings, l is memory, io, I 1.12. -+ IN is a memory block, 2 is a memory control unit, 3 is a CPU (central processing unit), 4 is an MMU (memory management unit), 5 is a direct memory access control unit (DMAC), 6 is a hard disk device, 7 is a Floppy disk device, 8 display/keyboard, 9 printer, 2
1 is a block control register, 22, 22o to 22m are block capacity calculation units, Ryu 23 is an RA'S selection unit, 230 to 23N are intra-block RAS selection units, 24 is a timing control unit, 25 is a memory address generation unit, RPRYOO ~RPRYnl is the capacity notification signal, RASO
O~RAS4t3 is the RAS signal (vertical address confirmation signal), CAS is the horizontal address confirmation signal, SAO-M is the address signal on the bus, 〇~m is the memory address, BLKnlNH is the memory block invalidation signal , EC are error check signals, respectively. Figure 1 shows the structure of the present invention. Figure 2 shows the system configuration of the practical reward 11 of the present invention.
Figure 3 is a diagram showing the configuration of the memory control section in the Ichisho i9+1 of the present invention.

Claims (1)

[Claims] Memory blocks divided into fixed capacity units (1_0, 1_
1, 1_2, ..., 1_N), a block control register (21) outputs a control signal to invalidate the memory block according to set contents; A block capacity calculation unit (22) calculates the effective capacity of each memory block and outputs a capacity signal, and a vertical address determination signal ( RAS0, RAS1
, RAS2, . . . , RASN);
The block control register (21) is set to invalidate a memory block in which a failure has been detected, the memory block is excluded, and the memory blocks are selected and rearranged to form a continuous address space. An automatic memory reordering method characterized by: