JPH0277791A - Level display device - Google Patents

Abstract

PURPOSE:To easily read a peak level value by increasing display data at a specific period T1 when input data is larger than the display data by a display data output means or decreasing the display data at a specific period T2 larger than the period T1 when smaller according to the comparison result of a comparing means. CONSTITUTION:The principal part of the level display device consists of a comparing circuit 6, the up-down counter 7, a dot converting circuit 8, a display part 10, AND circuits 11, 12, and 14, a delay circuit 13, a counter clock generating circuit 15, frequency dividing circuits 16 and 17, etc. Consequently, when the input data increases, the display data increases at the period of a up clock CK1 until the display data coincides with the input data and when the input data decreases, the display data decreases at the period of a down clock CK2 until the display data coincides with the input data. For the purpose, the up time and decay time are set freely by varying the periods of the clocks CK1 and CK2 and the peak level value is easily read.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a level display device that displays the signal level of an audio signal or the like.

Prior Art As a signal level display device used in audio equipment such as tape recorders, a plurality of light emitting elements are arranged in a line and the light emitting elements are selectively emitted in a bar graph shape according to the input level. something is known. Digital recording and playback devices such as DAT have a wide dynamic range and are often thought to be easier to set recording levels than analog recording, but in reality, quantization distortion occurs at low levels.
It exhibits the best SN ratio and distortion characteristics near the maximum level, and the distortion increases rapidly when the level is exceeded.
It is necessary to monitor the level setting more carefully than with analog recording. However, in a digital recording/reproducing device, the signal itself is digitized, so if this digital signal is used, accurate level display is possible. For example, reference may be made to the level display device described in Japanese Patent Publication No. 57-34585 shown in FIG. This level display device includes a plurality of 6 dB interval display elements 201L to 2 for Lch and Rch coupled to a plurality of transmission lines 23B to 125B at 6 clB intervals of linearly quantized digital signals, respectively.
11L and 201R to 211R and transmission line 23B to
Display elements 20OL and 20OR for Lch and Rch that are coupled to 73B and display the maximum value (OdB), and intermediate level display elements 212L to 216L and 212R to 216R for Lch and Rch that display between display elements at 6 dB intervals.
It is comprised of logic circuits 217 to 221, etc., which generate an output to bring the intermediate level display element into a display state.

<Problem to be solved by the invention> This conventional level display device accurately follows the input digital signal and calculates the attack time (rise time).
Because the display displays peak levels with zero decay time, the display flickers and becomes difficult to read, especially when rapidly sampled data is input due to its high-speed response.

As a final measure to overcome this drawback, instead of directly inputting the digital signal in the digital recording and reproducing device, an A/D converter for the level display device is provided, and the analog signal of the D/A converter in the digital recording and reproducing device is installed. output from this A/
A again at a lower sampling frequency by D converter
It is conceivable to perform A/D conversion and input and display this digital signal, but it is possible to input the A/D converter and its peripheral circuits (
(sampling and hold circuit, etc.), which leads to an increase in cost. Also in this case, the display is still not easy to read because it is either Decay time or Cero.

When setting the level, it is important to monitor the rising curve and peak level of the input level, but it is not so necessary to strictly monitor the falling curve.When setting the input level, it is important to monitor the falling curve slowly. It is desirable to make it easy to read.

<Means for Solving the Problems> The present invention was devised to solve the above problems, and includes a display data output means for outputting display data, a level display means for displaying a level based on the display data, and an input signal. The comparison means compares input data indicating the level with display data and outputs a signal indicating the comparison result.

<Function> Based on the signal indicating the comparison result outputted from the comparing means, the display data output means outputs the output signal at a predetermined period (T1) when the input data is larger than the display data, and at a predetermined period (T1) when the input data is smaller than the display data. Display data that goes down at a predetermined cycle (T2) larger than the cycle (T1) is output.

<Embodiment> An embodiment of a level display device according to the present invention will be described with reference to the block diagram of FIG.

A digital signal consisting of 16 bits of serial data represented by a 2'S concomitant code supplied from input terminal l at predetermined intervals is input to the value conversion circuit 2 from the MSB (the most significant of the digital input). 23B-LSB (the least significant bit of the digital input) is inverted and converted to data indicating an absolute value only when the bit is high.This data is further converted to 16-bit parallel data in the shift register 3. 23B-123B of this data is sent to the LOG conversion circuit 4.

This LOG conversion circuit 4 is shown in detail in FIG. 2, and converts dot data corresponding to the display levels (dB) of a total of 31 display elements (not shown) ranging from OdB to -60 dB of the display section 10, which will be described later. D3. It outputs ~D1, 23B-
Since each input signal of 123B is linearly quantized, dot data D25 corresponding to the display level at 6dB intervals is generated.
．． D19. DI4゜D1□, Ds, D? ,
Ds, D3. Other dot data are formed by directly forming D 2 and D + and by performing logical product of a plurality of input signals using an AND circuit.

For example, '1100100' indicates that the input signal is approximately -2 dB.
0000'', the result is -2d by ANDing A and B.
Dot data D2 corresponding to display element B. ga pa ■】″
'. At this time, the lower dot data DI on the circuit
9, D9 is also "H", but this dot data D1. ~The 32-dot to 5-bit conversion circuit 5 that inputs D1 is configured to convert into 5-bit data ('11101' in this case) based on the most significant dot data that has become H'', so there is no problem. .

Dot data D, 1~ output from the LOG conversion circuit 4
D1 is converted into dot data D3. by the 32-bit 15-bit conversion circuit 3. is converted into 5-bit data with a maximum value of "11111" when is 'H', and is supplied to one input side of the comparator circuit 6.Hereinafter, this 5-bit data will be referred to as input data A. Note that the lowest dot data D of the 32-dot 15-bit conversion circuit 5 is always “L”.
It is said that

On the other hand, a 5-bit up/down counter 7 is provided, and the count value of this counter 7 is supplied to the other input side of the comparator circuit 6, and is again converted to a display element by a 5-bit/32-dot conversion circuit 8. The dot data H3, -H0 of 32 dots are then supplied to the lower dot control circuit 9. Hereinafter, the count value of the counter 7 will be referred to as display data B. The lower dot control circuit 9 has data 113□~H1
All of the lower dot data below the dot data that has become "H" is converted to "H", and this converted data is supplied with 3 and 1 to the display unit IO, and a bar graph display is performed. .In addition, the display section 10 displays data from 1 to Ko.
32 display elements (not shown) respectively corresponding to the
Since the lowest input data Ko is always set to 'H', the -■ display element (not shown) is always lit.

Further, the comparison circuit 6 compares the input data A and the display data B, and outputs a signal S1 which becomes "H" when A)B.
is supplied to one side of ANDl 2, and when A (B, 'H''
The gate signal S2 is supplied directly and via the delay circuit 13 to ANDII. At the time of 8-B, the gate signals S, , S2 outputted from the comparator circuit 6 are both set to "L". Also, AND11 connects the gate signal S3 to ANDl.
Supply to one side of 4. Note that the delay time of the delay circuit 13 is set to a predetermined time T.

The counter clock generation circuit 15 has a clock C of a predetermined period.
This clock CK is frequency-divided by a frequency division ratio N times by the frequency dividing circuit 16, and then supplied to the count-up terminal UP of the counter 7 as an up-clock CK through the other side of ANDl2.

Further, the clock CK is divided by 2N times by the frequency dividing circuit 17, and then passed through the other side of ANDl 4 to the down clock C.
It is supplied to the countdown terminal DOWN of the counter 7 as K2.

Next, the operation of the above configuration will be explained with reference to FIG.

Time t. Input data A'' indicated by the dashed line -
When "00001" is input, the gate signals S + and S2 output from the comparator circuit 6 become "H" by comparison with the display data B "00000" shown by the solid line.
, becomes "L". At this time, the gate signal S is ANDl
1 and the delay circuit 13 do not affect the falling edge, so the signal becomes "H" immediately. Therefore, the up clock CK1 is supplied to the counter 7 and it starts counting up.

Note that the value inside "P" indicates 5-bit binary data.After that, input data A is input at a predetermined cycle, but since input data A continues to exceed display data B, gate signal SI maintains "H", the counter 7 continues to count up at the cycle of the up clock CK, and the display section I
A rapid increase in input level is displayed at O.

Next, input data A starts to fall, and at time t, input data A'''01001'' changes to display data B'''0101.
When the gate signals S1 and S2 become smaller than 0'', respectively.
L"', "H".Here, the gate signal S2 is AND
II and the delay circuit 13 for a predetermined time T, and therefore neither the up clock CK nor the down clock CK2 is supplied to the counter 7 during this period, so the count value of the counter 7 remains unchanged for the predetermined time T. Only the display data "01010" is held.

At time t2, after the predetermined time T has elapsed, the gate signal S
, or 'H'', and the non-counter 7 outputs the down clock CK.
2 and start the countdown. From then on, the state in which input data A is lower than display data B continues, so
Gate signal S2. The counters S3 hold L''' and 'H'' respectively, and the counter 7 continues to count down at the cycle of the down clock CK, which is set to twice the cycle of the up clock CK. A decrease in the input level is displayed.

When input data A "01001" is input at time L3, gate signal 31. S2 and S3 are again IIH"', "L" and L'", respectively.

Thereafter, time t. - J counter 7 as well as between tl
continues to count up, and a rapid increase in the input level is displayed on the display section IO.

Then, the input data A starts to fall, and at time [, the input data A "11001" becomes the display data B "11010".
"When the gate signals S1 and S2 become "L-", the gate signals S1 and S2 become "L-
'I]' However, since the signal S3 from Goo 1 maintains 'L' for the predetermined time T as described above, the count value of the counter 7 does not change and the display data B'110
10'' is maintained for a predetermined time T.

When the predetermined time T elapses and time L5 arrives, the gate signal S
3 becomes "H", then input level A becomes display level B
The counter 7 continues to count down until the input level exceeds the input level, and the slow decline in the input level is displayed on the display section IO.

In this way, when input data A rises, display data B
The display data B rises at the cycle of the up clock CK until it matches input data A, and when the input data A falls, the display data B rises at the cycle of the up clock C until it matches input data A.
Since it falls at the cycle of K2, the attack time and decay time are respectively up-clock CK, down-clock c
It can be freely set by changing the period of K2. Furthermore, since the display data B is held for a predetermined time T when the display data B changes from rising to falling, the peak level value thereof becomes easier to read.

In Figure 3, the peak levels of input data A and display data B are different, but by setting the cycle of upcrop clock CK shorter, display data B can more accurately follow the rise of input data A. , the peak level of these data can be made substantially concave.

Next, another embodiment of the level display device according to the present invention will be explained in the fourth embodiment.
This will be explained in detail with reference to FIGS. This embodiment is suitable for displaying the level of an input digital signal that is subjected to LR time division processing at a predetermined period. In these drawings, the same parts as in FIG. 1 are designated by the same reference numerals, and their explanations will be omitted.

The gate signal St from the comparator circuit 6 is sent to the data terminal of the D-type flip 70 tube (hereinafter abbreviated as D-FF) 18.20.
Further, the gate signal S2 is supplied to the data terminals of the D-FFIs 9 and 21, respectively. The LR clock signal (hereinafter abbreviated as LRCK) and the word clock signal (hereinafter abbreviated as WC) output from the control clock generation circuit 22 are logically ANDed by the AND 23 to become the clock signal S5 of the D-FFs 20 and 21. In addition, L to "'L" and "R" of LRCK.
Since input data A of ch and input data A of Rch correspond to each other, and WC has twice the frequency of LRCK, the tarok signal S5 rises when it is input data A of Rch (see Figure 6). , D-FF20.21 is husband h
Gate signals S, , S2 indicating the comparison result between input data A and display data B of Rch are held. In addition, L R is inverted by an inverter (hereinafter abbreviated as INV)
CK and WC are ANDed by AND25, and D-
The clock signal S of FF18 and 19 rises when the clock signal S4 or the input data A of Lch is input (see Fig. 6), and D-FF18 and 19 respectively become Lch.
Gate signals S, , S2 indicating the comparison result between input data A and display data B are held. Also, D-FF l 8
The Q output of AND I 2 L becomes the gate signal S6, and the Q output (gate signal sy) of the D-FF 19 and the Q output passed through the delay circuit 13L are logically ANDed by ANDIIL, and only at the rising edge is a predetermined time T. It is delayed and becomes the AND 14 L gate signal S8. In addition, the Q output of D-FF20 becomes the gate signal S of AND l 2 H, and the Q output (gate) of D-FF21 becomes the gate signal S.
+o) and the Q output through the delay circuit 13R or ANDI
A logical product is calculated by IR, and only the rise of the logical product is delayed by a predetermined time T, and the AND l 4 R gate signal S
It becomes ll. Also, the clock from the frequency dividing circuit 16 is AND
Lch up clock LC through 12L and 12R respectively
Counter 7 as K,,Rch up clock RCK,
It is supplied to the count up terminals r--UP and R-UP of L and 7R. Also, the tarok from the frequency dividing circuit 17 is AND
141-. Through 14R, each Lch down clock I
-CK, Rch down clock RCK2 as countdown terminals L-DOWN, R-D of counters 7L, 7R
OWN. Further, each count value of the counters 7L and 7R is supplied to the switch circuit 26.
6 corresponds to input data A, when LRCK is "L", the count value of counter 7L is
``'', the counter value of the counter 7R is supplied to the comparison circuit 6 and the latch circuit 27 as display data B, respectively.

The latch circuit 27 alternately latches the Lch and Rch while thinning out the display data B based on the latch clock (hereinafter abbreviated as LATCH) output from the control clock generation circuit 22. The display data B latched by the latch circuit 27 is converted to 32 pixels by the 5 hit/32 dot conversion circuit 8.
1-soto data, and is further converted by the lower dot control circuit 9 into lower dot data [・ or H'', L c h
The signal is supplied to a display section 28 that includes a group of display elements for Rch and Rch. As shown in detail in FIG. 5, this display section 28 has 32 display elements for Lch and Rch.
Display element group 29L for.

29R, an Lch drive signal and an Rch drive signal (hereinafter referred to as L-DRIVE) which are output from the control clock generation circuit 22 as "H" for a certain period of time at a certain period.

R-DRIVE) based on each display element group 29L,
From positive voltage application circuits 30L and 30R that apply a positive voltage to 29R through a resistor, respectively, and a switching circuit group 31 that controls each display element on and off based on the signal from the lower dot control circuit 9. It is configured.

The operation will be explained below with reference to the timing chart of FIG.

Note that this timing chart is based on Lch input data A
(L1), (L2)...(L37) and R
Channel input data A (R2), (R3)...
(R39) is the corresponding Lch display data table +
), (l□)...-(+37) and Rch display data B (r 2), (r 3)... (r 3
．． ), and other input data A is shown as being smaller than display data B.

At time T1, Lch input data A (L1) becomes Lch
The gate signals S, S2 output from the comparator circuit 6 are ``H'' and ``, respectively.
becomes L'''. At time T2, the clock signal S4 rises, and the gate signal S6 output from the D-FFs 18 and 19
．． S becomes "H" and "L" respectively. Here, the gate signal S8 becomes "L" immediately because ANDllL and the delay circuit 13L do not affect the rising edge. Therefore, the counter 7L is supplied with the Lch up clock LCK, and its count value increases. After that, the Lch input data A continues to rise and the Lch display display data continues to be large, so that the gate signal S6. The counter 7L continues to count up without changing the states of S, , S, and thus the Lch display data B rapidly increases. At time T3, LATCH rises, the latch circuit 27 latches the I-ch display data B (l□), and this display data B (12) is transferred to the 5-pin 1-/32 dot conversion circuit 8. The lower driver 1-control circuit 9 converts the data into dot data suitable for display, and the switching circuit group 31 of the display section 28 turns on the display elements of both channels corresponding to this data. Next, from time T, L-DRIV
When E or 'H' becomes 1.m, the positive voltage application circuit 3OL applies a positive voltage to the display element group 29L, and only the display elements of the Lch that are ON-controlled are turned on. Also, at time T4, the Rch input data A ( R2) also Rch display data B
(r2), so the gate signal S + ,
S2 becomes "H" and "L" respectively. Time T
, the clock signal S5 rises, and the D-FF20,2
+ gate signal S9. SIo is “H”
"," becomes "L".Here, the gate signal Sll becomes "A".
Since NDIIR and the delay circuit 13R do not affect the falling edge, the signal becomes 'L' immediately. Therefore, counter 7R
is supplied with the Rch up clock RCKI, and its counter I-value increases. Since the Rch input data continues to exceed the Rch display display data, the states of the gate signals Ss, Szo, and S++ do not change, and the counter 7R continues to increase. rise to

Further, at time T6, 1-DRIVE becomes L'', so the Lch display element that is controlled to be on turns off.

Also, at time T7, LATCH rises, and latch circuit 2
7 latches the Rch display data 1), and this display data B (r4) is sent to the 5-bit to 32-dot conversion circuit 8.
The lower dot control circuit 9 generates dot data suitable for display, and the switching circuit group 31 of the display section 28 turns on the display elements of both channels corresponding to this data. Next, from time T8, R-DRIVE becomes "H"', the positive voltage application circuit 30R applies a positive voltage to the display element group 29R, and only the R ch display element that is controlled to be turned on lights up. At time T, R-DRIVE
When the display element is turned on (7), the display element for the Rch that is on is turned off.

Incidentally, since displaying all the display data B in Lch and Rch in a time-division manner requires a very short cycle, the positive voltage application circuits 30L and 30R are required to have high-speed response.

In this embodiment, the display data B is thinned out by the latch circuit 27 and launched alternately on each channel to lengthen the period of time-division display. Achieves split display. In this case, all of the display data B will not be displayed, but there is almost no problem in practice.

After this, the Lch input data A (L3M) rapidly decreases and at time T1°, the Lch input data A (L3M)
Since it is smaller than display data B (lsa), time T1
1, gate signal S6. S y is “L”,
It becomes “H”. Here, the gate signal S8 is held at "L" for a predetermined time T from time T1 to T4 by ANDllL and the delay circuit 13L.
ch Azzo Clock LCK.

Since none of the Lch down clock LCK2 is supplied, the data value remains the same for a predetermined time T after the Lch display data B (13g). Therefore, the display time of the peak level value becomes longer and reading becomes easier. Also R
The channel input data A also rapidly decreases, and at time T1□, the Rch input data A (R, 1) also becomes smaller than the Rch display data (ao), and at time T1. and the gate signal S,
, S2 become "L" and "H", respectively. Here, the gate signal Sll is kept "L" for a predetermined time T from time T1. to time T8. by ANDi IR and the delay circuit 13R. is Rch up clock RCK,,
Since none of the Rch down clock RCK2 is supplied, the predetermined period of time after the Rch display data B (r4o) is
During F, the data values are the same.

Time T1. At time T14, when a predetermined time T has elapsed, the gate signal S8 becomes "H"', and the counter 7L shows L.
The ch town clock L CK2 is supplied and its count value decreases. After that, the Lch input data A drops rapidly, so the gate signal S6. S.

The countdown of the counter 7L continues without any change in each state of S8, so that the Lch display data B slowly decreases. Also, time T1. when a predetermined time T has elapsed from time T13. Then, the gate signal S11 becomes "H", the Rch down clock RCK2 is also supplied to the counter 7R, and its count value decreases. Since the Rch input data drops rapidly thereafter, the gate signal S9. Sl. , Sl+ do not change, and the counter 7R continues to count down, so that the Rch display data slowly decreases.

In the above embodiment, for convenience of explanation, LATCH,
L-DRIVE, R-DRIVE, and the predetermined time T are set appropriately, but in reality the sampling frequency is 48k.
In the case of Hz, LRCK=48kHz, WC-96kl (
z, up clock LCK1+ RCK+=375kHz
z, down clock LCK2. RCK2=300H2,
The predetermined time T = about 50 msec is selected, and the predetermined time is about 10 m.
If display data B is latched LR alternately every 5 ec and time-division display is performed, a visually favorable result can be obtained.

The present invention is not limited to the above embodiments, but can take various forms.

For example, FIG. 7 shows a case where an up/down counter 29 having a clock terminal CK and an up/down mode control terminal MODE is used instead of the uptown counter 7 having an up terminal UP and a down terminal DOWN in FIG. . In addition, the gate signal S3 is converted into a one-shot multi-by-flake (hereinafter abbreviated as MM) 30. INV31
, 32°ANDII. Note that the same parts as in FIG. 1 are denoted by the same reference numerals, and their explanation will be omitted.

The current value of the counter 29 is supplied to the other input of the comparison circuit 6 and to the 5-hin 1-/32-dot conversion circuit 8. The comparison circuit 6 connects the gate signal S1 to one of ANDl2 and U.
Counter 29 up/town mode i/control terminal MOD
E, and the gate I/signal S2 is passed through MM30 to AN.
AND to one side of DII, also through INV3], 32
II. By the way, is MM30 that input?
It is configured such that when the output goes from "L" to "H", the output is held at "L" for a predetermined time T.
N+) 11 supplies the gate signal S3 to one side of ANDI 4. Note that the gate signal S is controlled by INV31 and INV32.
By slightly delaying 2, the gate signal S2 or "H"
This prevents the clock signal S3 from becoming H" at the moment when the output of ANDl 2 (up clock signal S3
) The output of ANDl 4 (town clock CK2) is 0.
It is supplied to the clock terminal CK of the counter 29 through R33. In this configuration, for example, one signal S1
When the value becomes 'H'', the counter 29 enters the up mode, and the up clock CK is input to the counter 2 through ○R33.
9 and starts counting up. Also, when the gate signal S2 becomes "H", the gate signal S1 naturally becomes "H".
The counter 29 goes into the down mode because it becomes L''.The gate I/signal S3 is MM30.
Its rise is delayed by a predetermined time T by NDll. When the predetermined time T has elapsed and the signal S3 becomes high, the counter 29 registers the town clock CK2 as 0R.
33 and starts the countdown. In the above configuration, the gate signal S2 is sent to the up/down counter 29 via INV instead of the gate signal S1.
It is clear that the signal may also be sent to the down mode control terminal MODE.

Further, FIG. 8 shows a case where an up/down counter 29 having a clock terminal CK and an up/down mode control terminal MODE is used as in FIG. 7, and a frequency dividing circuit 34 whose frequency division ratio can be controlled is further used.

Components that are the same as those in FIGS. 1 and 7 are designated by the same reference numerals, and their explanations will be omitted.

The counter clock generation circuit 15 has a clock C of a predetermined period.
Ko is generated, and after being frequency-divided by a frequency divider circuit 34 whose frequency division ratio can be controlled, this tarlock CKo is supplied to one of AND12.14. The frequency division ratio of the frequency dividing circuit 34 is controlled by the signal S1, and when the signal S1 becomes ``H'', the frequency division ratio becomes N times, and when it becomes ``L'', the frequency division ratio becomes 2N times. In the configuration, for example, if the gate signal S1
When it reaches "H", the counter 29 goes into up mode,
The frequency dividing circuit 34 divides the clock CKo by N times. Therefore, the up clock CK in the counter 29 is 0R33.
is supplied through and starts counting up. Also,
When the gate signal S2 becomes "H", the gate signal S, or'
Since the clock signal S3 becomes "H", the counter 29 goes into town mode, and the frequency divider circuit 34 divides the clock CK by 2N times. Town clock CK2 is 0R
33 and starts the countdown. Note that in the above configuration, a gate signal is used instead of the gate signal S1.
The gate signal S2 may be sent to the up/down mode control terminal MODE of the counter 29 via INV, or the gate signal S2 may be sent to the control terminal of the frequency divider circuit 34 via TNV instead of the gate signal S1. The good news is obvious.

Although the configurations in FIGS. 7 and 8 have been described as modifications of FIG. 1, it is clear that similar modifications can be made in FIG. 4 as well. Also, ANDII in FIG. 1 and the delay circuit 13 may be omitted and the gate signal S2 may be directly supplied to ANDI4, or
R, delay circuits 13L and 13R are omitted, and gate signal S7
+SIO can also be directly supplied to AND14L and 14R, respectively.

Further, if it is desired to include a peak hold circuit in the level display device of the present invention, for example,
The binary code in the peak hold circuit described in Publication No. 59 is used as display data B, and the peak value of this display data B is bolded, and the peak value and peak hold value are switched at the same time or one of them on the display section 10.28. It can be displayed.

<Effects of the Invention> According to the level display device of the present invention, its attack time and decay time can be set arbitrarily,
In particular, it is possible to make reading easier by slowing down the display level.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a level display device according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing details of its LOG conversion circuit, FIG. 3 is a diagram for explaining its operation, and FIG. A block diagram showing a level display device according to another embodiment of the present invention, FIG. 5 is a circuit diagram showing details of the display section,
Figure 6(a). (b) is a timing chart for the various signals, FIGS. 7 and 8 are block diagrams of main parts showing still further embodiments, and FIG. 9 is a circuit diagram showing a conventional level display device. Explanation of symbols-3! ]-6: Comparison circuit 7.7L, 7R, 29 near block down counter 8: 5-bit/32-dot conversion circuit 1
0.28: Display section 11, 12° 12L, 12R, 1
4, 14L, 14R, 23°25+AND 13:
Delay circuit 15: Counter clock generator circuit 16
, 17.34: Frequency divider circuit 18.19, 20, 21:
I)-FF22: Clock generation circuit 24, 31.3
2: INV 26: Switch circuit 27; Latch circuit 30: One shot]・Multi-vibrator 33
:OR

Claims (10)

[Claims] (1) A display data output means for outputting display data, a level display means for displaying a level based on the display data, and comparing the input data indicating the level of the input signal with the display data, and displaying the comparison result. The display data output means outputs a signal representing the comparison result, and the display data output means outputs a signal representing the comparison result at a predetermined period (T_1) when the input data is larger than the display data, based on the signal representing the comparison result output from the comparison means. and when the input data is smaller than the display data, the predetermined cycle (T_1) is larger than the predetermined cycle (T_1).
2) A level display device characterized in that it outputs display data that goes down. (2) A LOG conversion circuit that converts a linearly quantized digital signal into first dot data corresponding to the levels indicated by a plurality of display elements, and a dot/log conversion circuit that converts the first dot data into N-bit input data. a bit conversion circuit; a display data output means for outputting display data; a comparison means for comparing the input data and the display data and outputting a signal indicating the comparison result; a bit/dot conversion circuit that converts only the corresponding dot into second dot data that is in a second state different from the first state of other dots; and a dot in the second dot data that is in the second state. a lower dot control circuit that puts the lower dots in the second state, respectively; The display unit includes a display section including the plurality of display elements that display different display states, and the display data output means determines whether the input data is better than the display data based on a signal indicating a comparison result output from the comparison means. When the input data is larger than the display data, it is increased at a predetermined period (T_1), and when the input data is smaller than the display data, it is increased at a predetermined period (T_1) that is larger than the predetermined period (T_1).
2) A level display device characterized in that it outputs display data that goes down. (3) The display data output means includes a counter (7) having a count-up terminal and a count-down terminal and outputting the display data, a first clock of the predetermined period (T_1) and the predetermined period (T_2). clock generating means (15, 16, 17) for generating a second clock; and a clock generating means (15, 16, 17) for generating a second clock of the first clock when the input data is larger than the display data based on a signal indicating a comparison result outputted from the comparing means. a first clock supply means (12) for supplying a count-up terminal of the counter; 3. A level display device according to claim 1, further comprising second clock supply means (14) for supplying a clock to a countdown terminal of said counter. (4) The display data output means has a clock input terminal and an up/down mode control terminal, and a counter (29) that outputs the display data, a first clock of the predetermined period (T_1) and the predetermined clock. Based on the clock generation means (15, 16, 17) that generates a second clock of period (T_2) and the signal indicating the comparison result outputted from the comparison means, when the input data is larger than the display data, a first clock supply means (12) for supplying the first clock to a clock input terminal of the counter; and when the input data is smaller than the display data based on a signal indicating a comparison result output from the comparison means; and a second clock supply means (14) for supplying the second clock to a clock input terminal of the counter, the counter having a second clock supplying means (14) for supplying the second clock to a clock input terminal of the counter, the counter having a second clock supplying means (14) for supplying the second clock to a clock input terminal of the counter, the counter having a second clock supplying means (14) for supplying the second clock to a clock input terminal of the counter. 2. The device according to claim 1, wherein a signal indicating a result is supplied so that the up mode is set when the input data is greater than the display data, and the down mode is set when the input data is smaller than the display data. Level display device according to item 2. (5) The display data output means has a clock input terminal and an up/down mode control terminal, and a counter (29) that outputs the display data, and a signal indicating the comparison result output from the comparison means. Based on the comparison, clock generating means (15, 34) generates the first clock when the input data is larger than the display data and generates the second clock when the input data is smaller than the display data; a first clock supply means for supplying a first clock of the predetermined period (T_1) to a clock input terminal of the counter when the input data is greater than the display data, based on a signal indicating a comparison result output from the means; (12), and based on the signal indicating the comparison result output from the comparison means, when the input data is smaller than the display data, the second clock of the predetermined period (T_2) is input to the clock input terminal of the counter. and a second clock supply means (14) for supplying a second clock, and the counter receives a signal indicating the comparison result outputted from the comparison means to the up/down mode control terminal of the counter, 3. The level display device according to claim 1, wherein the level display device enters the up mode when the data is larger than the display data, and enters the down mode when the input data is smaller than the display data. (6) A signal conversion circuit in which the display data output means changes the state of the signal output from the comparison means, which changes its state when the input data becomes smaller than the display data, for a predetermined period of time ( 11, 13 or 11, 3
3. The level display device according to claim 1, characterized in that the level display device has the following values: 0, 31, 32). (7) A display data output means for alternately outputting Lch display data and Rch display data, an Lch display element group, and an Rch display element group.
a level display means including a group of channel display elements, in which the Lch display element group is alternately drive-controlled based on the Lch display data and the Rch display element group is alternately driven and controlled based on the Rch display data; Lch input; Comparison that alternately compares the Lch input data indicating the level of the signal and the above Lch display data, and the Rch input data indicating the level of the Rch input signal and the above Rch display data, and outputs a signal indicating the comparison result. and the display data output means outputs a predetermined period ((
T_1), and the above Lch input data becomes above Lc.
If it is smaller than h display data, the specified period (T_1)
The Lch display data goes down at a larger predetermined cycle (T_2), and when the Rch input data is larger than the Rch display data, it goes up at a predetermined cycle (T_1), and when the Rch input data is smaller than the Rch display data, it goes up. A level display device that alternately outputs Rch display data that goes down at a predetermined cycle (T_2) that is larger than a predetermined cycle (T_1). (8) A digital signal that has been linearly quantized and in which Lch data and Rch data are alternately supplied at every predetermined cycle is
Lch first dot data and Rc corresponding to the levels indicated by each display element of the ch display element group and the Rch display element group, respectively.
A LOG conversion circuit that alternately converts the Lch first dot data and Rch first dot data into N-bit Lch input data and N-bit Rch input data, respectively. a dot/bit conversion circuit that outputs the Lch display data and the Rch display data alternately, and a display data output means that outputs the Lch display data and the Rch display data alternately; and comparing means for alternately comparing the Lch display data and the Rch display data, respectively, and outputting a signal indicating the comparison results, and comparing the Lch display data and the Rch display data, respectively, wherein only the dot corresponding to the display data is different from the first state of the other dots. a bit/dot conversion circuit that alternately converts Lch second dot data and Rch second dot data that are in a second state; and a bit/dot conversion circuit that is lower than the dot that is in the second state in the Lch second dot data. a lower dot control circuit that alternately converts the dots in the second state to the second state, and the dots lower than the dots in the second state in the Rch second dot data to the second state. and the Lch display element group and the Rch display element group corresponding to each dot output from the lower dot control circuit and having different display states corresponding to the first and second states of the dot, respectively.
and a display section in which the Lch display element group is alternately drive-controlled based on the Lch display data and the Rch display element group is alternately drive-controlled based on the Rch display data. When the Lch input data is larger than the Lch display data, the display data output means outputs the Lch input data at a predetermined period (T_1) based on the signal indicating the comparison result outputted from the comparison means. is the above L
When it is smaller than the channel display data, the predetermined period (T_
1) Lch goes down at a larger predetermined period (T_2)
The display data and the Rch input data are the Rch
Rch display data that increases at a predetermined cycle (T_1) when the Rch input data is larger than the display data, and decreases at a predetermined cycle (T_2) that is larger than the predetermined cycle (T_1) when the Rch input data is smaller than the Rch display data;
A level display device characterized by outputting signals alternately. (9) The display data output means has a count up terminal and a count down terminal, and
It has a first counter (7L) that outputs channel display data, a count up terminal and a count down terminal, and R
a second counter (7R) that outputs channel display data; a switch means (26) that alternately outputs the Lch display data and Rch display data in correspondence with the Lch input data and Rch input data; and the above comparison. first holding means for holding a signal outputted from the means and whose state changes when the input data becomes larger than the display data, each time the comparing means compares the Lch input data and the Lch display data; (18
), and the comparison means compares the Rch input data and the Rc
a second holding means (
20) Each time the comparing means compares the Lch input data and the Lch display data, a signal is output from the comparing means and changes its state when the input data becomes smaller than the display data. The third holding means (19
), and the comparison means compares the Rch input data and the Rc
4th holding means (4th holding means (
21); clock generation means (15, 16, 17) for generating the first clock and second clock; and clock generation means (15, 16, 17) for generating the first clock and the second clock; a first clock supply means (12L) for supplying the first clock to the count-up terminal of the second counter; and a first clock supplying the first clock to the count-up terminal of the second counter based on the signal output from the second holding means. supply means (12R); third clock supply means (14L) for supplying the second clock to the countdown terminal of the first counter based on the signal output from the third holding means; and the fourth holding means. and fourth clock supply means (14R) for supplying the second clock to the countdown terminal of the second counter based on the signal output from the means. level indicator. (10) The display data output means further retains the Lch display data and the Rch display data for a predetermined period of time;
The signal output from the third holding means indicating that the Lch input data has become smaller than the Lch display data, and the fourth holding means indicating that the Rch input data has become smaller than the Rch display data. A claim characterized in that the invention comprises a first signal conversion circuit (11L, 13L) and a second signal conversion circuit (11R, 13R), each of which converts a signal output from a signal into a state before the change for a predetermined period of time. Item 9. Level display device according to item 9.