JPH0277683A - Alarm watch - Google Patents

Abstract

PURPOSE:To improve efficiency of detecting alarm time by a method wherein a plurality of alarm time settings consisting of time information starting with month and date units are stored in the sequence of this year and the following year according to month and date information of the current time. CONSTITUTION:An electronic watch is operated by a 8-bit parallel processing micro program control method and consists of a ROM, a RAM 13, an arithmetic unit, etc. The RAM 13 is equipped with a register BD for memorizing the current date, a data memory DM, etc. Schedule data, etc. consisting of date data and message data is stored in a line address region of the memory DM, and each line is equipped with areas f1 to f50 for memorizing the following-year- memorizing flags indicating that data refers to the schedule for the following year. The schedule data memorized in the memory DM is edited and memorized in a specified sequence. When a time correction mode or a schedule write mode is canceled, re-arrangement processing of module data is re-arranged according to the current date and time in the sequence of time series of the respective schedule data, thereby detection of alarm time can be efficiently carried out.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an alarm clock that stores a plurality of alarm times.

[Problems with Prior Art] Conventionally, an alarm clock is known in which a plurality of pieces of alarm time data are stored in a memory and a notification is issued when the alarm time is reached.

In this type of alarm clock, the alarm time is stored in the order of date and time in order to simplify the above-mentioned notification operation or to make it easier to display and confirm the stored alarm time. For example, Japanese Patent Laid-Open No. 54-78175,
The technique is described in Japanese Patent Application Laid-Open No. 57-97488 and the like.

However, as shown in Japanese Patent Application Laid-Open No. 57-97488, if the input alarm time includes the year, month, and day, the order of the date and time is clear and there is no problem. 1 Normal.

In daily life, it is rare to need an alarm time that includes a date that is many years in the future, and such alarm clocks are usually battery-powered and have a lifespan of 2.3 years. Therefore, even if the alarm time is stored many years in the future, the contents will be erased when the battery is replaced. Therefore, it is usually sufficient to simply store the alarm time consisting of the month, day, and hour without inputting the year, and also eliminates the troublesome operation of inputting the year.

However, if the alarm time is set to month, day, hour, and minute without inputting the year, there is a drawback that the alarm time for the following year cannot be set. For example, even if it is October 10th and you enter the month, day, and time with the intention of setting the alarm time for February of the following year, the alarm time for that February will be There is a drawback that the alarm time is not treated as the alarm time for the next year, but as the alarm time for February of the year, which has already passed.

[Purpose of the invention] This invention was made against the background of the above-mentioned circumstances, and its purpose is to store a large number of alarm times consisting of monthly and daily data without inputting the year. To provide an alarm clock that can distinguish between the current year and the next year and efficiently process alarm time detection.

[Summary of the Invention] In order to achieve the above-mentioned object, the present invention compares the date information (month/day information) of the alarm time with the date information of the current time, and calculates the alarm time having date information after the current time. It is determined that the alarm time information is for the current year, and the alarm time having date information before the current time is regarded as the alarm time information for the next year, and is stored in the memory so that the alarm time information for the next year is located after the alarm time information for the current year. This is how it was done.

[Example J Hereinafter, this invention will be specifically described based on an example shown in the drawings. FIG. 2 is an external view of an electronic wristwatch with a schedule function to which the present invention is applied. A keyboard 1 and a display wave W2 are arranged on the front side of the watch case. The keyboard l is provided with various keys that function as alphabet keys, numeric keys, and the like.

In addition, there are push button switches S+ on both sides of the watch case.
S2, S3, and Ss are provided. Here, switch S4 is a page change switch for the schedule function, switch S3 is a mode switch that switches between clock mode and schedule mode, and switch S2 is a correction switch that switches to time correction mode in the clock mode and to schedule writing mode in schedule mode. The mode changeover switch, switch S1, is a correction digit selection switch in the correction mode.

FIG. 3 shows the configuration of the display device 2. As shown in FIG. This display device 2 is constituted by a liquid crystal display device, and a main digital display portion 2A constituted by an eight-digit day-shaped display is provided in its lower display area.

In addition, the upper display area is provided with a sub-digital display section 2B consisting of a four-digit day-shaped display from the left in the figure, a matrix display section 2C consisting of five digits, an AM display, and a PM display. ing.

Next, the circuit configuration of this electronic wristwatch will be explained based on FIG. 1. This electronic wristwatch operates using a microprogram control method with 8-bit parallel processing, and a ROM (read only memory) 11 stores microprograms that control all operations of this electronic wristwatch, and the microinstruction
Outputs F, Do, and NA in parallel. Here, the microinstruction OP is input to the instruction decoder 12, which decodes it and provides it to the R/W input terminal of the RAM (random access memory) 13 as a data read/write command. 14 as an arithmetic instruction. Further, the microinstruction DO is input as address data to the Addr input terminal of the RAM 13 via the data bus, and is also input to the DI2 of the calculation unit 14.
The data is inputted to the input terminal as numerical data, and further inputted to the address control section 15. Further, the microinstruction NA is next address data input to the address control unit 15, and the address data output from the address control unit 15 is applied to the Addr input terminal of the ROMII.

The RAM 13 has a configuration including a numeric register, an arithmetic register, etc., and is used for timekeeping processing, key manual processing, arithmetic processing, etc., and executes data writing and reading operations under the control of the instruction decoder, and the DO output of the RAM 13. The data read from the terminals is applied to the DII input terminal and the DI2 input terminal of the calculation section 14 and is displayed on the display section 17 via the display control section 16. Arithmetic unit 14
executes various calculations according to calculation instructions from the instruction decoder 12, and the calculation result data is stored in the RAM 1.
3 and read into the RAM 13. Further, when executing a judge operation, the calculation unit 14 outputs a signal indicating the presence or absence of data as a result of the operation and a signal indicating the presence or absence of carry generation, and supplies them to the address control unit 15.
Convert the ROMII address. In addition, the address control unit 15 receives a 16Hz signal obtained by dividing the reference clock signal from the oscillator 18 by a frequency dividing circuit 19.
A clock of 16 Hz is input, and according to this 16 Hz signal, the clock process is executed by interrupting once every 1716 seconds. Further, the predetermined frequency signal output from the frequency dividing circuit 19 is given to a timing generator 20, which outputs various timing signals and supplies them to each circuit. Further, the key code output from the key input unit 21 is given to the DI2 input terminal of the calculation unit 14.

FIG. 4 shows the main part of the RAM 13, and the RAM 13 has a storage area in which the user can freely write in clock data and system control data in accordance with key operations. That is, the RAM 13 is provided with a BD register for storing the current date, a BT register for storing the current time, and a data memo 90M. This data memory DM
is capable of storing schedule data for 50 pages corresponding to the row addresses rlJ to "50", and each row address area contains date data for month and day, time data for hour and minute, and messages (schedule contents). ) is stored in the area Ml-Mso corresponding to each row, a message is stored in the area Ml-Mso, date data is stored in the area D+-Dso, and time data is stored in the step T+''Tso. Areas f1 to f that store next year memory flags indicating that the schedule is for the next year.
s.

is provided. Here, the schedule data stored in the data memory DM is edited and stored in a predetermined order. Other RAM 13 includes address register n for specifying the row address of data memory DM, schedule total data count memory N, display page pointer P, flag register Fs, and alarm 0.
An N10FF flag register AL is provided.

[Operation of the Embodiment] Next, the operation of the embodiment will be described with reference to FIGS. 5-10. Here, FIGS. 5 to 8 are flowcharts for explaining the operation, and FIGS. 9 and 1θ are diagrams of display states that change in accordance with switch operations.

First, an overview of the overall operation will be explained with reference to the general flow shown in FIG. When entering this general flow, step TI is executed and the system is in a standby state until there is a request for clock timing or key manual input. Now, when the key code corresponding to the operation key is output from the key human power unit 21, a corresponding key processing program is specified, and key processing and display processing are executed (step T2). When the clock clock of
The current time of the BT register in 3 is updated, and if a carry is obtained as a result, the date of the BD register is updated. When such time counting processing is completed, an alarm processing (step T4) is first performed, and then a display processing (step T5) is performed.

FIG. 6 is a flowchart showing specific details of the key processing and display processing (step T2) shown in FIG. Now, to switch from clock mode to schedule mode and from schedule mode to clock mode, press switch S.
3 is operated, this is detected at step T and the process proceeds to step 712, where the contents of register FS are set to "0".
can be investigated. Here, the register Fs indicates that it is “1”.
” to specify write mode in schedule mode, time correction mode in clock mode, and 0 to specify read mode in schedule mode and normal mode in clock mode. If the flag is to be stored and the mode is schedule read mode or clock normal mode, proceed to step TI3 and step 1.
Mode switching between clock mode and schedule mode is executed, but this mode switching is prohibited in schedule writing mode or time correction mode. Therefore, in the next step THa, the setting mode is determined, and as a result, if it is the clock mode, the time is displayed (step T11), and if it is the schedule mode, the value of the address register n is displayed as the page pointer P. The schedule data of the page indicated by the value of the display page pointer P is read out from the data memory DM and displayed (step TI5, step Tl).
6) e In this case, the address register n contains the primary notification number, that is, the row address of the data memory DM in which the schedule data of the page to be notified next among the schedule data stored in the data memory DM is stored. is set. Therefore, the schedule data to be notified next will be displayed on the display unit 17. Since such an operation is repeated every time the switch S3 is operated, the clock mode and schedule mode are cyclically switched.

9a and 9b show the display states at this time, with FIG. 9a showing the clock mode and FIG. 9b showing the schedule mode.

When the switch S2 is operated in the 1 watch mode, the operation of the switch S2 is determined in step TI8, the setting state of the watch mode is determined in step TI9, and the process proceeds to step T20, and as a result, the contents of the register Fs are set to "0".
When it is, it is rewritten as "1", and when it is "1", it is rewritten as "0" (step 721, step T22).

Therefore, as shown in FIG. 9, when the switch S2 is operated in the normal mode of FIG. 9a, the time adjustment mode of FIG.
Press to return to normal mode.

Here, only when the time adjustment mode is switched to the normal mode with the operation of the switch S2, step T2
Proceeding to step 3, editing processing for rearranging the schedule data is executed.

When such editing processing is completed, or when switching from normal mode to time correction mode is completed, the process proceeds to step T24, where the time is displayed.

On the other hand, if the switch S2 is operated in the schedule mode, this is detected in steps TI8 and TI9, and the same processes as steps 720 to T23 described above (steps 725 to T28) are executed.

Therefore, as shown in FIG. 9, when S2 is operated in the schedule mode read mode shown in FIG. 9, the mode becomes the schedule write mode shown in FIG. 9 d, and when switch S1 is operated in the write mode, the mode returns to the read mode. . Even in this case, only when switching from write mode to read mode is the editing process (step T
28) is executed in the same way as in the above case. When the editing process is finished, the value of address register n (
The next notification number is transferred to the display page pointer P,
The schedule data of the page corresponding to the value of the display page pointer P is displayed (steps T29 and T30) - Next, the operation accompanying the operation of the switch S4 will be described. Note that the switch S4 is operated when changing the displayed page to the next page in the schedule writing mode and reading mode. However.

When the switch S4 is operated, this is detected in step T31, and the process proceeds to step T32, where it is checked whether it is the schedule mode. Here, in the clock mode, the switch S4 is disabled, but in the schedule mode, the processing accompanying the subsequent operation of the switch S4 is executed. That is, first, in step T33, it is determined whether the value of the total data number memory N is "0", that is, whether no data is stored in the data memory DM. As a result, except when no schedule data is stored in the data memory DM, if at least one schedule data is stored, step T3 is executed.
Proceed to g, display page pointer P and total data number memory N
The values of are compared. Now, if the value of the display page pointer P is equal to the total data number memory N, the next step T35
In step , it is determined whether the value of the total data number memory N is "50", that is, whether the data memory DM is in a full state in which 50 pages of data are stored. Here, if it is detected in step T34 that the number of displayed pages is smaller than the total number of scheduled data, the value of the displayed page pointer P is determined because data is continuously stored in the data memory DM. Increment processing that increases +1 (
After step T36) is executed, the schedule data of the page indicated by the value of the display page pointer P is displayed (step T36, step T38). Step T36 is also performed when the data memory DM is not in a full state.
．． Step T3B is executed, but in this case, an empty page is displayed. As a result of the operation of the switch S4, the value of the total page number pointer P is incremented by 1, the step T
If the number of displayed pages becomes larger than the total number of data in 34, or if the number of displayed pages matches the total number of data and the data memory DM is in a full state, ``rl'' is set in the number of displayed pages pointer P. and the first page is displayed (step T37, step T38)11
FIG. 10 shows the display state accompanying the operation of the switch S4, and the schedule data in the data memory DM is cyclically displayed every time the switch S4 is operated.

Further, when the switch S1 is operated, this is detected in step T39, and the process proceeds to step T40, where it is determined whether the contents of the register Fs are "0". Now, if the content of register Fs is "1" and the mode is time correction mode or schedule mode, the cursor moves to 1 in the next step T41.
The digits are shifted. Therefore, in this case, switch S+
functions as a correction digit selection switch, but when the contents of register Fs are "0", the operation of switch SI is invalid. Note that the selection techniques (shown with circles in FIGS. 9c and d) are clearly indicated by blinking.

Also, in the time correction mode or schedule writing mode, when the numeric keypad or alphabet keys are operated to input one character, step T39 to step T
The process advances to step 42, where it is determined whether the contents of the register Fs are "0". Since the time adjustment mode or schedule writing mode is currently set, the process advances to step T43, and the input data is displayed at the cursor position when the key input is completed. Thereafter, it is checked whether the mode is clock mode or schedule mode, and the corresponding processing (steps T45 and T46) is executed. That is, in the 1-clock mode, input data is stored as date or time data in registers BD and BT in the RAM 13. This rewrites the contents of register BD and register BT, making it possible to correct the date and time. Further, in the schedule mode, input data is stored as schedule data in the data memory DM addressed by the value of the display page pointer P.

This allows the schedule data in the data memo 90M to be modified or new schedule data to be written. In this case, in order to write new data, it is sufficient to display an empty page by operating the switch S4 described above, and then input the data.

FIG. 7 is a flowchart showing specific details of the schedule data sorting process (steps T23 and T28) shown in FIG. First, an initial value rlJ is set in address register n (step Ts+)
, Next, the process proceeds to step T52 and the area DI+ (
In this case, D+) is compared with register BD to check whether the current date has passed the scheduled date of the schedule. As a result, if the schedule has passed, the process proceeds to step TS3, where the next year flag is turned on to indicate that the schedule is for the next year, and "l" is placed in area f corresponding to area Dn.
is set. Also, if it has not passed, step T
Proceeds to 's4, and the next year's flag is turned off. However,
An increment process (step T55) in which the value of address register n is increased by 1 is executed, and the process proceeds to step T56, where address register n and total data number memory N are compared to determine whether the value of address register n exceeds the total number of data. It is checked, and if it is not exceeded, the process returns to step T52 and the above-described operation is repeated. As a result, the next year flag is set to O according to the current date corresponding to each schedule data.
N: Turned off.

When such next year flag ON/OFF processing is completed, the process proceeds to step T57, and schedule data rearrangement processing is executed. That is, the schedule data is sorted in descending order of schedule date and time based on the current date and time.

Therefore, even if there are multiple schedules on the same day, they are sorted in ascending order of time, and next year's schedule data is sequentially placed after this year's data.

Once the contents of the data memory DM have been edited in this way, a process for setting the next notification number in the address register n is then executed. In this case, since the schedule data to be notified next by the above-mentioned editing process is normally stored at address "l" of the data memory DM, "1" is set in the address register n (step Tss). However, if there are multiple schedules on the same day, the next year's flag will be turned on and off based on the date, so even if the current time has passed the schedule time, that schedule data will not become the theta for the next year, but the time Edited in chronological order. Therefore, in such a case, the following process is executed to update the value of address register n. That is, first, in step T59, area D
n and register BD are compared to determine whether the current date has reached the first scheduled scheduled date. If not, the value of address register n remains rlJ, but when the scheduled scheduled date arrives, step T60 to check whether the current time has passed the scheduled time. In this case, if it has passed, the value of the address register n remains rlJ, but if it has passed, the value of the address register n is incremented by 1, and then the address register n and the total data number memory N are compared. (Step T61. Step T62) *Now, if the value of the address register n exceeds the total number of data, the value of the address register n remains unchanged, but if it does not, the process returns to step T59 and the same process is executed. As a result, the next notification number is set in the address register n.

Figure 8 shows the alarm processing (step T4) shown in Figure 5.
2 is a flowchart showing specific contents. First, when entering this flow, it is determined whether the alarm flag is ON or OFF based on the contents of the alarm flag register AL (step T?+) @If the alarm is currently OFF,
Current date and time data read from register BD and register BT and read from area Dn and area Tn corresponding to the next notification number in address register n
The updated schedule date and time data are compared and a match is detected. (Step T72) Now, when coincidence of alarm times is detected, the alarm flag is turned on, "l" is set in the register AL, and then the timer operation is started (step T72).
73, Step T p a )a Note that at the same time as this timer starts, a buzzer is turned on and an alarm sound is generated. As described above, when the alarm time comes, the alarm flag is turned ON, so when the alarm processing is started again after the next 1716 seconds, the process proceeds from step 771 to step T75, and it is determined whether a certain period of time has elapsed. Here, it is determined whether a certain period of time has elapsed. Here, if a certain period of time has not elapsed, the alarm sound will continue to be generated until the certain period of time has elapsed, but when the certain period of time has elapsed, the buzzer will turn off in step T76.
It is turned off and the alarm sound is stopped. Then, in the next step T77, the value of the address register n is incremented by 1, and the next notification number is updated.

As described above, in this embodiment, when the time adjustment mode or the schedule writing mode is canceled by operating the switch S2, the schedule data is rearranged, so even if the schedule data is written out of order. However, each schedule data can be rearranged in ascending order of date and time based on the current date and time. therefore,
When detecting a coincidence of alarm times, it is only necessary to compare the schedule data indicated by the next notification number of address register n with the current date and time, so even if a large amount of schedule data is stored, alarm time detection is easy. Processing can be performed efficiently.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be modified and applied in various ways without departing from the scope of the present invention.

[Effects of the Invention] As described above in detail, the present invention allows a plurality of alarm times consisting of time information on a month-day basis or less to be rearranged and stored in the order of the current year and the next year according to the month and day information of the current time. As a result, even if a large number of alarm times are stored, the detection of alarm times can be efficiently processed.

[Brief explanation of the drawing]

The drawings show one embodiment of the present invention, and FIG. 1 is a block circuit diagram of an electronic wristwatch with a schedule function to which the present invention is applied, FIG. 2 is an external plan view thereof, and FIG. The configuration diagram of the display device shown in FIG. 4 is the R shown in FIG.
Main configuration diagram of AM, Figure 5 is a general flowchart showing an overview of the overall operation, Figure 6 is a flowchart showing specific details of the key processing and display processing shown in Figure 5, and Figure 7 is a flowchart showing specific details of the display processing. 8 is a flowchart showing the specific details of the schedule data rearrangement process shown in FIG. FIG. 11...ROM, 12...Instruction decoder, 13...RAM, 14...Arithmetic section, 21...Key manual section. Patent applicant Casio Computer Co., Ltd. Figure 2 2A Figure 3 Figure 5 Figure 4 Figure 8 Figure 9 Figure 10

Claims (1)

[Scope of Claims] A clock means for obtaining current time information consisting of month/day information and hour/minute information; and an alarm time storage means having a plurality of storage areas in which alarm time information consisting of month/day information and hour/minute information is stored. , editing means for rearranging and storing the alarm time information in each storage area of the alarm time storage means according to time order; and an editing means for rearranging and storing the alarm time information in each storage area of the alarm time storage means, and a current time obtained by the alarm time information stored in the alarm time storage means and the time measurement means. In the alarm clock, the editing means includes month/day information comparing means for comparing the month/day information of the alarm time information with the month/day information of the current time information. Based on the comparison result of this month/day information comparison means, alarm time information having month/day information before the current month/day information is placed after alarm time information having month/day information after the current month/day information. An alarm clock characterized by comprising a sorting means for sorting.