JPH027670A - Picture reader - Google Patents

Abstract

PURPOSE:To prevent an output waveform from being distorted at joints of color CCDs by applying white balance adjustment of the 1st - nth line sensors based on the result of image pickup from the 1st line sensor. CONSTITUTION:A picture read section 21 having the 1st - nth line sensors 27a-27e, a white balance adjusting base 36 picked up by the 1st line sensor 27a, and the 2nd drive section outputting the result of pickup from the 2nd - nth line sensors 27b-27e in the predetermined 2nd timing, are provided to the reader. Moreover, the 1st drive section 26 outputting the result of pickup from the 1st line sensor 27a when the 2nd drive section does not drive the 2nd - nth line sensors, and a white balance adjusting section 22 applying white balance adjustment of the 1st - nth line sensors based on the result of pickup when the result of pickup is outputted from the 1st line sensor are provided. Thus, even if the value of a white level correction value beta is fluctuated, the output waveform at the joints of color CCDs is not distorted.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Application The present invention provides an image reading system for reading a document while adjusting the white balance of a plurality of line sensors.

<Prior Art> As an image reading device used in a digital copying machine, facsimile machine, image file device, etc., the one shown in FIG. 11 is conventionally known.

The image reading device shown in this figure has a color CCD array l
, an analog processing section 2, an A/D conversion section 3, a digital processing section 4, an interface section 5, and a timing control section 6, and when a document is inserted, the document is processed line by line. to generate RGB color signals,
Output this.

The color CCD array 1 includes five color CCDs 7a to 7e arranged in a staggered manner as shown in FIG. 12, and a white balance adjustment substrate 16 arranged within the imaging range of the color CCD 7a. When the driving voltage is supplied, each color CCD 7a to 7e reads an image line by line, and converts the imaging result (line image) into an analog signal by using line shift signals φv1 to φv7 supplied from the timing control unit 6. It is supplied to the processing section 2. In addition, these color CCDs 7a to 7e are arranged in four staggered positions, respectively, so that these color CCDs are
Images of each dummy pixel portion (see FIG. 13) of CDs 7a to 7e can be read by effective pixel portions of other color CCDs.

As shown in FIG. 14, the analog processing section 2 includes a first correction circuit 8a to a fifth correction circuit 8e4, and performs shading correction and dark current correction on the pixel signals supplied from the color CCD array 1 or 45. , performs various corrections such as white level correction, and converts the resulting pixel signal into A, /
The signal is supplied to the D converter 3.

In this case, the first correction circuit 8a and the pixel capture circuit 9,
It is equipped with an ACC circuit IO, a shading correction circuit 11, a dark current correction circuit 12, and a mortar level calculation/white level correction circuit 13, and performs shading correction and dark current correction on the pixel signal supplied from the color CCD 7a. Various types of oil iE such as correction and white level correction are performed, and an amplification factor α and a white level correction value β for this pixel signal are determined.

Every time a pixel signal is supplied from the color CCD 7a, the pixel capture circuit 9 captures the pixel signal and supplies it to the AGC circuit IO.

When the AGC circuit IO is supplied with the signal WB indicating the self-balance instruction, the AGC circuit IO determines the optimal amplification factor α for the value of the pixel signal supplied from the pixel capture circuit 9, and calculates the optimum amplification factor α for the value of the pixel signal supplied from the pixel capture circuit 9, and applies this to the second correction circuit 8b to the second correction circuit 8b. 5 correction times V38e, and this amplification factor α until the signal WB is supplied again.
The pixel signal is amplified and supplied to the shading correction circuit 11.

The shading correction circuit 11 corrects the value of the pixel signal supplied from the ACC circuit 10 based on the shading correction data 5HDI supplied from the A/D converter 3, and supplies it to the dark current correction circuit I2. .

When supplied with the signal DS, the dark current correction circuit 12 calculates a dark current correction value γ based on the value of the pixel signal supplied from the shading correction circuit 11, and calculates the dark current correction value γ based on the value of the pixel signal supplied from the shading correction circuit 11.
The value of the pixel signal is corrected using this dark current correction value γ until the dark current correction value γ is supplied again, and this is supplied to the mortar level calculation/white level correction circuit 13.

When the signal We is supplied, the mortar level calculation/whitening correction circuit 13 calculates a white level correction value β based on the pixel signal supplied from the dark current correction circuit 12, and uses this as a second correction value β. At the same time as the signal is supplied to the correction circuits 8b to 5th correction circuit 8e, the value of the pixel signal is corrected with this white level correction value β, and this is sent to the A/D.
Supply to converter 3.

The second correction circuit 8b includes a pixel capture circuit 9, a preamplifier circuit 15, a shading correction circuit 11, a dark current correction circuit 12, and a white level correction circuit 14, and is supplied with the signal O5. At this time, the dark current correction value γ is calculated, and the value of the pixel 1a supplied from the color CCD 7b is corrected using this dark current correction value γ until the signal DS is supplied again. The pixel signal is amplified using the amplification factor α supplied from 8a and the white 1 noher correction value β, the white level is corrected, and the shape ink correction data 5HD2 supplied from the A/D converter 3 is used. Shading correction is performed on the value of the pixel signal. Then, the pixel signals after each of these correction processes are supplied to the A/D converter 3.

Further, the third correction circuits 80 to 8e also include the second correction circuit 8b.
The color ccD7c to 7e
Each correction process is performed on the pixel signal supplied from the A/1 converter 3, and the pixel signal obtained thereby is supplied to the A/1 converter 3.

The A/D converter 3 includes a converter that A/D converts each pixel signal supplied from the analog/cog processor 2,
During self-balance adjustment, each pixel signal supplied from the analog processing section 2 is A/D converted to generate shading correction data 5HDI to 5II05, and each of these shading correction data 51101 is used until the next white balance adjustment.
While holding f7 HD5s, each of these is supplied to the analog processing section 2.

Furthermore, when capturing an image, the pixel signals supplied from the analog processing section 2 are A/D converted to generate image data, which is then supplied to the digital processing section 4 .

The digital processing unit 4 processes the image data and converts it into RGB
A color signal is generated and supplied to the interface unit 5.

The interface section 5 generates a predetermined format RGB color signal from the ROB color signal supplied from the digital processing section 4, and supplies this to a next-stage device (not shown).

The timing control unit 6 includes various timing generation circuits, and operates the color C(1) array 1 to the interface unit 5 as described below.

First, the timing control section 6 controls each color CCD 7a constituting the color CCD array 1 as shown in FIG. 15(a).
A shift gate signal SH is supplied to CCDs 7a to 7e to enable output of each line image captured by these color CCDs 7a to 7e.

Next, the timing control section 6 supplies two-phase lock signals φA and φB to these color CCDs 7a to 7e as shown in FIG. 15(1)), and as shown in FIG. The pixels of the dummy pixel portion are outputted pixel by pixel from the CCDs 7a to 7e, and while the pixels of the dummy pixel portion are being output, the signal 05 is supplied to the analog processing unit 2 as shown in FIG. 15(d). to perform dark current correction.

After this, when effective pixels start to be output from each color CCD 7a to 7e, the timing control section 6
As shown in the figure, the signal νB is supplied to the analog processing section 2 to correct the balance of the pixel signals output from each of the color CCDs 7a to 7e.
RGB color signals are generated based on the output of e.

Then, when the processing of the image for one line is completed, the timing control unit 6 controls each color C as shown in FIG. 15(f).
Line shift signals φv1 to φv7 are supplied to the CDs 7a to 7e to record one line of images captured by the color CCDs 7a to 7e in the elements and to start the next imaging operation.

Thereafter, the above-described operation is repeated to read the original.

Purpose> By the way, in such conventional image reading devices,
A white balance:A transfer board 16 is placed within the field of view of the color CCD 7a, and based on the own level correction value β obtained by imaging this board 16, the color CCD 7a and other color CCDs 71) to 7e are adjusted. Since self-balance adjustment is being performed, until the amplification factor α of the AGC circuit 10 is stabilized,
As shown in FIG. 16, output waveform distortion occurs at the joints between these color CCDs 7a to 7e.

In view of the above circumstances, an object of the present invention is to provide an image reading device that can prevent the output waveform from being distorted at the joint portion of each color CCD even if the value of the white level correction value β changes. There is.

Configuration> In order to solve the above-mentioned problems, an image reading device according to the present invention includes an image reading section having first to nth line sensors, a white balance adjustment board imaged by the first line sensor, , a second driving section that outputs the imaging results from the second to eleventh line sensors at a second predetermined timing; and this second driving section does not drive the second to +1st line sensors. When the first line sensor outputs the imaging result, when the first line sensor outputs the imaging result, the first drive unit outputs the imaging result from the first line sensor based on the imaging result ζ.
The present invention is characterized in that it includes a white balance adjustment section that adjusts the white balance of the 1st to 1st line sensors.

The present invention will be specifically described below based on one embodiment.

FIG. 1 is a block diagram showing an embodiment of an image reading device according to the present invention.

The image reading device shown in this figure has a color CCD array 2
1, an analog processing section 22, an A/D conversion section 23, a digital processing section 24, an interface section 25, and a timing control section 26. Each unit is read to generate an RGB color signal, which is supplied to the next stage device (not shown).

As shown in FIG. 2, the color CCD array 21 includes five color CCDs 27a to 27e arranged so that their effective pixel portions and dummy pixel portions overlap each other so that all pixels in the main scanning direction can be imaged. and color CCD27a
A board 36 for white balance adjustment arranged within the imaging range of
and each of these color CCDs 27a to 27e.
The substrate 36 and the original are imaged by the image capturing operation, and pixel signals obtained by this image capturing operation are supplied to the analog processing section 22.

As shown in FIG. 3, the color CD 27a includes a photodiode array 40, a barrier electrode 41, a storage electrode 42,
It includes a plurality of line shift gates 43a to 43g, one shift gate 44, a horizontal CCD register 45, a manual gate 46, an output gate 47, a reset gate 48, and an output transistor section 49. Then, when line shift signals φv1 to φv7 are supplied from the timing control section 26 as shown in FIGS. 4(a) to 4(C),
The pixel charges obtained by the imaging operation are transferred from the barrier electrode 41 to the storage electrode 42 to the plurality of line shift gates 43a to 43g.
→Transfer to the shift gate 44 via a path called shift gate 44. Thereafter, when the shift gate signal S old is supplied from the timing control section 26 as shown in FIG. 4(d), each pixel charge held in the shift gate 44 is transferred to the horizontal CCD register 45. And Fig. 4(e)
When the two-phase lock signals φIAI, φ2AI, and φ281 are supplied from the timing control section 26 as shown in FIG.
In synchronization with these, each pixel charge held in the horizontal CCD register 45 is output pixel by pixel by the transistor section 49.
and output it from the output terminal O5.

In addition, the color CCDs 271) and 27d are also the color CCDs 271) and 27d.
It is constructed similarly to D27a. And Figure 5 (
When the line shift signals φVl to φv7 are supplied from the timing control section 26 as shown in a) to (g), the line shift gates 43C to 43g are held in a blank state, respectively.
The pixel charges obtained by the imaging operation before the "4" to "1" operations are sequentially line-shifted, and the pixel charges before the "4" operation are transferred to the shift gate 44, and the pixel charges obtained by the current imaging operation are transferred to the shift gate 44. The generated pixel charge is transferred to the line shift gate 43C via the barrier electrode 41→storage electrode 42→line shift gate 43a, 431]→line shift gate 43C and held therein.
), when the shift gate signal SH2 is supplied from the timing control section 26, each pixel charge held in the shift gate 44 is transferred to the horizontal CCD register 45. Then, as shown in FIG. 5(i), two-phase lock signals φtA2 and φIA2 are output from the timing control section 26.
, φ2B2 are supplied, the horizontal C
Each pixel charge held in the CD register 45 is transferred pixel by pixel to the output transistor section 49, and outputted from the output terminal O5. In this case, these color CCD
27b and 27d output the pixel charge obtained by the imaging operation before the "4" operation, thereby
The deviation in the sub-scanning direction with respect to the CD 27a is electrically compensated.

Color CCDs 27c and 27e also have the color 〇CD.
It is configured similarly to 27a. And the color C
During the line shift period of the CD 27a, the line shift signals φVl to φ supplied from the timing control section 26
v7, shift gate signal 5H12-phase clock signal φIA
2. The pixel charges obtained by the current imaging operation are output from the output terminal O5 in units of one pixel corresponding to φ2A2 and φ2B2.

The analog processing section 22 includes a first correction circuit 28a to a fifth correction circuit 28e as shown in FIG. 6, and performs shading correction, dark current correction, and Performs various corrections such as white level correction, and converts the resulting pixel signals into A/
The signal is supplied to the D converter 23.

In this case, the first correction circuit 28a includes a pixel capture circuit 29, an AGC circuit 30, a shading correction circuit 31, a dark current correction circuit 32, a white level correction/white level The correction circuit 33 performs various corrections such as shading correction, dark current correction, and white level correction on the pixel signal supplied from the color CCD 27a, and calculates the amplification factor α for this pixel signal. , and calculate the mortar level correction value β.

The pixel capture circuit 29 includes two FETs (field effect transistors) 50.51, a variable resistor 52 inserted between the drain and source of these FETs 50.51, and a signal C.
an analog switch 53 that closes when LP is supplied to ground the gates of the FETs 50 and 51; and a signal 5CL.
The analog switch 54 is provided with an analog switch 54 that closes when the color CCD 27a is supplied and supplies the pixel signal supplied from the color CCD 27a to the gate of the FET 50. Each time the pixel signals are alternately supplied, the pixel signals supplied from the color CCD 27a are taken in and the AGC
Supplied to circuit 30.

The AGC circuit 30 includes an operational amplifier 55 that amplifies the output from the variable resistor 52, a variable feedback circuit 56 that controls the gain of the operational amplifier 55, a resistor 57, and a capacitor 58.
an analog switch 60 that closes when signal B is supplied and supplies the output of the operational amplifier 55 to the integration circuit 59; and an analog switch 60 that buffers and amplifies the output of the integration circuit 59 to optimize the output. A signal indicating the amplification factor α is generated, and the signal is supplied to the feedback circuit 5G to control the feedback, and the second correction circuit 281) to the fifth correction circuit 128
and a buffer amplifier 61 for supplying signals to e. When the signal -8 is supplied from the timing control section 26, the optimum amplification factor α is determined for the value of the pixel signal supplied from the pixel capture circuit 29, and a signal indicating this amplification factor α is determined. Here, the signal WB is again supplied to the second correction circuit 28I) to the fifth correction circuit 28e.
amplifying the pixel signal with this amplification factor α until the pixel signal is supplied;
This is supplied to the shading correction circuit 31.

The shading correction circuit 31 receives the shading correction data 5D+ supplied from the A/D converter 23 and the A/D converter 23.
A digital/analog multiplier 62 that multiplies the pixel signal supplied from the GC circuit 30, a logarithmic amplifier 63 that logarithmically amplifies the output of the digital/analog multiplier 62, and a signal FS)ID from the timing control section 26. an analog switch 6 that closes when the output is output and supplies the output of the digital/analog multiplier 62 to the dark current correction circuit 22;
4, and “1” when the signal FSHO is not output.
° An inverter 65 that generates a signal, and this inverter 6
The analog switch 66 closes when the output signal from the logarithmic amplifier 63 is output from the logarithmic amplifier 63 and supplies the output of the logarithmic amplifier 63 to the dark current correction circuit 32.

When the shading correction data S old is supplied from the A/D converter 23, the value of the pixel signal supplied from the AGC circuit 30 is corrected based on the value of the shape ink correction data S old (shading correction). do. Further, when the signal FSHD is supplied, that is, when creating the shading correction data 5llO1, the output of the digital/analog multiplier 62 is selected and supplied to the dark current correction circuit 32. Moreover, the signal FS)l[
) is not supplied, a pixel signal obtained by logarithmically amplifying the output of the digital/analog multiplier 62 is selected and supplied to the dark current correction circuit 32.

The dark current correction circuit 22 includes the shading correction circuit 3.
An operational amplifier 67 that amplifies the pixel signal from 1 and a resistor 6
an analog switch 71 that closes when the timing control section 26 outputs the signal DSI and supplies the output of the operational amplifier 67 to the holding circuit 70; buffer and amplify the output of to generate a signal indicating the dark current correction value γ,
A buffer 72 is provided to feed back this to the operational amplifier 67 to cancel the offset due to the dark current. When the signal DS is supplied, a dark current correction value γ is calculated based on the value of the pixel signal supplied from the shading correction circuit 11, and this dark current correction value γ is calculated until the signal DSI is supplied again. γ to correct the value of the pixel signal and supply it to the white level calculation/white level correction circuit 23.

The white level calculation/white level correction circuit 23 includes a correction value 17 holding section 73 and a voltage dividing section 74, and when the signal WB is supplied, the white level calculation/white level correction circuit 23 converts the pixel signal supplied from the dark current correction circuit 12 into Based on this, a mortar level correction value β is determined, and this is supplied to the second to fifth correction circuits 8h to 8e, and the pixel signal is maintained at this own level correction value β until the signal -B is supplied again. Correct the value of and convert this correction result into A
/D converter 23.

The correction value holding unit 73 includes a holding unit 77 including a resistor 75 and a capacitor 76, and a holding unit 77 that closes when the signal WB is supplied and supplies the pixel signal output from the dark current correction circuit 22 to the holding unit 77. It is equipped with an analog switch 7 and a buffer 79 for buffering and amplifying the signal held in the holding section 77, and the timing control section 2
When the signal WB is supplied from 6, the dark current correction circuit 2
The value of the pixel signal output from 2 is held and supplied to the voltage dividing section 74.

The voltage dividing unit 74 includes four variable voltage dividers 80a to 80d that divide the output of the correction value holding unit 73, and four analog switches 81a to 81d that selectively take out the output of each of these variable voltage dividers 80a to 80d. and a buffer amplifier 82 that buffers and amplifies the signals selected by these analog switches 81a to 81d, and when the signal FSHD is supplied from the timing control section 26, the variable voltage divider 80d controls the correction value holding section 73. The output of
The A/D converter 23 and the second correction circuit 2 as a signal indicating
8b to the fifth correction circuit 28e.

Further, the concentration designation signal FD is sent from the timing control section 26.
(or one of the concentration designation signals N and il1 degree designation) is supplied, the output of the variable voltage divider 80a (or either of the variable voltage dividers 80b and 80c) is selected in response to this. , this is used as a signal indicating the mortar level correction value β to the A/D converter 23 and the second correction circuit 28b.
It is supplied to the fifth correction circuit 28e.

Further, as shown in FIG. 7(1), the second correction circuit 281] includes a pixel capture circuit 29, a preamplifier circuit 35, a shading correction circuit 3], and a dark current? ? IiE circuit 3
2 and a white level correction circuit 34.

In this case, the preamplifier circuit 35 includes an operational amplifier 83 that amplifies the output of the pixel capture circuit 29, and a variable feedback circuit 84 that adjusts the gain of the operational amplifier 83. The output of the pixel capture circuit 29 is amplified using an amplification factor α based on the supplied signal, and is supplied to the shading correction circuit 31 .

Further, the own level correction circuit 34 includes the dark current correction circuit 32
and the signal output from the first correction circuit 28a (signal indicating the white level correction value β),
/D converter 23.

The second correction circuit 281) calculates a dark current correction value γ when the signal DS2 is supplied, and the dark current correction value γ is supplied from the color CCD 27b until the signal 052 is supplied again. correct the value of the pixel signal,
The pixel signal is amplified using the amplification factor α supplied from the first correction circuit 28a and the mortar level correction value β, the white level is corrected, and the shading correction data 5llD2 is supplied from the A/D converter 23. The value of the pixel signal is subjected to shading correction based on the pixel signal. Then, the pixel signals after each of these correction processes are sent to the A/D converter 23.
supply to.

Further, the third correction circuits 28c to 28e are also configured similarly to the second correction circuit 28b, and the third correction circuits 28c to 28e are configured similarly to the second correction circuit 28b.
Each correction process is performed on the pixel signals supplied from c to 27e, and the pixel signals obtained thereby are sent to A.
/D converter 23.

The A/D conversion section 23 includes a converter 94a that A/D converts each pixel signal supplied from the analog processing section 22.
-94e, when adjusting white balance, each pixel signal supplied from the analog processing section 22 is A/D converted to generate shading correction data 5HOI-5t (05), and these are stored until the next white balance adjustment. While holding the shading correction data 5HDI to 5HD5, each of these data is supplied to the analog processing section 22.
When capturing an image, the signal supplied from the analog processing section 22 is A/D converted to generate image data, which is then supplied to the digital processing section 24 .

The digital processing unit 24 processes the image data to create an RG image.
A B color signal is generated and sent to the interface section 25.
supply to.

The interface unit 25 generates a predetermined format RGB color signal from the RGB color signal supplied from the digital processing unit 24, and supplies this to the next stage device.

Further, the timing control section 6 includes an oscillation circuit 85, a timing generation circuit 86, and a control circuit 87, as shown in FIG. ~Interface section 25
control.

The oscillation circuit 85 includes a clock generator 88 that generates a clock signal, and generates a line peer signal from the clock signal obtained by the clock generator 88 to generate 5VNCI, LSYN.
C2 and a signal generator 89 that generates a video clock signal VCLK, and supplies various signals obtained by the signal generator 89 to a timing generation circuit 86 and a control circuit 87.

The timing generation circuit 86 generates the line synchronization signal LSY.
Each time NCI is supplied, a first main scanning counter 90 clears the previous count value and restarts counting of the video clock signal VCLK, and a shift gate is activated based on the count output of the first main scanning counter 90. Signal S old, two-phase lock signal φIAI, φ2AI, <628
1. Every time the 10th switch circuit 91 that generates the signals [ISl, We, etc. and the input signal LSYNC2 mentioned above is supplied, it clears the previous count value and also clears the count of the video clock signal VCLK. The second main scanning counter 92 restarts, and based on the count output of the second main scanning counter 92, the shift gate signal 5t12.2 phase lock signals φIA2, φ2A2, φ282, and the signal O52 are activated.
and a 20th chic circuit 93 that generates the following.

Then, the shift gate signal Sold, two-phase lock signals φIAI, φ2A1 obtained by the tenth shift circuit 91
, φ2 old, signal O5+, We, and second c2 chic circuit 9
Shift gate signal SH2 obtained by 3, 2-phase a
Tsuk signal φ1A21. φ2A2, φ2B2, signal Oc
>2 is supplied to the color CD array 21 to interface section 25 to control these operations.

Further, the control circuit 87 generates various control signals from the output of the oscillation circuit 85 and controls the operations of the color CCD array 21 to the interface section 25.

Next, the operation of this embodiment will be explained with reference to the timing charts shown in FIGS. 9(a) to 9(j).

First, when the imaging operation for 1942 minutes is completed, the timing control section 26 supplies line shift signals φv1 to φ7 to the color CCDs 27a to 27e constituting the color CCD array 1, as shown in FIG. 9(a). , this color CCD
The images captured by 27a to 27e are transferred to the shift gate 44. Thereafter, the timing control unit 26 supplies the shift gate signal 5 to the color CCD 27a, as shown in FIG. 9(b), so that each line image captured by the color CCD 27a can be output.

Next, the timing control section 26 applies a two-phase lock signal φIAI to the color CCD 27a as shown in FIG. 9(C).
, φ2Al, and φ281, the pixels of the dummy pixel portion are outputted pixel by pixel from each color CCD 27a as shown in FIG. 9(d), and the pixels of the dummy pixel portion are being outputted. So, Figure 9(e)
As shown in the figure, the signal [ ) St is supplied to the analog processing section 2 to cause the first correction circuit 28a to perform dark current correction.

Thereafter, when effective pixels begin to be output from the color CCD 27a, the timing control section 26 supplies the signal WB to the analog processing section 22 as shown in FIG. 28e to correct its own balance, R based on the output of this color C0D 27a.
Generates a GB color signal and sends it to the digital processing unit 2.
4 to be memorized. In this case, since no pixel signals are output from the color CCDs 27b to 27e other than the color CCD 27a, the outputs of the second to fifth correction circuits 28b to 28e, which process the outputs of these color CCDs 27b to 27e, do not change. .

Further, when effective pixels are being output from the color C0D 7a, the timing control unit 26 controls the timing control unit 26 as shown in FIG.
As shown in g), the shift gate signal 5) 12 is supplied to these color CCDs 27b to 27e to convert these color CCDs.
Each line image captured by 27b to 27e is made ready for output.

Next, the timing control unit 26 supplies two-phase lock signals φIA2, φ2A2, and φ2B2 to these color CDs 27b to 27e as shown in FIG.
As shown in i), each of these color CCDs 271) to 27
The pixels of the dummy pixel portion are output from e in units of pixels, and while the image of this dummy pixel portion is being output, the signal DS2 is supplied to the analog processing unit 2 as shown in FIG. 9(j). This causes the second correction circuits 28b to 28e to perform dark current correction.

Thereafter, when effective pixels start to be output from each of these color CCDs 27b to 27e, the timing control section 26 controls the RG
A B color signal is generated and this is sent to the digital processing section 24.
to be memorized.

When all pixels for one line are output from these color C and CD 27a to 27e, the digital processing unit 2
R of each color CCD 27a to 27e stored in 4
Based on the GB color signals, the interface section 25 outputs RGB color signals in a predetermined format.

Thereafter, the document is conveyed one line in the sub-scanning direction, and the above-described operation is repeated.

In this way, in this embodiment, the color CCD 27
When no pixels are output from b to 27e, color C
Based on the output of CD27a, this color C0D27a
Also, since the white balance adjustment of the other color CCDs 27b to 27e is performed, the output waveform of the joint portion of these color CCDs 27a to 27e can be flattened as shown in number 10.

Further, in the embodiment described above, the color CCD 27b to
During the line shift period of 27e, a signal We is generated,
These colors C0D27b to 27e and color 〇CD2
7a, when dummy pixels are being output from the color CCDs 27b to 27e, the signal We is generated to adjust the white balance of each color CCD 27a to 27e.
27e may be used to adjust the white balance.

Effect> As explained above, according to the present invention, the mortar level correction value β
Even if the value of is changed, it is possible to prevent the output waveform from being distorted at the joint portion of each color CCD.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an image reading device according to the present invention, FIG. 2 is a schematic diagram showing a configuration example of the color CCD array shown in FIG. 1, and FIG.
A schematic diagram showing an example of the configuration of a CD, FIGS. 4(a) to 4(e) are timing charts showing driving examples of a color CCD in the same embodiment, and FIGS. 5(a) to (i) each show the same embodiment. 6 is a block diagram showing details of the analog processing section shown in FIG. 1, and FIG. 7(a) shows details of the first correction circuit shown in FIG. 6. The circuit diagram, Fig. 7 (1)) is the same as the circuit diagram shown in Fig. 6.
FIG. 8 is a circuit diagram showing details of the correction circuit; FIG. 8 is a block diagram showing details of the timing control section shown in FIG. 1; FIG. 9(a)
~(j) are timing charts showing operation examples of the same embodiment, FIG. 10 is a waveform diagram showing an output example of the same embodiment, and FIG.
FIG. 1 is a block diagram showing an example of a conventional image reading device.
FIG. 12 is a schematic diagram showing an example of the configuration of the color CCD array shown in FIG. 11, FIG. 13 is a schematic diagram showing an example of the pixel configuration of the color CCD array, and FIG. 14 is a detailed diagram of the analog processing section shown in FIG. 11. A block diagram showing FIG. 15 (a) to (f)
) are timing charts showing operation examples of the image reading device shown in FIG. 11, and FIG. 16 is a waveform diagram showing an output example of the image reading device shown in FIG. 11. 21... Image reading unit (color CCD array), 22
...White balance adjustment section (analog processing section), 26...
・First drive section, second drive section (timing control section), 27
a to 27e... 1st to nth line sensors (color CCD), 36... White balance adjustment board (substrate)
.

Claims (1)

[Claims] an image reading section having first to nth line sensors;
a white balance adjustment board imaged by the first line sensor; a second drive section that causes the second to n-th line sensors to output the imaging results at a second predetermined timing; and the second drive section. a first driving section that outputs an imaging result from the first line sensor when the second to nth line sensors are not being driven; and a first driving section that outputs the imaging result from the first line sensor; An image reading device comprising: a white balance adjustment section that adjusts the white balance of the first to nth line sensors based on the imaging results.