JPH027476A - Amorphous silicon semiconductor device and manufacture thereof - Google Patents
Amorphous silicon semiconductor device and manufacture thereofInfo
- Publication number
- JPH027476A JPH027476A JP63157746A JP15774688A JPH027476A JP H027476 A JPH027476 A JP H027476A JP 63157746 A JP63157746 A JP 63157746A JP 15774688 A JP15774688 A JP 15774688A JP H027476 A JPH027476 A JP H027476A
- Authority
- JP
- Japan
- Prior art keywords
- amorphous silicon
- electrode layer
- semiconductor device
- silicon semiconductor
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021417 amorphous silicon Inorganic materials 0.000 title claims abstract description 99
- 239000004065 semiconductor Substances 0.000 title claims abstract description 86
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 42
- 239000002184 metal Substances 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 239000000843 powder Substances 0.000 claims abstract description 31
- 229920005989 resin Polymers 0.000 claims abstract description 28
- 239000011347 resin Substances 0.000 claims abstract description 28
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 18
- 238000007639 printing Methods 0.000 claims abstract description 7
- 229910052804 chromium Inorganic materials 0.000 claims abstract description 4
- 229910052750 molybdenum Inorganic materials 0.000 claims abstract description 3
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical group [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 38
- 238000000034 method Methods 0.000 claims description 9
- 239000002245 particle Substances 0.000 claims description 9
- 239000011651 chromium Substances 0.000 claims description 5
- 238000010030 laminating Methods 0.000 claims description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- 239000011733 molybdenum Substances 0.000 claims description 2
- 238000007650 screen-printing Methods 0.000 abstract description 5
- 238000010438 heat treatment Methods 0.000 description 8
- 238000007740 vapor deposition Methods 0.000 description 7
- 239000011521 glass Substances 0.000 description 5
- 238000004898 kneading Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000000605 extraction Methods 0.000 description 3
- 238000011056 performance test Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 2
- 239000011230 binding agent Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000011888 foil Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- QTBSBXVTEAMEQO-UHFFFAOYSA-M Acetate Chemical compound CC([O-])=O QTBSBXVTEAMEQO-UHFFFAOYSA-M 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910001295 No alloy Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 150000008065 acid anhydrides Chemical class 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000002518 antifoaming agent Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005422 blasting Methods 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000005007 epoxy-phenolic resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 238000005984 hydrogenation reaction Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000002932 luster Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000013081 microcrystal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 150000002815 nickel Chemical class 0.000 description 1
- -1 organic acid salt Chemical class 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229920006254 polymer film Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 239000012255 powdered metal Substances 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000005361 soda-lime glass Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Landscapes
- Photovoltaic Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明はアモルファスシリコン系半導体装置及びその
製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an amorphous silicon semiconductor device and a method for manufacturing the same.
アモルファスシリコン系半導体装置は、その−例を第3
図に示すように、透明基板1上に、透明電極層2とアモ
ルファスシリコン系半導体層3と裏面電極層4とを順次
積層して成るl又は複数のアモルファスシリコン系半導
体素子5によって構成されている。そして、このアモル
ファスシリコン系半導体装置の裏面電極層4は、アモル
ファスシリコン系半導体層3の被着後、その上に所定の
パターンのマスクを設置してアルミニウム^lやクロム
Crなどの金属材料を蒸着あるいはスパッターによって
被着して形成されていた。Amorphous silicon semiconductor devices are the third example.
As shown in the figure, it is composed of l or a plurality of amorphous silicon semiconductor elements 5 formed by sequentially laminating a transparent electrode layer 2, an amorphous silicon semiconductor layer 3, and a back electrode layer 4 on a transparent substrate 1. . The back electrode layer 4 of this amorphous silicon semiconductor device is formed by depositing a metal material such as aluminum or chromium Cr on a mask with a predetermined pattern after the amorphous silicon semiconductor layer 3 is deposited. Alternatively, it was formed by sputtering.
裏面電極層4を蒸着によって形成するためには、アモル
ファスシリコン系半導体N3が被着された透明基板1を
蒸着装置内にセットするとともに所定のパターンが形成
されたマスクの位置調整をする必要があり、作業が煩雑
で時間を要し、生産性の悪いものであった。また、蒸着
装置内を高真空にする必要があり、高価な設備を要した
。しかも、蒸着時に金属材料の突沸により熔融金属の塊
が飛散してアモルファスシリコン系半導体層3を突き破
り、アモルファスシリコン系半導体N3にダメージを与
えることが多く、またこのダメージはアモルファスシリ
コン系半導体装置の歩留りを低下させる原因にもなって
いた。In order to form the back electrode layer 4 by vapor deposition, it is necessary to set the transparent substrate 1 on which the amorphous silicon-based semiconductor N3 is deposited in a vapor deposition apparatus, and also to adjust the position of a mask on which a predetermined pattern is formed. , the work was complicated and time consuming, and the productivity was poor. Furthermore, it was necessary to create a high vacuum inside the vapor deposition apparatus, which required expensive equipment. Moreover, lumps of molten metal are often scattered due to bumping of the metal material during vapor deposition and break through the amorphous silicon semiconductor layer 3, damaging the amorphous silicon semiconductor N3, and this damage reduces the yield of the amorphous silicon semiconductor device. It was also the cause of the decline.
そこで、本発明者らはアモルファスシリコン系半導体装
置の生産性及び作業性を向上させることを目的に種々、
鋭意研究を重ねた結果、本発明に至ったのである。Therefore, the present inventors have made various efforts to improve the productivity and workability of amorphous silicon semiconductor devices.
As a result of extensive research, we have arrived at the present invention.
本発明に係るアモルファスシリコン系半導体装置の要旨
とするところは、絶縁基板上に、第一の電極層、アモル
ファスシリコン系半導体層及び第二の電極層を順次積層
して構成されたアモルファスシリコン系半導体素子が少
なくとも1つ形成されたアモルファスシリコン系半導体
装置において、前記第一の電極層又は第二の電極層が金
属粉末を含有する樹脂層からなるようにしたことにある
。The gist of the amorphous silicon-based semiconductor device according to the present invention is an amorphous silicon-based semiconductor device configured by sequentially stacking a first electrode layer, an amorphous silicon-based semiconductor layer, and a second electrode layer on an insulating substrate. In the amorphous silicon semiconductor device in which at least one element is formed, the first electrode layer or the second electrode layer is made of a resin layer containing metal powder.
また、本発明に係るアモルファスシリコン系半導体装置
の製造方法の要旨とするところは、絶縁基板上に、透明
電極層とアモルファスシリコン系半導体層と裏面電極層
とを順次積層して成るアモルファスシリコン系半導体素
子が1又は複数形成されたアモルファスシリコン系半導
体装置を製造する方法において、
金属粉末を含有する樹脂を所定のパターンに印刷して前
記裏面電極層を形成する工程と、前記裏面電極層が印刷
された工程品に熱処理を施す工程と
を含むようにしたことにある。Furthermore, the gist of the method for manufacturing an amorphous silicon semiconductor device according to the present invention is to produce an amorphous silicon semiconductor device formed by sequentially laminating a transparent electrode layer, an amorphous silicon semiconductor layer, and a back electrode layer on an insulating substrate. A method for manufacturing an amorphous silicon-based semiconductor device in which one or more elements are formed, including a step of printing a resin containing metal powder in a predetermined pattern to form the back electrode layer, and a step of printing the back electrode layer. The present invention includes a step of heat-treating the processed product.
かかる本発明によれば、絶縁基板としてガラスなどの透
明基板に対しては第二の電極層が、金属などの不透明な
絶縁基板に対しては第一の電極層が、それぞれ金属粉末
を含有する樹脂を塗布を含む印刷法によって層状に印刷
されて形成される。According to the present invention, the second electrode layer for a transparent substrate such as glass as an insulating substrate and the first electrode layer for an opaque insulating substrate such as metal each contain metal powder. It is formed by printing in layers using a printing method that includes coating resin.
金属粉末を一定量以上含有する樹脂層は導電性が良く、
電極として機能し得る。A resin layer containing a certain amount or more of metal powder has good conductivity,
Can function as an electrode.
また、アモルファスシリコンは構造上、点欠陥が結晶に
比べて多いため、金属との相互拡散係数が大きく、比較
的低温でも容易に金属との合金化が起こり、オーミック
コンタクトが出来やすい特徴がある。したがって、アモ
ルファスシリコン系半導体層と接触して形成された金属
粉末を含有する樹脂層から成る電極層は、熱処理によっ
てその金属とアモルファスシリコンとがオーミック接合
して、アモルファスシリコン系半導体層と強固に接合さ
せられる。Additionally, since amorphous silicon has more point defects than crystals due to its structure, it has a large interdiffusion coefficient with metals, and is easily alloyed with metals even at relatively low temperatures, making it easy to form ohmic contacts. Therefore, an electrode layer made of a resin layer containing metal powder that is formed in contact with an amorphous silicon semiconductor layer is heat-treated to form an ohmic contact between the metal and the amorphous silicon, and is firmly bonded to the amorphous silicon semiconductor layer. I am made to do so.
次に、本発明の実施例を図面を参照しつつ、詳しく説明
する。なお、図面は説明のため、適宜拡大して示す。Next, embodiments of the present invention will be described in detail with reference to the drawings. Note that the drawings are shown enlarged as appropriate for the purpose of explanation.
第1図及び第2図において、符号1oは絶縁基板であり
、絶縁基板lOはガラスや高分子フィルムなどの透明基
板や、金属箔に絶縁処理を施したものやセラミックなど
の不透明基板により構成され、剛性のあるもの以外に可
撓性のあるものでも良い、絶縁基板lOの上にば第一の
電極Ji12が被着され、絶縁基板10が透明基板であ
る場合は第一の電極層12として透明電極層が形成され
、また絶縁基板10が不透明基板である場合には第一の
電極層12として裏面電極層が形成されることとなる。In FIGS. 1 and 2, the reference numeral 1o indicates an insulating substrate, and the insulating substrate 1O is composed of a transparent substrate such as glass or a polymer film, an opaque substrate such as a metal foil subjected to insulation treatment, or a ceramic substrate. The first electrode Ji12 is deposited on the insulating substrate 10, which may be flexible in addition to the rigid one, and if the insulating substrate 10 is a transparent substrate, the first electrode layer 12 is A transparent electrode layer is formed, and when the insulating substrate 10 is an opaque substrate, a back electrode layer is formed as the first electrode layer 12.
先ず、絶縁基板10が透明基板である場合を例にして説
明する。First, a case where the insulating substrate 10 is a transparent substrate will be described as an example.
透明基板10の上には第一の電極1112として透明電
極層がスパッター法などにより被着形成される。透明電
極層12にはITO,Sn0g、 ITO/5nOtな
どが用いられ、フォトエツチング法、レーザースクライ
ブ法あるいはマスク法などにより所定のパターンに成形
される。A transparent electrode layer is formed as a first electrode 1112 on the transparent substrate 10 by sputtering or the like. The transparent electrode layer 12 is made of ITO, Sn0g, ITO/5nOt, or the like, and is formed into a predetermined pattern by photoetching, laser scribing, masking, or the like.
所定のパターンに成形された複数の透明電極層12の上
には、アモルファスシリコン系半導体層14がイオンブ
レーティング法、真空蒸着法、プラズマCVD法あるい
はスパッタリング法などにより被着される。アモルファ
スシリコン系半導体N14はたとえば、アモルファスシ
リコンa−Si+水素水素化7フルフアスシリコンat
:H+水水素化7ルルフアスシリコンカーバイドa5k
C:H,アモルファスシリコンナイトライドなどの非晶
質からなるものの他、微結晶を含み、またシリコンSt
と炭素C。On the plurality of transparent electrode layers 12 formed into a predetermined pattern, an amorphous silicon semiconductor layer 14 is deposited by an ion blasting method, a vacuum evaporation method, a plasma CVD method, a sputtering method, or the like. The amorphous silicon semiconductor N14 is, for example, amorphous silicon a-Si + hydrogen hydrogenated 7 full silicon at
:H + water hydrogenation 7 rulphous silicon carbide a5k
C:H, in addition to those consisting of amorphous materials such as amorphous silicon nitride, they also contain microcrystals, and silicon St.
and carbon C.
ゲルマニウムGe、スズSnなど他の元素との合金から
なるアモルファスシリコン系半導体を、pin型。Amorphous silicon-based semiconductors made of alloys with other elements such as germanium Ge and tin Sn are pin-type.
pn型、 Ml!9型、ヘテロ接合型、ホモ接合型、シ
ツットキーバリアー型あるいはこれらを組み合わせた型
などに堆積させたものである。pn type, Ml! 9 type, heterozygous type, homozygous type, Schittky barrier type, or a combination of these types.
アモルファスシリコン系半導体層14が被着された透明
基板10の上には、透明電極層12に対応した位置に第
二の電極N16として裏面電極層が形成され、第一の電
極N(透明電極層)12とアモルファスシリコン系半導
体層14と第二の電極層(M面電極層)16とによって
アモルファスシリコン系半導体素子18が構成される。On the transparent substrate 10 on which the amorphous silicon semiconductor layer 14 is deposited, a back electrode layer is formed as a second electrode N16 at a position corresponding to the transparent electrode layer 12. ) 12, the amorphous silicon semiconductor layer 14, and the second electrode layer (M-plane electrode layer) 16 constitute an amorphous silicon semiconductor element 18.
裏面電極N16は金属粉末を樹脂にて混練してペースト
状にしたものをスクリーン印刷法などにより所定のパタ
ーンに印刷された後、固化されて形成される。The back electrode N16 is formed by kneading metal powder with resin to form a paste, printing it into a predetermined pattern by screen printing or the like, and then solidifying it.
ここで、使用される粉末状の金属としては、アモルファ
スシリコンとオーミック接合し得る金属であるとともに
、導電性があり且つ耐熱性があるものが良(、特にニッ
ケルNi+ クロムCr、チタンTt+ モリブデンl
’loが好ましい、なお、従来よりシリコンSi単結晶
に対してアルミニウムAIや銀^gなどでオーミック接
合を得ていたが、結晶構造のシリコンSiに対しては高
温で焼成しなければオーミック接合の合金層が得られな
かった。しかし、アモルファスシリコンではニッケルN
iなどに対して150℃、60分程度の熱処理で充分な
相互拡散が起こり、アモルファスシリコンを熱によって
変性させることなくオーミック接合が得られるのである
。The powdered metal used here should preferably be one that can form an ohmic contact with amorphous silicon, has electrical conductivity, and is heat resistant (particularly nickel, Ni, chromium, titanium, Tt, and molybdenum).
'lo is preferred.In addition, conventionally, ohmic contact has been obtained with aluminum AI, silver^g, etc. for silicon Si single crystal, but ohmic contact cannot be obtained for crystalline silicon Si unless it is fired at high temperature. No alloy layer was obtained. However, in amorphous silicon, nickel N
Heat treatment at 150° C. for about 60 minutes with respect to i, etc. causes sufficient interdiffusion, and an ohmic bond can be obtained without denaturing the amorphous silicon due to heat.
また、金属粉末の粒径は約50μm以下のものが好適に
使用し得て、形状としては球状のものが好ましい、特に
、金属粉末の粒径を111m以下にすると、アモルファ
スシリコン系半導体N14の膜厚が1μm程度であって
もその金属粉末によって接合が破壊されることはなく、
電極間のリーク電流が少ないアモルファスシリコン系半
導体素子18が得られる。したがって、5QIux程度
の低照度で用いられる電子卓上計算機や腕時計などに、
好適に用いることができる。金属粉末を樹脂にて混練し
てスクリーン印刷して得られた裏面電極層16には金属
光沢がなく、裏面電極J116での反射光による発電は
期待し得ないが、低照度で本例に係るアモルファスシリ
コン系半導体装置を用いる場合には元来、入射光量が少
ないため、出力の低下は僅かであり、無視し得るもので
ある。In addition, the particle size of the metal powder is preferably about 50 μm or less, and the shape is preferably spherical. In particular, when the particle size of the metal powder is 111 m or less, the film of the amorphous silicon semiconductor N14 Even if the thickness is about 1 μm, the metal powder will not destroy the bond.
An amorphous silicon-based semiconductor device 18 with low leakage current between electrodes is obtained. Therefore, for electronic desk calculators, watches, etc. that are used in low illuminance of about 5QIux,
It can be suitably used. The back electrode layer 16 obtained by kneading metal powder with resin and screen printing does not have metallic luster, and power generation by reflected light on the back electrode J116 cannot be expected, but it is difficult to generate electricity in this example under low illuminance. When an amorphous silicon semiconductor device is used, the amount of incident light is originally small, so the decrease in output is slight and can be ignored.
他方、粒径が50μm以下の金属粉末を使用する場合は
、その金属粉末が仮にアモルファスシリコン系半導体層
14を破壊してアモルファスシリコン系半導体素子1B
の並列抵抗が小さ(なっても、換言すればリーク電流が
多くなっても、アモルファスシリコン系半導体素子18
の出力にほとんど影響を与えない屋外用に好適である。On the other hand, when using metal powder with a particle size of 50 μm or less, the metal powder may temporarily destroy the amorphous silicon semiconductor layer 14 and cause the amorphous silicon semiconductor element 1B to break down.
Even if the parallel resistance of the amorphous silicon semiconductor element 18 becomes small (in other words, even if the leakage current increases)
Suitable for outdoor use as it has little effect on output.
金属粉末のバインダーである樹脂としては、エポキシ樹
脂やフェノール樹脂などの熱硬化性樹脂やあるいは反応
硬化性樹脂が用いられ、特にアセトンやエタノールなど
の有機溶剤に不溶の耐溶剤性のものが望ましい、樹脂の
硬化条件あるいは硬化促進条件としては、温度120〜
L80’C,時間20〜80分が望ましく、樹脂を硬化
させると同時にアモルファスシリコンと樹脂に含有され
た金属とをオーミック接合させるのに必要な条件を満た
すのが望ましい、また、バインダーである樹脂と金属粉
末との組成比(重量)は、樹脂1に対して金属粉末0.
5〜15であるのが望ましく、導電性を確保し得るとと
もに樹脂の硬化後、金属粉末が剥離し難い範囲で選定さ
れる。As the resin that is the binder for the metal powder, thermosetting resins such as epoxy resins and phenolic resins, or reaction-curing resins are used, and it is particularly desirable to use solvent-resistant resins that are insoluble in organic solvents such as acetone and ethanol. The curing conditions or curing acceleration conditions for the resin include a temperature of 120~
L80'C, the time is preferably 20 to 80 minutes, and it is desirable to satisfy the conditions necessary to cure the resin and at the same time make an ohmic contact between the amorphous silicon and the metal contained in the resin. The composition ratio (weight) of the metal powder is 1 part resin to 0.0 parts metal powder.
The number is desirably 5 to 15, and is selected within a range that ensures conductivity and prevents the metal powder from peeling off after the resin is cured.
このようにアモルファスシリコン系半導体7114の上
に金属粉末を含有させた樹脂を所定のパターンに印刷し
、熱処理によって固化させて裏面電極層16を形成する
とともに、アモルファスシリコンと金属とをオーミック
接合させているのである。In this way, resin containing metal powder is printed on the amorphous silicon semiconductor 7114 in a predetermined pattern and solidified by heat treatment to form the back electrode layer 16, and at the same time, the amorphous silicon and the metal are ohmic bonded. There is.
ここでニッケルNtは半田との親和性に優れているため
、ニッケルNiの粉末を用いて裏面電極N16を形成す
る場合は、電流の取り出し電極20部にもそのニッケル
ペーストが印刷され、取り出し電極20が形成される0
本発明者らは取り出し電極20部にニッケルNtの粉末
を樹脂にて混練したペーストを使用して印刷した後、そ
の取り出し電極20に銀Ag1%入り共晶半田を300
W、先端温度300℃で、直径0.7 L1m+のスズ
Snコートリード線を、半田付けした。そして、このリ
ード線を引っ張り、取り出し電極20部の破壊試験をし
たところ、強度IKgで破壊された。この強度は従来の
蒸着によって得られた取り出し電極部の強度と較べて充
分大きい値であることがn認された。Here, since nickel Nt has excellent affinity with solder, when forming the back electrode N16 using nickel Ni powder, the nickel paste is also printed on the current extraction electrode 20, and the nickel paste is printed on the current extraction electrode 20. is formed 0
The present inventors printed 20 parts of the take-out electrode using a paste made by kneading nickel Nt powder with resin, and then applied 300 parts of eutectic solder containing 1% silver to the take-out electrode 20.
A tin-Sn coated lead wire with a diameter of 0.7 L1m+ was soldered with W and a tip temperature of 300°C. Then, when this lead wire was pulled and a destructive test was performed on 20 parts of the lead-out electrode, it was destroyed with a strength of I kg. This strength was found to be sufficiently larger than the strength of the extraction electrode portion obtained by conventional vapor deposition.
以上詳述したところから明らかなように、本実施例によ
れば、透明基板10上に透明電極N12及びアモルファ
スシリコン系半導体層14を被着した後、金属粉末が含
有させられた樹脂をスクリーン印刷し、低温で熱処理し
て裏面電極fii16を形成するようにしているため、
生産性が向上するだけでなく、安価なアモルファスシリ
コン系半導体装置を提供することが可能となる。しかも
、低温で熱処理することでオーミック接合が得られ、金
属を蒸着させて裏面電極層を形成していた従来のアモル
ファスシリコン系半導体装置と較べ、品質が劣るどころ
か、−層歩留りの良い品質の優れたアモルファスシリコ
ン系半導体装置が得られることとなる。As is clear from the detailed description above, according to this embodiment, after the transparent electrode N12 and the amorphous silicon semiconductor layer 14 are deposited on the transparent substrate 10, a resin containing metal powder is screen printed. However, since the back electrode fii16 is formed by heat treatment at low temperature,
This not only improves productivity but also makes it possible to provide inexpensive amorphous silicon semiconductor devices. Furthermore, ohmic contact can be obtained through heat treatment at low temperatures, and compared to conventional amorphous silicon semiconductor devices in which the back electrode layer is formed by vapor-depositing metal, the quality is not inferior to that of conventional amorphous silicon-based semiconductor devices, which have a high layer yield. Thus, an amorphous silicon-based semiconductor device can be obtained.
次に、絶縁基板10が金属箔などの不透明基板である場
合について説明する。この場合には、不透明基板10の
上に前述した金属粉末を含有した樹脂がスクリーン印刷
され、第一の電極層12として裏面電極層が形成される
0次に、裏面電極層(12)の上に前述と同様にしてア
モルファスシリコン系半導体層14が被着され、更に第
二の電極層16として透明電極層が被着され、アモルフ
ァスシリコン系半導体装置が製造される。Next, a case where the insulating substrate 10 is an opaque substrate such as metal foil will be described. In this case, the resin containing the metal powder described above is screen printed on the opaque substrate 10, and then the back electrode layer (12) is formed as the first electrode layer 12. Then, an amorphous silicon semiconductor layer 14 is deposited in the same manner as described above, and a transparent electrode layer is further deposited as a second electrode layer 16, thereby manufacturing an amorphous silicon semiconductor device.
ここで、アモルファスシリコン系半導体層14を被着さ
せるのに伴って発生する熱によって、アモルファスシリ
コン系半導体114のアモルファスシリコンと第一の電
極層12の金属とはオーミック接合させられるが、さら
に熱処理をしてオーミック接合が確実に得られるように
するのが望ましい。Here, the amorphous silicon of the amorphous silicon semiconductor 114 and the metal of the first electrode layer 12 are brought into ohmic contact by the heat generated when the amorphous silicon semiconductor layer 14 is deposited. It is desirable to ensure that ohmic contact is obtained.
以上、本発明の実施例を詳述したが、本発明はその他の
形態で実施することが可能であり、たとえば、アモルフ
ァスシリコン系半導体素子18のパターンは図面に示す
形状に限定されるものではなく、種々の形態を採り得る
ものである。Although the embodiments of the present invention have been described in detail above, the present invention can be implemented in other forms. For example, the pattern of the amorphous silicon semiconductor element 18 is not limited to the shape shown in the drawings. , which can take various forms.
また、絶縁基板上に形成されるアモルファスシリコン系
半導体素子は1つでも良く、また前述の例に示すように
複数のアモルファスシリコン系半導体素子を形成して、
必要な起電力を得るため、それらのアモルファスシリコ
ン系半導体素子の第一の電極層と隣接する第二の電極層
とを接続して、複数のアモルファスシリコン系半導体素
子が直列に接続されたアモルファスシリコン系半導体装
置を得るようにしても良い。Further, the number of amorphous silicon semiconductor elements formed on the insulating substrate may be one, or as shown in the above example, a plurality of amorphous silicon semiconductor elements may be formed.
In order to obtain the necessary electromotive force, a plurality of amorphous silicon semiconductor elements are connected in series by connecting the first electrode layer and the adjacent second electrode layer of the amorphous silicon semiconductor elements. Alternatively, a system semiconductor device may be obtained.
その他、本発明はその趣旨を逸脱しない範囲内で、当業
者の知識に基づき種々なる変形、修正。In addition, the present invention may be subjected to various modifications and modifications based on the knowledge of those skilled in the art without departing from the spirit thereof.
改良を加えた態様で実施し得るものである。It can be implemented in an improved manner.
災履凱−工
絶縁基板として1.1m+IrIJ−のソーダライムガ
ラスを使用し、そのガラス基板の上にITOをスパッタ
ーにより300人(表面抵抗80Ω/口、透過率80%
;550r+m)被着させた後、第1図に示す所定の4
直列セルにエツチングパターンした。A 1.1m+IrIJ- soda lime glass was used as an insulating substrate, and ITO was sputtered onto the glass substrate by 300 people (surface resistance 80Ω/hole, transmittance 80%).
;550r+m) After depositing, the prescribed 4 as shown in FIG.
An etching pattern was made on the series cells.
次に、透明電極が被着されたガラス基板の上に、グロー
放電によりアモルファスシリコンをpm。Next, amorphous silicon was deposited on the glass substrate covered with the transparent electrode by glow discharge.
iN、n層の順にそれぞれ150人、5500人。150 people and 5,500 people for iN and n-tier, respectively.
300人、金属マスクにより被着した0次いで、被着さ
れたアモルファスシリコン系半導体層の上にニッケルペ
ーストを5US250メツシユのスクリーン製版を用い
て印刷した後、160°C,60分で硬化させて、裏面
電極を形成した。裏面電極の膜厚は20μmであった。Next, nickel paste was printed on the deposited amorphous silicon semiconductor layer using a 5US 250 mesh screen plate, and then cured at 160°C for 60 minutes. A back electrode was formed. The film thickness of the back electrode was 20 μm.
更に、得られたアモルファスシリコン系半導体装置を1
80°C130分の条件で熱処理して、アモルファスシ
リコン系半導体層のアモルファスシリコンと裏面電極の
金属粉末とのオーミック接合が充分得られるようにした
。Furthermore, the obtained amorphous silicon semiconductor device was
Heat treatment was performed at 80° C. for 130 minutes to ensure sufficient ohmic contact between the amorphous silicon of the amorphous silicon semiconductor layer and the metal powder of the back electrode.
ここで、ニッケルペーストは次のようにして作成した。Here, the nickel paste was created as follows.
先ずエポキシ樹脂(エピコート828)に対し、硬化剤
として酸無水物を50%を加え、更に粘度調整のため3
0%のセラソルブアセテートを加え、更にレベリング剤
(日本ユニ力A187)を1%、消泡剤(東芝シリコー
ン SH200)を1%加えて、バインダーとなる樹脂
を得た。First, 50% acid anhydride was added as a hardening agent to the epoxy resin (Epicoat 828), and 3% was added to adjust the viscosity.
0% Cerasolve Acetate was added, and further 1% of a leveling agent (Nippon Uniriki A187) and 1% of an antifoaming agent (Toshiba Silicone SH200) were added to obtain a resin to serve as a binder.
次に、金属粉末として、有機酸塩分解による粒径lum
以下のニッケルNiの粉末(冑純度化学■、品番811
0101 )を得られた樹脂に対して300%重量の割
合で混ぜた後、それを三本ロールを用いて隙間0.02
m5+で3回パスさせて混練した後、真空脱泡して、ニ
ッケルペーストを作成した。Next, as a metal powder, particle size lum is determined by organic acid salt decomposition.
The following nickel Ni powder (Kujunyu Kagaku ■, product number 811
0101) was mixed at a ratio of 300% by weight to the resin obtained, and then rolled using three rolls with a gap of 0.02
After kneading with m5+ for three passes, vacuum defoaming was performed to prepare a nickel paste.
得られたアモルファスシリコン系半導体装置について性
能試験を行った。このアモルファスシリコン系半導体装
置の受光面積は1.6cm”であった。A performance test was conducted on the obtained amorphous silicon semiconductor device. The light receiving area of this amorphous silicon semiconductor device was 1.6 cm''.
F L5Q luxの下で、短絡電流はl5c=6.8
1!^/c醜”+開放電圧はVoc・2.50V、フィ
ルファクタはFF= 62%であり、出力は10.5a
Hであった。Under F L5Q lux, the short circuit current is l5c=6.8
1! ^/c Ugly” + open circuit voltage is Voc・2.50V, fill factor is FF=62%, output is 10.5a
It was H.
結果を第1表に示す。The results are shown in Table 1.
ル較炭−上
比較のため、実施例1と同様にしてガラス基板上に透明
電極とアモルファスシリコン系半導体層とを被着させた
後、裏面電極層としてアルミニウム^lを蒸着させて、
アモルファスシリコン系半導体装置を得た。受光面積は
1.6cm”であった。FL50 luxの下で、短絡
電流は1sc=6.8 μA/C11−開放電圧はVo
c=2−45LフイルフアクタはFF−60%であり、
出力はlO3θμ匈であった。For comparison, a transparent electrode and an amorphous silicon semiconductor layer were deposited on a glass substrate in the same manner as in Example 1, and then aluminum was deposited as a back electrode layer.
An amorphous silicon based semiconductor device was obtained. The light receiving area was 1.6 cm". Under FL50 lux, the short circuit current was 1sc = 6.8 μA/C11 - the open circuit voltage was Vo
c=2-45L film factor is FF-60%,
The output was lO3θμ.
結果を第1表に示す。The results are shown in Table 1.
第1表
実施例1と同様にして得られた樹脂に対して、粒径50
μm以下のニッケル粉末を重量で10倍添加して混練し
、ニッケルペーストを作成した。Table 1 For the resin obtained in the same manner as Example 1, the particle size was 50.
A nickel paste was prepared by adding and kneading 10 times the weight of nickel powder having a size of 10 μm or less.
このニッケルペーストを用いて、実施例1と同様の条件
でアモルファスシリコン系半導体装置を製造した。ただ
し、本例においては、実施例1において行った裏面電極
の形成後の熱処理(180℃。Using this nickel paste, an amorphous silicon semiconductor device was manufactured under the same conditions as in Example 1. However, in this example, the heat treatment (180° C.) after the formation of the back electrode was performed in Example 1.
30分)を施さなかった1得られた裏面電極層のニッケ
ルの粒径を走査型顕微鏡で観察したところ、平均粒径1
0μm、最大50μmであり、はぼ球状であった。When the particle size of nickel in the obtained back electrode layer was observed with a scanning microscope, the average particle size was 1.
The diameter was 0 μm, the maximum was 50 μm, and the shape was spherical.
得られたアモルファスシリコン系半導体装置について性
能試験を行った結果、受光面積1.6cm”。A performance test was conducted on the obtained amorphous silicon semiconductor device, and the result was that the light receiving area was 1.6 cm.
F L50 luxの下で、短絡電流はl5c=6.7
u A/cm”+開放電圧はVoc・2.20V、フ
ィルファクタはFF・48%であった。Under F L50 lux, the short circuit current is l5c=6.7
u A/cm''+open circuit voltage was Voc·2.20V, and fill factor was FF·48%.
結果を第2表に示す。The results are shown in Table 2.
叉旌±−主
粒径がlpm以下のニッケルを用いて、実施例2と同じ
条件でアモルファスシリコン系半導体装置を得た。なお
、本例においても、実施例2と同様に得られたアモルフ
ァスシリコン系半導体装置について、熱処理を施さなか
った。An amorphous silicon-based semiconductor device was obtained under the same conditions as in Example 2 using nickel having a main grain size of lpm or less. Note that in this example as well, the amorphous silicon-based semiconductor device obtained in the same manner as in Example 2 was not subjected to heat treatment.
そのアモルファスシリコン系半導体装置について性能試
験を行った結果、受光面積1.6 cm”、 F L5
0 luxの下で、短絡電流はl5c=6.7 μA/
cg+”、開放電圧はVoc・2.30V、フィルファ
クタはFF・53%であった。As a result of performance tests on the amorphous silicon semiconductor device, the light receiving area was 1.6 cm", F L5
Under 0 lux, the short circuit current is l5c = 6.7 μA/
cg+”, the open circuit voltage was Voc·2.30V, and the fill factor was FF·53%.
結果を第2表に示す。The results are shown in Table 2.
第2表
実施例2及び実施例3で用いたアモルファスシリコン系
半導体装置で屋外用の装置を作成して、比較したところ
、ニッケルの粒径による差は認められなかった。このこ
とは屋外用のアモルファスシリコン系半導体装置は発電
電流が大きく、リーク電流(並列抵抗成分の電流)の影
響を受けにくいためと考えられる。When an outdoor device was made using the amorphous silicon semiconductor devices used in Example 2 and Example 3 of Table 2 and compared, no difference was observed depending on the particle size of nickel. This is thought to be because outdoor amorphous silicon semiconductor devices generate a large current and are less susceptible to leakage current (current of parallel resistance components).
かかる本発明は裏面電極層となる第一の電極層又は第二
の電極層を、金属粉末を含有させた樹脂にて形成するよ
うにしているため、スクリーン印刷することが可能とな
り、生産性が向上するとともに、生産コストを下げるこ
とが可能となる。In the present invention, the first electrode layer or the second electrode layer, which serves as the back electrode layer, is formed of resin containing metal powder, so screen printing is possible and productivity is improved. It is possible to improve the performance and reduce production costs.
また、従来の蒸着法と異なり、蒸着時の金属の突沸によ
ってアモルファスシリコン系半導体層が破壊されること
はないため、不良品が少なくなる。Furthermore, unlike conventional vapor deposition methods, the amorphous silicon semiconductor layer is not destroyed by metal bumping during vapor deposition, resulting in fewer defective products.
しかも、低温での熱処理によりアモルファスシリコン系
半導体層のアモルファスシリコンと裏面電11iNの金
属とがオーミック接合させられ、電気的にも又機械的に
も優れた接合が得られ、品質の優れたアモルファスシリ
コン系半導体装置が得られるなど、本発明は優れた効果
を奏する。Furthermore, heat treatment at low temperatures creates ohmic contact between the amorphous silicon of the amorphous silicon semiconductor layer and the 11iN metal on the back surface, resulting in an excellent bond both electrically and mechanically, resulting in high-quality amorphous silicon. The present invention has excellent effects such as the ability to obtain a system semiconductor device.
【図面の簡単な説明】
第1図は本発明に係るアモルファスシリコン系半導体装
置及びその製造方法を説明するための平面図であり、第
2図は第1図の要部正面断面図である。
第3図は従来のアモルファスシリコン系半導体装置の製
造方法を説明するため、アモルファスシン系半導体装置
の構成を示す説明図である。
;絶縁基板
;第一の電極層
;アモルファスシリコン系半導体層
;第二の電極層
;アモルファスシリコン系半導体素子
;取り出し電極
第1図
特許出願人 鐘淵化学工業株式会社
第3図BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view for explaining an amorphous silicon-based semiconductor device and a manufacturing method thereof according to the present invention, and FIG. 2 is a front cross-sectional view of a main part of FIG. 1. FIG. 3 is an explanatory diagram showing the structure of an amorphous thin semiconductor device in order to explain a conventional method of manufacturing an amorphous silicon semiconductor device. ; Insulating substrate; First electrode layer; Amorphous silicon-based semiconductor layer; Second electrode layer; Amorphous silicon-based semiconductor element; Take-out electrode Figure 1 Patent applicant Kanekabuchi Chemical Co., Ltd. Figure 3
Claims (5)
コン系半導体層及び第二の電極層を順次積層して構成さ
れたアモルファスシリコン系半導体素子が少なくとも1
つ形成されたアモルファスシリコン系半導体装置におい
て、前記第一の電極層又は第二の電極層が金属粉末を含
有する樹脂層からなることを特徴とするアモルファスシ
リコン系半導体装置。(1) At least one amorphous silicon-based semiconductor element is configured by sequentially laminating a first electrode layer, an amorphous silicon-based semiconductor layer, and a second electrode layer on an insulating substrate.
1. An amorphous silicon-based semiconductor device in which the first electrode layer or the second electrode layer is made of a resin layer containing metal powder.
ンTi又はモリブデンMoであることを特徴とする請求
項第1項に記載のアモルファスシリコン系半導体装置。(2) The amorphous silicon semiconductor device according to claim 1, wherein the metal powder is nickel Ni, chromium Cr, titanium Ti, or molybdenum Mo.
特徴とする請求項第1項又は第2項に記載のアモルファ
スシリコン系半導体装置。(3) The amorphous silicon semiconductor device according to claim 1 or 2, wherein the metal powder has a particle size of 50 μm or less.
コン系半導体素子の各起電力が直列になるように第一の
電極層と隣接する第二の電極層とを接続したことを特徴
とする請求項第1項乃至第3項のいずれかに記載のアモ
ルファスシリコン系半導体装置。(4) A claim characterized in that the first electrode layer and the adjacent second electrode layer are connected so that the electromotive forces of the plurality of amorphous silicon semiconductor elements formed on the insulating substrate are connected in series. The amorphous silicon semiconductor device according to any one of Items 1 to 3.
ン系半導体層と裏面電極層とを順次積層して成るアモル
ファスシリコン系半導体素子が1又は複数形成されたア
モルファスシリコン系半導体装置を製造する方法におい
て、 金属粉末を含有する樹脂を所定のパターンに印刷して前
記裏面電極層を形成する工程と、 前記裏面電極層が印刷された工程品に熱処理を施す工程
と を含むことを特徴とするアモルファスシリコン系半導体
装置の製造方法。(5) A method for manufacturing an amorphous silicon-based semiconductor device in which one or more amorphous silicon-based semiconductor elements are formed by sequentially laminating a transparent electrode layer, an amorphous silicon-based semiconductor layer, and a back electrode layer on an insulating substrate. , an amorphous silicon characterized by comprising: a step of printing a resin containing metal powder in a predetermined pattern to form the back electrode layer; and a step of heat-treating the process product on which the back electrode layer is printed. A method for manufacturing a semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63157746A JPH027476A (en) | 1988-06-26 | 1988-06-26 | Amorphous silicon semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63157746A JPH027476A (en) | 1988-06-26 | 1988-06-26 | Amorphous silicon semiconductor device and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH027476A true JPH027476A (en) | 1990-01-11 |
Family
ID=15656443
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63157746A Pending JPH027476A (en) | 1988-06-26 | 1988-06-26 | Amorphous silicon semiconductor device and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH027476A (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02117177A (en) * | 1988-10-26 | 1990-05-01 | Fuji Electric Co Ltd | Thin film optoelectric transducer |
WO2008130031A1 (en) * | 2007-04-19 | 2008-10-30 | Mitsubishi Materials Corporation | Conductive reflecting film and method for manufacturing the same |
WO2009035112A1 (en) * | 2007-09-12 | 2009-03-19 | Mitsubishi Materials Corporation | Composite membrane for super straight solar cell, process for producing the composite membrane for super straight solar cell, composite membrane for substraight solar cell, and process for producing the composite membrane for substraight solar cell |
JP2009088489A (en) * | 2007-09-12 | 2009-04-23 | Mitsubishi Materials Corp | Composite film for super straight type thin film solar battery and method of manufacturing the same |
JP2010087480A (en) * | 2008-08-08 | 2010-04-15 | Mitsubishi Materials Corp | Composite film for substraight type solar cell and method of manufacturing the same |
WO2013136424A1 (en) * | 2012-03-13 | 2013-09-19 | 三洋電機株式会社 | Solar cell module |
US8816193B2 (en) | 2006-06-30 | 2014-08-26 | Mitsubishi Materials Corporation | Composition for manufacturing electrode of solar cell, method of manufacturing same electrode, and solar cell using electrode obtained by same method |
US8822814B2 (en) | 2006-10-11 | 2014-09-02 | Mitsubishi Materials Corporation | Composition for electrode formation and method for forming electrode by using the composition |
-
1988
- 1988-06-26 JP JP63157746A patent/JPH027476A/en active Pending
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02117177A (en) * | 1988-10-26 | 1990-05-01 | Fuji Electric Co Ltd | Thin film optoelectric transducer |
US9620668B2 (en) | 2006-06-30 | 2017-04-11 | Mitsubishi Materials Corporation | Composition for manufacturing electrode of solar cell, method of manufacturing same electrode, and solar cell using electrode obtained by same method |
US9312404B2 (en) | 2006-06-30 | 2016-04-12 | Mitsubishi Materials Corporation | Composition for manufacturing electrode of solar cell, method of manufacturing same electrode, and solar cell using electrode obtained by same method |
US8816193B2 (en) | 2006-06-30 | 2014-08-26 | Mitsubishi Materials Corporation | Composition for manufacturing electrode of solar cell, method of manufacturing same electrode, and solar cell using electrode obtained by same method |
US8822814B2 (en) | 2006-10-11 | 2014-09-02 | Mitsubishi Materials Corporation | Composition for electrode formation and method for forming electrode by using the composition |
WO2008130031A1 (en) * | 2007-04-19 | 2008-10-30 | Mitsubishi Materials Corporation | Conductive reflecting film and method for manufacturing the same |
JP2008288568A (en) * | 2007-04-19 | 2008-11-27 | Mitsubishi Materials Corp | Conductive reflecting film and method of manufacturing the same |
US10020409B2 (en) | 2007-04-19 | 2018-07-10 | Mitsubishi Materials Corporation | Method for producing a conductive reflective film |
US8758891B2 (en) | 2007-04-19 | 2014-06-24 | Mitsubishi Materials Corporation | Conductive reflective film and production method thereof |
WO2009035112A1 (en) * | 2007-09-12 | 2009-03-19 | Mitsubishi Materials Corporation | Composite membrane for super straight solar cell, process for producing the composite membrane for super straight solar cell, composite membrane for substraight solar cell, and process for producing the composite membrane for substraight solar cell |
US8921688B2 (en) | 2007-09-12 | 2014-12-30 | Mitsubishi Materials Corporation | Composite film for superstrate solar cell having conductive film and electroconductive reflective film formed by applying composition containing metal nanoparticles and comprising air pores of preset diameter in contact surface |
JP2009088489A (en) * | 2007-09-12 | 2009-04-23 | Mitsubishi Materials Corp | Composite film for super straight type thin film solar battery and method of manufacturing the same |
JP2010087480A (en) * | 2008-08-08 | 2010-04-15 | Mitsubishi Materials Corp | Composite film for substraight type solar cell and method of manufacturing the same |
WO2013136424A1 (en) * | 2012-03-13 | 2013-09-19 | 三洋電機株式会社 | Solar cell module |
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