JPH0273708A - Fet circuit - Google Patents
Fet circuitInfo
- Publication number
- JPH0273708A JPH0273708A JP22462188A JP22462188A JPH0273708A JP H0273708 A JPH0273708 A JP H0273708A JP 22462188 A JP22462188 A JP 22462188A JP 22462188 A JP22462188 A JP 22462188A JP H0273708 A JPH0273708 A JP H0273708A
- Authority
- JP
- Japan
- Prior art keywords
- fet
- signal
- resistor
- amplitude
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 5
- 101100119059 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) ERG25 gene Proteins 0.000 description 4
- 101150079361 fet5 gene Proteins 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
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- Networks Using Active Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は高周波回路に係り、特に不平衡な入力信号を平
衡な出力信号に変換することに好適なＦＥＴ回路に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high frequency circuit, and particularly to an FET circuit suitable for converting an unbalanced input signal into a balanced output signal.
不平衡信号を平衡信号に変換する従来のＦＥＴ回路は、
特開昭６０−９６９０６号公報に記載のように、２個の
ＦＥＴを差動型に配置してそれぞれのＦＥＴのソースを
接続し、この接続点と接地電位との間に定電流源を接続
して、第１のＦＥＴのゲートに不平衡の信号を入力し、
第２のＦＥＴのゲートにコンデンサを接続して高周波的
に接地することにより、第１のＦＥＴのドレインと第２
のはＦＥＴのドレインから平衡信号を得ている。A conventional FET circuit that converts an unbalanced signal into a balanced signal is
As described in Japanese Unexamined Patent Publication No. 60-96906, two FETs are arranged in a differential type, the sources of each FET are connected, and a constant current source is connected between this connection point and the ground potential. and input an unbalanced signal to the gate of the first FET,
By connecting a capacitor to the gate of the second FET and grounding it at high frequency, the drain of the first FET and the second
The balanced signal is obtained from the drain of the FET.
上記従来技術では、差動型ＦＥＴのゲートに直流電圧を
加えて動作させるために、不平衡信号入力の場合に入力
端子の一方をコンデンサを介して高周波的に接地しなけ
ればならなので、ＩＣ回路に用いる場合にはコンデンサ
が大きな面積を占有し、ＩＣの外部に付加する場合は回
路の素子数とＩＣの端子数の増加となる問題があった。In the above conventional technology, in order to operate the differential FET by applying a DC voltage to its gate, one of the input terminals must be grounded at high frequency via a capacitor in the case of an unbalanced signal input, so the IC circuit When used in the IC, the capacitor occupies a large area, and when added outside the IC, there is a problem in that the number of circuit elements and the number of terminals of the IC increase.
本発明の目的は、不平衡な高周波入力信号に対して、高
周波の入力されない一方の端子をコンデンサを介して接
地せずに平衡な信号を発生させるＦＥＴ回路の簡略化に
ある。An object of the present invention is to simplify an FET circuit that generates a balanced signal in response to an unbalanced high-frequency input signal without grounding one terminal to which no high-frequency signal is input via a capacitor.
上記目的は、従来高周波的に接地している第２のＦＥＴ
のゲートを直流的に零電位にしても動作するように定電
流源を取り去り、第２のＦＥＴのソースに入力信号が伝
達する構成とすることで達成できる。The above purpose is to replace the second FET which is conventionally grounded at high frequency.
This can be achieved by removing the constant current source so as to operate even when the gate of the FET is set to zero DC potential, and by configuring the input signal to be transmitted to the source of the second FET.
不平衡入力端子の一方を直接接地して平衡出力信号を発
生させるＦＥＴ回路は、信号が入力される第１のＦＥＴ
のゲート電圧がほぼ零電位となるので、第１のＦＥＴの
ソース電位と第２のＦＥＴのソース電位を低く保ち、第
１のＦＥＴのゲートと第２のＦＥＴのソースを接続する
回路構成とすることで、不平衡入力信号が第１のＦＥＴ
のゲートと第２のＦＥＴのソースに加わり、第１のＦＥ
Ｔのゲートに加わった信号は、第１のＦＥＴのドレイン
に逆相で発生し、第２のＦＥＴのソースに加わった信号
は、第２のＦＥＴのトレインに同相で発生するので、平
衡信号を発生させることができる。A FET circuit that generates a balanced output signal by directly grounding one of its unbalanced input terminals has a first FET to which the signal is input.
Since the gate voltage of the FET becomes almost zero potential, the source potential of the first FET and the source potential of the second FET are kept low, and the circuit configuration is such that the gate of the first FET and the source of the second FET are connected. This allows the unbalanced input signal to be applied to the first FET.
to the gate of the first FET and the source of the second FET.
The signal applied to the gate of T is generated in opposite phase to the drain of the first FET, and the signal applied to the source of the second FET is generated in phase to the train of the second FET, creating a balanced signal. can be generated.
以下、本発明の一実施例を第１図により説明する。１は
高周波信号入力端子、２及び３は高周波信号平衡出力端
子、４は正の直流電圧印加端子、５及び６はデプレショ
ン型ＦＥＴ、７及び８はドレイン負荷抵抗、９及び１０
はソース抵抗、１２はゲート抵抗、１３が高周波信号伝
達用抵抗である。端子１に印加された高周波信号はＦＥ
Ｔ５のゲートに加わり、端子２に入力信号と逆位相の信
号が生しる。又、端子１に印加された高周波信号は抵抗
１３と抵抗１２により分圧されてＦＥＴ６のソースに゛
印加される。ＦＥＴ６のゲートは抵抗１２により直流的
にほぼ零電位であるので、ＦＥＴ６のソースに印加され
た信号は端子３に同相で発生される。ＦＥＴ５は、ゲー
トに印加された信号の振幅値に対して、ソースが同位相
で変化する振幅幅との差によって動作電流値が変化し、
抵抗７の電圧降下によりドレイン電圧が変化し、出力端
子２の振幅値を決める動作をする。ＦＥＴ６は。An embodiment of the present invention will be described below with reference to FIG. 1 is a high frequency signal input terminal, 2 and 3 are high frequency signal balanced output terminals, 4 is a positive DC voltage application terminal, 5 and 6 are depletion type FETs, 7 and 8 are drain load resistors, 9 and 10
1 is a source resistance, 12 is a gate resistance, and 13 is a high frequency signal transmission resistance. The high frequency signal applied to terminal 1 is FE
It is added to the gate of T5, and a signal with the opposite phase to the input signal is generated at terminal 2. Further, the high frequency signal applied to the terminal 1 is divided by the resistors 13 and 12 and applied to the source of the FET 6. Since the gate of the FET 6 is at approximately zero DC potential due to the resistor 12, the signal applied to the source of the FET 6 is generated at the terminal 3 in the same phase. In FET5, the operating current value changes depending on the difference between the amplitude value of the signal applied to the gate and the amplitude width that changes with the source in the same phase.
The drain voltage changes due to the voltage drop across the resistor 7, which determines the amplitude value of the output terminal 2. FET6 is.
ゲートが抵抗１２を介して接地されているため、ソース
に加えられた信号の振幅値で動作電流が変化して、抵抗
８の電圧降下によりドレイン電圧が変化し、出力端子３
の振幅値を決める動作をする。Since the gate is grounded through the resistor 12, the operating current changes depending on the amplitude value of the signal applied to the source, and the drain voltage changes due to the voltage drop across the resistor 8.
The action is to determine the amplitude value of.
ＦＥＴ５のゲート入力信号とＦＥＴ６のソース入力信号
の振幅値を変えることにより端子２と端子３の出力信号
の振幅値を一致させることができるので、抵抗１３によ
りＦＥＴ５とＦＥＴ６の入力信号の振幅値を変えて、端
子２と端子３に平衡信号を発生させる。本実施例によれ
ば、高周波信号を端子１に加えると端子２と端子３から
振幅が等しく位相が反転された信号が発生するため、不
平衡信号を平衡信号に変換する回路となり、入力の直流
電位を低くでき、回路の簡略化の効果がある。By changing the amplitude values of the gate input signal of FET 5 and the source input signal of FET 6, the amplitude values of the output signals of terminals 2 and 3 can be made to match. Instead, balanced signals are generated at terminals 2 and 3. According to this embodiment, when a high frequency signal is applied to terminal 1, signals with equal amplitude and inverted phase are generated from terminals 2 and 3, so that the circuit converts an unbalanced signal into a balanced signal, and the input DC current This has the effect of simplifying the circuit.
第２図は、本発明の別の実施例を示す回路図で、１は高
周波信号入力端子、２及び３は高周波信号出力端子、４
は正の直流電圧印加端子、５及び６はデプレション型Ｆ
ＥＴ、７及び８はドレイン負荷抵抗、９及び１ｏはソー
ス抵抗である。端子１に入力された高周波信号は、ＦＥ
Ｔ５のゲートに印加され、端子２に位相が反転された信
号に変換される。さらに入力された高周波信号はＦＥＴ
６のソースに印加され、端子３に同相な信号に変化され
る。ＦＥＴ５のソースとＦＥＴ６のゲートが接続されて
いるため、入力信号に対して同じ振幅で電圧変化し、Ｆ
ＥＴ５とＦＥＴ６の動作電流の変化量は同じになり、抵
抗７と抵抗８が等しい抵抗値の場合に端子３の端子４に
平衡信号が出力される。更に、ＦＥＴ６のゲートに信号
を入力された場合も同様に平衡信号が得られる。本実施
例によれば、ＦＥＴ５のゲート入力信号の振幅とＦＥＴ
５のソース出力信号の振幅が一致しない場合に。FIG. 2 is a circuit diagram showing another embodiment of the present invention, in which 1 is a high frequency signal input terminal, 2 and 3 are high frequency signal output terminals, and 4 is a high frequency signal input terminal.
is a positive DC voltage application terminal, 5 and 6 are depletion type F
ET, 7 and 8 are drain load resistances, and 9 and 1o are source resistances. The high frequency signal input to terminal 1 is FE
The signal is applied to the gate of T5 and is converted to a signal whose phase is inverted at terminal 2. Furthermore, the input high frequency signal is sent to the FET
6 and is changed into a signal that is in phase with terminal 3. Since the source of FET5 and the gate of FET6 are connected, the voltage changes with the same amplitude with respect to the input signal, and the FET
The amount of change in the operating current of ET5 and FET6 becomes the same, and a balanced signal is output to terminal 4 of terminal 3 when resistor 7 and resistor 8 have the same resistance value. Furthermore, when a signal is input to the gate of FET 6, a balanced signal can be obtained in the same way. According to this embodiment, the amplitude of the gate input signal of FET5 and the FET
5 when the amplitudes of the source output signals do not match.
端子２と端子３から平衡変換された信号を取り出せる効
果がある。This has the effect that balanced converted signals can be taken out from terminals 2 and 3.
第３図は１本発明の別の実施例を示す回路図で。FIG. 3 is a circuit diagram showing another embodiment of the present invention.
１は高周波信号入力端子、２及び３は高周波信号出力端
子、４は正の直流電圧印加端子、５及び６はデプレショ
ン型ＦＥＴ、７及び８はドレイン負荷抵抗、９及び１ｏ
はソース抵抗、１１及び１２はゲート抵抗、１４は定電
流源用抵抗、ＩＳは定電流源用デプレション型ＦＥＴで
ある。抵抗１４とＦＥＴ１５で定電流源を構成し、ＦＥ
Ｔ５とＦＥＴ６に流れる電流の合計量を一定に保つ。端
子１に高周波信号を印加させると、ＦＥＴ５のゲート電
圧が変化して動作電流が変化するので、端子２に同相の
信号が出力される。ＦＥＴ５の動作電流の変化は、定電
流源によりＦＥＴ６の動作電流を逆相で変化させること
になり、端子３より入力信号の逆相の信号を発生させる
ことができる。定電流源用ＦＥＴ１５のゲート電圧は、
入力信号の振幅により抵抗７を介して変化するが、抵抗
１４によりＦＥＴ１５のソース電位も同様に変化するの
で、ＦＥＴ１５の動作電流は変わらない。本実施例によ
れば、不平衡信号を平衡信号に変化させることができ、
入力と出力の直流電位がほぼ零電位となり、ゲートバイ
アス印加用回路が不要で回路の簡略化となる効果がある
。1 is a high frequency signal input terminal, 2 and 3 are high frequency signal output terminals, 4 is a positive DC voltage application terminal, 5 and 6 are depletion type FETs, 7 and 8 are drain load resistances, 9 and 1o
is a source resistance, 11 and 12 are gate resistances, 14 is a constant current source resistance, and IS is a constant current source depletion type FET. The resistor 14 and FET 15 constitute a constant current source, and the FE
The total amount of current flowing through T5 and FET6 is kept constant. When a high frequency signal is applied to terminal 1, the gate voltage of FET 5 changes and the operating current changes, so that an in-phase signal is output to terminal 2. The change in the operating current of the FET 5 causes the operating current of the FET 6 to change in the opposite phase by a constant current source, and a signal with the opposite phase of the input signal can be generated from the terminal 3. The gate voltage of constant current source FET 15 is
Although it changes via the resistor 7 depending on the amplitude of the input signal, the source potential of the FET 15 similarly changes due to the resistor 14, so the operating current of the FET 15 does not change. According to this embodiment, an unbalanced signal can be changed to a balanced signal,
The direct current potential of the input and output becomes almost zero potential, which eliminates the need for a gate bias application circuit and has the effect of simplifying the circuit.
本発明によれば、ＦＥＴを用いて不平衡の信号を平衡信
号に変換する場合に、入力端子の一方を高周波接地用コ
ンデンサで接地せずに平衡信号が得られるので、集積化
に対し回路の簡略化となる効果がある。According to the present invention, when converting an unbalanced signal into a balanced signal using a FET, a balanced signal can be obtained without grounding one of the input terminals with a high-frequency grounding capacitor. This has the effect of simplification.
第１図は本発明の一実施例の平衡変換ＦＥＴ回路図、第
２図は本発明の別の実施例を示すＦＥＴ回路図、第３図
は本発明の別の実施例を示すＦＥＴ回路図である。
１・・信号入力端子、２，３・・・信号出力端子、４・
・・電源端子、５，６・・・ＦＥＴ、７〜１４・・・抵
抗。
１５・・・定電流源用ＦＥＴ。
躬 １ 閃
策 ３Ｚ
躬２図FIG. 1 is a balanced conversion FET circuit diagram of one embodiment of the present invention, FIG. 2 is a FET circuit diagram of another embodiment of the present invention, and FIG. 3 is a FET circuit diagram of another embodiment of the present invention. It is. 1... Signal input terminal, 2, 3... Signal output terminal, 4...
...Power terminal, 5, 6...FET, 7-14...Resistance. 15... FET for constant current source. Mitsu 1 Sensaku 3Z Mitsu 2 diagram
Claims (1)
に第１の抵抗を接続し、第１のＦＥＴのソース電極と接
地電位との間に第２の抵抗を接続し、第１のＦＥＴのゲ
ート電極と第２のＦＥＴのソース電極との間に第３の抵
抗を接続し、第２のＦＥＴのドレイン電極と正の電源端
子との間に第４の抵抗を接続し、第２のＦＥＴのソース
電極と接地電位との間に第５の抵抗を接続し、第２のＦ
ＥＴのゲート電極と接地電位との間に第６の抵抗を接続
した構成において、第１のＦＥＴのゲート電極に信号入
力端子を設け、第１のＦＥＴのドレイン電極と第２のＦ
ＥＴのドレイン電極に信号出力端子を設けたことを特徴
とするＦＥＴ回路。1. A first resistor is connected between the drain electrode of the first FET and the positive power supply terminal, a second resistor is connected between the source electrode of the first FET and the ground potential, and the first A third resistor is connected between the gate electrode of the FET and the source electrode of the second FET, a fourth resistor is connected between the drain electrode of the second FET and the positive power supply terminal, and a fourth resistor is connected between the drain electrode of the second FET and the positive power supply terminal. A fifth resistor is connected between the source electrode of the second FET and the ground potential, and the fifth resistor is connected between the source electrode of the second FET and the ground potential.
In a configuration in which a sixth resistor is connected between the gate electrode of the ET and the ground potential, a signal input terminal is provided at the gate electrode of the first FET, and a signal input terminal is connected between the drain electrode of the first FET and the second FET.
An FET circuit characterized in that a signal output terminal is provided at the drain electrode of the ET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22462188A JPH0273708A (en) | 1988-09-09 | 1988-09-09 | Fet circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22462188A JPH0273708A (en) | 1988-09-09 | 1988-09-09 | Fet circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0273708A true JPH0273708A (en) | 1990-03-13 |
Family
ID=16816580
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22462188A Pending JPH0273708A (en) | 1988-09-09 | 1988-09-09 | Fet circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0273708A (en) |
-
1988
- 1988-09-09 JP JP22462188A patent/JPH0273708A/en active Pending
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