JPH0273443A - Input/output controller - Google Patents

Abstract

PURPOSE:To avoid the instantaneous increase of a data transfer speed by delaying the transmission timing of the request signal for the final byte date. CONSTITUTION:A final request detecting circuit 21 detects that the present output value of a transfer frequency counter 18 is equal to 1 and outputs a detecting signal to an input tag generating circuit 16. The circuit 16 produces an input tag and a final output tag and delays the transmission timing of the final input timing tag 103 so that the fetch timing of the final byte data is approximately equal to the fetch timing of each byte data. As a result, the interval between the fetch timing of the final data and that of the immediately preceding data is decreased and can be set at the value larger than the prescribed width. Thus it is possible to avoid the instantaneous increase of the data transfer speed for the final data.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to an input/output control device, and particularly to a transfer control technique for performing data transfer using a non-response acknowledgment method with a channel device.

(Prior Art) As is well known, an input/output control device is interposed between a channel device and an input/output device, and controls data transfer between the channel device and the input/output device. The input/output interface method between the input/output control device and the channel device can basically be classified into response confirmation method and non-response confirmation method.
The response confirmation method is a method in which data is exchanged while checking each other's response actions to one's own actions. On the other hand, the non-response confirmation method is a method in which data is exchanged without confirming the response operation of the other party, and the basic signal configuration is as shown in FIG. 3, for example.

In FIG. 3, the direction of data transfer is determined based on the channel device 1, so the signal going from the channel device 1 to the input/output control device 2 is output data +000° output tag 100.
1 and the final output tag 1002, and the signal going from the input/output control device 2 to the channel device 1 is the input data 2.
000, input tag 2001 and final input tag 2002
becomes. Data transfer is performed byte by byte, but input (output) tag 2001 (+00
1) is used, and the final input (output) tag 2002 (+002) is used when transferring the final byte. In addition,
The "tag" may be output in a certain relationship with the data sent onto the data bus, or may be output independently without data transmission. That is, the "tag" may be used as a so-called strobe signal or as a request signal.

A conventional transfer control method when the input/output control device 2 receives and receives data from the channel device 1 will be described below.

A conventional input/output control device is configured as shown in FIG. 4, for example. In Figure 4, 10.11 is the receiver, 1
2.13 is a driver, 14 is a receiver, 15 is a driver, 17 is a microprocessor, 19 is an output data register, 20 is an input data register, 36 is an input tag generation circuit, and 38 is a transfer number counter. Note that the channel device is not shown in FIG. 4 because it can be considered by using the input tag generation circuit 36 as an output tag generation circuit and reversing the input/output relationship between the tag and data.

In the above configuration, the microprocessor 17 sets the transfer number counter 38 to, for example, "3" as the number of bytes to be transferred, and also instructs the input tag generation circuit 36 to request output data transmission.

The transfer number counter 38 outputs the contents of the counter to the input tag generation circuit 36. Its value is input tag generation circuit 3
Each time a notification that an input tag has been generated is received from 6, 1 address is subtracted.

Since the command from the microprocessor 17 is a request to send output data, the input tag generation circuit 36 does not control the input data register 20, but keeps a predetermined pulse width until the output of the transfer number counter 38 becomes "1". Input tags are generated repeatedly at predetermined time intervals, and the final input tag is generated when the output of the transfer number counter 38 is "1". Switching between generation of input tags and final input tags is performed by gate control.

As a result, the input tag 132, which is the output of the driver 12, becomes as shown in FIG. 5(1), and the final input tag 133, which is the output of the driver 13, becomes as shown in FIG. 5(2). It is sent to the device and taken into the channel device with a slight time delay (Fig. 5 (3) (4>
>.

Then, in the channel device, the receiver is attached to the input tag (fifth
In addition to sending output data to the output data path in response to the final input tag (Fig. 5 (4))) and the final input tag (Fig. 5 (4)),
Generate corresponding output tags and final output tags, respectively. This output tag and the final output tag are shown in Figure 5 (6) (
7), the receiver 10. Same 1
1 and taken into the input tag generation circuit 36.

In this way, the input tag generation circuit 36 generates the output tag 130 (FIG. 5(6)) and the final output tag +31 (FIG. 5(6)).
In response to (7) in FIG. 5, the output data register 19 is controlled, and each byte of output data input via the receiver 14 is stored in the output data register 19 and stored therein.

In FIG. 5, the intervals T51, T52, T1, T2, T5'1, and Tg2 have approximately the same time width.

(Problem to be Solved by the Invention) By the way, even though the input (output) tag and the final input (output) tag are generated at the same location, the transmission systems are different. There may be a difference in the time interval for marking. Then, the direction of the shift is the fifth
As illustrated in Figures (5) and (8), the interval T2 and the same TJ
In the direction of reducing 2, a problem arises because the transfer rate of the final data increases instantaneously.

As shown in FIGS. 5(1) and (2>), the interval between the occurrence of the second input tag 132 and the final input tag 133 is originally an interval T, 2, which is approximately equal to the interval T, 1. However, due to the unequal characteristics of the drivers 13 and 14, the interval T52 may be narrower than the original one and sent to the interface line.In addition, even in the channel device, due to the unequal characteristics of the corresponding receivers, the input If the interval between the second tag and the final input tag shifts in the direction of narrowing, as shown in FIG. Since the reception is received ΔT earlier than that, the channel device sends the final byte data and the final output tag based on the final input tag shown in FIG. 5(5).

In addition, (a) in the input/output control device that receives the output tag, if the distance between the second output tag and the final output tag shifts in the direction of narrowing due to unequal characteristics of the corresponding receivers 10 and 11. Then, this deviation ΔT2 is added to the above ΔT1, and the final output tag that should originally be attached at the position of the interval T2 as shown in FIG. 5(7) becomes as shown in FIG. 5(8). As shown in FIG. Then, the input/output control device takes in the final byte data based on the final output tag 131' (FIG. 5 (8)) that was accepted earlier.
The time interval between the last output tag 13 and the immediately preceding output tag is much narrower than the time interval between other output tags, i.e. the data transfer rate increases instantaneously when the last byte of data is captured. This causes trouble in capturing the final byte data.

Therefore, in conventional input/output control devices, the so-called double buffer technology is used to distribute each byte of output data into odd-numbered and even-numbered data in order to secure a predetermined processing time for the final byte data. This allows for easy access to the site without any problems.

However, the circuit added in this way is expensive because it consists of multiple circuit elements and can operate at a certain level of high speed, and there is a problem that it is difficult to reduce the cost of the input/output control device. .

The present invention was developed in view of these conventional problems, and its purpose is to suppress the instantaneous increase in data transfer speed by delaying the sending timing of the final byte data request signal (final input tag). The purpose of this invention is to provide an input/output control device that can perform the following tasks.

(Means for Solving the Problems) In order to achieve the above object, the input/output control device of the present invention has the following configuration.

That is, the input/output control device of the present invention performs data transfer with a channel device using a non-response confirmation method, and sends n-1 data request signals to the channel device via the first transmission path. In the input/output control device which transmits one final data request signal via the second transmission path and thereby receives n data transmissions from the channel device; generation timing of the final data request signal; The present invention is characterized in that it includes: a detection means for detecting; and a delay means for delaying the sending timing of the final data request signal in response to the detection output of the detection means.

(Function) Next, the function of the input/output control device of the present invention configured as described above will be explained.

In the present invention, the final data request signal is sent after an appropriate time delay compared to the conventional method.

As a result, even if the interval between the final data acquisition timing and the immediately preceding data acquisition timing becomes narrow, the interval can be made larger than a predetermined width. In other words, it is possible to suppress the data transfer rate from increasing instantaneously at the time of final data.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an input/output control device according to an embodiment of the present invention. Parts that are the same as those in the prior art are given the same reference numerals and their explanations will be omitted.

In the present invention, the input tag generation circuit 1 has functions added to the final request detection circuit 21 and the conventional input tag generation circuit 36.
6 is provided. The only difference between the transfer number counter 18 and the conventional transfer number counter 38 is that it outputs the current value to the final request detection circuit 21.

The operation when receiving 3-byte output data from the channel device as in the conventional case will be described below.

When the final request detection circuit 21 detects that the current output value of the transfer number counter 18 becomes "1", it outputs a detection signal to the input tag generation circuit 16.

The input tag generation circuit 16 generates two input tags and a final input tag as in the conventional case, but the generation interval is as shown in FIG.
1) It becomes as shown in (2>. That is, the first and second input tags +02 occur with an interval T+ (which may be approximately equal to the conventional interval T51), but the occurrence of this second one After that, the detection signal is input, so the final input tag 103
occur with a larger interval T2 than the interval T.

As a result, the channel device can receive the input tag and the final input tag as shown in Figure 2 (3) and (4), but the final input tag is shifted by ΔT1 as shown in Figure 2 (5).
As mentioned above, applications may be received early.

Then, in the input/output control device, the final output tag is shown in Figure 2 (
As shown in 8), ΔT1+ deviates from the original interval T'2.
In the case where an acceptance is made early to T2, in the present invention, the interval between the second output tag +00 and the final output tag +01' is narrower than the interval T'i, but the interval between the first and second output tag 100 is narrower than the interval T'i. The distance is approximately equal to the second interval T″1.

In other words, the sending timing of the final input tag 103 is delayed so that the timing of taking in the final pie 1 data is approximately equal to the timing of taking in each previous byte data. Since each byte data has approximately the same timing, internal data processing can be facilitated.

Here, regarding the additional circuit, the final request detection circuit 21 only needs to detect when the current output value of the transfer number counter 18 becomes "1", so the configuration is simple, and the circuit elements have high speed. It is not necessary, and the input tag generation circuit 16 only delays the predetermined time. Therefore, this additional circuitry is significantly less expensive than conventional double buffer technology.

(Effects of the Invention) As explained above, according to the input/output control device of the present invention, the sending timing of the final data request signal (a final input tag) can be delayed, so that the final data capture timing and Even if the interval between the timings of fetching the immediately preceding data becomes narrow, the interval can be made greater than a predetermined width, and this has the effect of suppressing the instantaneous increase in the data transfer rate at the time of the final data.

Note that the additional circuit according to the present invention has a simple configuration and does not require high speed, so it can be configured at low cost, and has the effect of reducing the cost of the input/output control device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the configuration of an input/output control device according to an embodiment of the present invention, FIG. 2 is a time chart of output data transfer control according to the present invention, and FIG. FIG. 4 is a block diagram of a conventional input/output control device, and FIG. 5 is a time chart of conventional output data transfer control. DESCRIPTION OF SYMBOLS 1... Channel device, 2... Input/output control device, 10... Receiver, 11...
...Receiver, 12...Driver, 13
......driver, 14...receiver (plurality), 15...driver (plurality), 1
6... Input tag generation circuit, 17... Microprocessor, 18. Old... Transfer number counter,
19... Output data register, 20...
...Input data register, 2] ...Final request detection circuit.

Claims (1)

[Claims] This method performs data transfer with a channel device using a non-response confirmation method, in which n-1 data request signals are sent to the channel device via a first transmission path, and a second transmission path is transmitted to the channel device. In an input/output control device that transmits one final data request signal through the channel device and receives n data transmissions from the channel device; a detection means for detecting the generation timing of the final data request signal; An input/output control device comprising: delay means for delaying the sending timing of the final data request signal in response to a detection output.