JPH0273439A - Cache controller for auxiliary memory - Google Patents

Abstract

PURPOSE:To prevent the erasion of date at exchange of an ECC/memory control circuit by adding this control circuit to an auxiliary memory control part and supplying the power to a cache memory part and the auxiliary memory control part through the different power supply parts. CONSTITUTION:When an ECC/memory control circuit 121 has a trouble, no access is possible to a semiconductor memory element 111 from a host computer 300. As a result, the exchange is required for the circuit 121. When the circuit 121 is exchanged, the connection is cut off between a disk control part 120 and a power supply 125 before exchange od the circuit 121. Then the connection is secured between the part 120 and the part 125. The power is supplied continuously to the part 111 from a power supply part 115 even under such conditions. Thus it is possible to prevent the erasion of the data stored in the part 111.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a cache control device for an auxiliary storage device connected between a host computer and an auxiliary storage device.
In particular, the present invention relates to a cache control device for an auxiliary storage device characterized by a connection relationship between a cache memory section and a power supply section.

[Prior Art] FIG. 2 is a block diagram of a conventional cache control device for a magnetic disk drive including a cache memory section. Hereinafter, the cache control device for a magnetic disk device will be referred to as a disk cache control device.

This disk cache control device 400 includes a cache memory section 410 and a disk control section 420.

Cache memory section 410 includes a high-speed and volatile semiconductor memory element section 411 and an ECC/memory control circuit 412. The disk control unit 420 controls the magnetic disk device 20
0, cache memory section 410, and host computer 3
It includes a control circuit 421 that controls the exchange of information with 00.

The cache memory unit 410 includes a dedicated power supply unit 41.
5 is connected. The disk control unit 420 is also connected to a dedicated power supply unit 425.

[Problems to be Solved by the Invention] In the conventional disk cache control device 400 described above, the semiconductor storage element section 4 of the cache memory section 410
11 and the FCC/memory control circuit 412 are supplied with electricity from the same power supply section 41-5. Therefore, E
If a failure occurs in the CC/memory control circuit 412 and it is to be replaced, the electricity supplied to the cache memory section 410 must be cut off. At this time, the electricity supplied to the semiconductor memory element section 411 is naturally cut off, so there is a drawback that all data in the semiconductor memory element section 111, which is a volatile memory, is erased.

SUMMARY OF THE INVENTION An object of the present invention is to provide a cache control device for an auxiliary storage device that does not cut off the supply of electricity to a semiconductor storage element even when replacing an FCC/memory control circuit.

[Means for Solving the Problems] In order to achieve the above object, a cache control device for an auxiliary storage device according to the present invention has the following (a) to (d).

(a) Cache memory section.

(b) A power supply section for the cache memory section.

(c) an FCC that controls the operation of the cache memory unit and performs error correction processing for the cache memory unit;
- A memory control circuit, the auxiliary storage device, and the FCC.
An auxiliary storage device control unit including a control circuit that controls the exchange of information between a memory control circuit and the host computer.

(d) A power supply section for the auxiliary storage device control section.

Here, the auxiliary storage device refers to an external storage device of a computer, and includes, for example, a magnetic tape storage device, a magnetic disk storage device, an optical disk storage device, a magnetic drum device, and the like.

Cache memory is a high-speed memory that reduces the information processing speed gap between auxiliary storage and computers. For example, information from the auxiliary storage device is once stored in a cache memory, and the information stored here is read out at high speed by a host computer.

The ECC/memory control circuit has two main functions. That is, they are control of the operation of the cache memory section and error correction processing for the cache memory. Error correction processing involves generating an error code and adding it to the information when writing information to the cache memory section, and correcting errors based on the error code when reading information from the cache memory section. including.

[Operation] In order to avoid cutting off the electricity supplied to the semiconductor memory element section of the cache memory section when replacing the ECC/memory control circuit, separate power supplies are provided for the ECC/memory control circuit and the semiconductor memory element section. It is sufficient if electricity can be supplied from the Therefore, in the present invention, the ECC/memory control circuit is provided not in the cache memory section but in the auxiliary storage device control section. Separate power supplies are connected to the cache memory section and the auxiliary storage device control section.

[Example] Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

In this embodiment, the present invention is applied to a cache control device for a magnetic disk device 200, that is, a disk cache control device.

This disk cache control device 100 is roughly divided into four parts: a cache memory section 110, a power supply section 115 for it, a disk control section 120, and a power supply section 125 for it.

A semiconductor storage element section 111, which is a volatile high-speed memory inside the cache memory section 110, is connected to the disk control section 12.
It is connected to the internal ECC/memory control circuit 121 of 0. Then, inside the disk control unit 120, the ECC
-Memory control circuit 121 and control circuit 122 are connected. This control circuit 122 is connected to the ECC/memory control circuit 121, the magnetic disk device 200, and the host computer 300, and controls the exchange of information between them.

Next, a case where the ECC/memory control circuit 121 is replaced will be explained. If the FCC/memory control circuit 121 fails, it becomes impossible for the host computer 300 to access the semiconductor memory element section 111. Therefore, E
The CC/memory control circuit 121 must be replaced. In this replacement work, the FCC/memory control circuit 121 is replaced after cutting off the connection between the disk control section 120 and the power supply section 125. After that, the disk controller 1
20 and the power supply unit 125 are connected. Even during this operation, since electricity is supplied to the semiconductor memory element section 111 from the power supply section 115, the data in the semiconductor memory element section 111 is not erased. After the replacement work is completed, the host computer 300 can access the semiconductor memory element section 111.

The correspondence between the configuration of the present invention and the above embodiments is as follows: (1) the auxiliary storage device of the present invention corresponds to the magnetic disk device 200 of the embodiment; (2) the auxiliary storage device of the present invention corresponds to the magnetic disk device 200 of the embodiment; The device cache control device corresponds to the disk cache control device 100 of the embodiment, and (3) the auxiliary storage device control section of the present invention corresponds to the disk control section 120 of the embodiment.

[Effects of the Invention] As explained above, in the present invention, the ECC/memory control circuit is provided not in the cache memory section but in the auxiliary storage device control section. Electricity is supplied to each of the cache memory section and the auxiliary storage device control section from separate power supply sections. As a result, ECC・
When the memory control circuit breaks down and needs to be replaced, the FC
C. Even if the electricity to the memory control circuit is cut off, electricity is always supplied to the semiconductor storage element section in the cache memory section.
This has the effect that the data in the semiconductor memory element section is not erased.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional device. 100...Disk cache control device 110...
・Cache memory section 111...Semiconductor storage element section 115, 125...Power supply section 120...Disk control section 121...ECC/memory control circuit 122...Control circuit Fig. 1 Patent applicant: NEC Corporation Co., Ltd. Agent Patent Attorney Toshiyuki Meiki Figure 2

Claims (1)

[Scope of Claims] In a cache control device for an auxiliary storage device connected between a host computer and an auxiliary storage device, the following (a)
) to (d). A cache control device for an auxiliary storage device. (a) Cache memory section. (b) A power supply section for the cache memory section. (c) ECC that controls the operation of the cache memory unit and performs error correction processing on the cache memory unit;
- A memory control circuit, the auxiliary storage device, and the ECC.
An auxiliary storage device control unit including a control circuit that controls the exchange of information between a memory control circuit and the host computer. (d) A power supply section for the auxiliary storage device control section.