JPH0273108A - Measuring instrument for object - Google Patents

Abstract

PURPOSE:To prevent the deterioration of measuring accuracy of an object due to the divergence of focus and variance of member sensitivity by dividing plural optical sensors and storing a photodetected result of each optical sensor. CONSTITUTION:At the time of measuring the object 20 to be measured, a projecting device 10 forms slit light by an optical generator 12 to irradiate a scanning device 14 and scanning is carried out at the prescribed rotational angular velocity. A scanning detector 33 generates a current I according to the light quantity of the slit light and sends it to an image pickup device 32 as a scanning reference signal. The device 32 counts clock pulses and stores these. In addition, the object 20 is irradiated by the slit light whose reflected light is converged by a photodetector 30 and the pulsative photodetection current in accordance with its light quantity is generated and stored in the device 32. A data processor 40 then calculates and stores the positions (X, Y and Z) of a reflected point P of the slit light at the object 20 based on the data from the device 32.

Description

Detailed Description of the Invention (1) Purpose of the Invention [Industrial Field of Application] The present invention relates to an object measuring device, and particularly relates to an object measuring device that measures objects by convergence of light generated by a projector and reflected by an object to be measured. The present invention relates to an object measuring device that measures the time when an image of a light reflection point is formed on each optical sensor of an optical sensor device and calculates the position of the light reflection point from the measurement result.

[Prior Art] Conventionally, this type of object measuring device uses a light receiving device, that is, each light sensor of a light sensor device, which is operated in accordance with the convergence of light generated by a light projector and reflected by an object to be measured. A counting circuit is provided in common for both, and when the light reflected by the object to be measured is imaged on each optical sensor by the imaging device, the counting contents given from the counting circuit are sent to each optical sensor. On the other hand, a method was proposed in which the position of the light reflection point on the object to be measured is calculated by storing the light in a storage device consisting of registers connected in a one-to-l ratio.
“Prototype of dimensional object measuring device” IEICE technical research report Institute of Electronics, Information and Communication Engineers PRU-87-41
October 1, 1987).

[Problems to be solved] However, in this type of object measuring device, (i)
Since the resistors of the Ki-1 equipment were connected one-to-one to each optical sensor, the number of optical sensors was increased (for example, 10
(0 pieces x 100 pieces = 10,000 pieces), the number of registers increases accordingly to, for example, 10,000 pieces, which has the disadvantage of (ii) an increase in the mounting area and an increase in implementation cost. (iii) Since an imaging device was used, there was a drawback that the resolution could not be maintained sufficiently when the image on each optical sensor became out of focus depending on the location, and (iv) Since the sensitivity of the components varies, there is a drawback that the pulse width of the received light signal changes, and as a result, the TV
) There was a drawback that the accuracy of object measurement was affected by focus deviation or variations in component sensitivity 6 Therefore, the present invention has the following drawbacks:
In order to solve these drawbacks, a plurality of optical sensors belonging to the optical sensor device are divided into at least one group parallel to the scanning direction of the measurement area by the light projector, and one-to-one communication is performed for each group. By connecting a random access memory to the memory and storing the light reception results of multiple optical sensors belonging to the optical sensor device, the mounting area and cost of the storage device can be reduced, and the space between the optical sensor and the random access memory can be reduced. It is an object of the present invention to provide an object measuring device which suppresses deterioration in object measuring accuracy due to focus deviation or variations in component sensitivity by disposing a pulse center detection circuit in the object measuring device.

(2) Structure of the invention [Means for solving the problems] The means for solving the problems provided by the present invention are [(a)
(b) a light projector that generates light for scanning a measurement area; and (b) reflected light obtained when the light generated by the projector is reflected by a measurement object placed in the measurement area. an imaging device that converges the light to form an image of the reflection point of the light on the object to be measured; a first optical sensor device consisting of a plurality of optical sensors arranged to form at least one group along the scanning direction; and a +d1 light projector operated by light generated to scan the measurement area. (e) a reset terminal connected to the second photosensor device and reset by a scanning reference signal generated by light sensing of the second photosensor device; A counting circuit that counts the number of clock pulses later applied to the input terminal; at least one random access memory into which the counting contents of the counting circuit are input and stored when the optical sensors belonging to the first optical sensor device are operated; At least one pulse center detection circuit (h) random which is attached and detects the pulse center of the light reception signal output by the optical sensor belonging to the first optical sensor device and provides a trigger signal to the random access memory according to the detection result. An object measuring device comprising: a data processing device that receives storage content from an access memory, calculates a scanning angle of a reflection point by a light projector, and then calculates a position of the reflection point from the calculated scanning angle. ”.

[Function] The object measuring device according to the present invention converges the light generated by the illuminating device and reflected by the object to be measured in the region to be measured by the imaging device, and forms an image of the reflection point. Since the memory device arranged one-to-one for each group of photosensors belonging to the first photosensor device operated by the random access memory is formed by random access memory, the mounting area and cost of the storage device are reduced. has the effect of
In addition, (ii) by arranging a pulse center detection circuit on a one-to-one basis for each group of optical sensors belonging to the first optical sensor device, the pulse center of the light reception signal output by the first optical sensor is detected. Since a trigger signal is given to the random access memory according to the detection result, the image formed on the photosensor belonging to the first photosensor causes a focus shift and maintains high resolution; Even if there are variations in the sensitivity of components such as optical sensors belonging to the optical sensor device, the pulse width of the received light signal changes. This serves to avoid a decrease in accuracy.

[Example] Next, the object measuring device according to the present invention will be described in detail by giving examples thereof. However, the examples described below are described to facilitate or accelerate the understanding of the present invention, and are not described to limit the present invention. In other words, each member disclosed in the embodiments described below includes various design changes and equivalent substitutions as long as they belong to the spirit and technical scope of the present invention.

゛ Fig. 1 is a perspective view showing one embodiment of the object measuring device according to the present invention.6 Figs. 2 and 3 are both enlarged perspective views of a part of the embodiment of Fig. 1. It is a diagram.

FIG. 4 is an enlarged partial circuit diagram showing a part of the embodiment of FIG. 1 in an enlarged manner.

FIG. 5 is a block circuit diagram showing a part of FIG. 3 in an enlarged manner.

FIG. 6 is a time chart diagram for explaining the operation of FIG. 5.

FIG. 7 is a detailed block circuit diagram embodying FIG. 5.

FIG. 8 is a time chart diagram for explaining the operation of FIG. 7.

FIG. 9 is another detailed block circuit diagram that embodies FIG. 5.

FIG. 10 is a time chart diagram for explaining the operation of FIG. 9.

First, the configuration of an embodiment of the object measuring device according to the present invention will be described in detail with reference to FIGS. 1 to 4.

10 is a light projection device of the object measuring device according to the present invention, which generates light for scanning a measurement area; -
A slit light generator 12 that generates slit light that is dimensionally expanded, that is, linearly expanded, and a slit light generator 12 that temporally moves the traveling direction of the slit light in a direction perpendicular to the expansion direction (hereinafter referred to as the "° scanning direction"). A scanning device 1 that scans a measurement area while changing it at a constant rate (i.e., a constant angular velocity ω)
4.

The slit light generator 12 is, for example, a gas laser light source,
A suitable light source 121 such as a semiconductor laser light source 0, a light emitting diode light source or a tungsten lamp light source, and a light source 12
Appropriate means for converting the beam light generated by
It encompasses.

When the light source 121 is a gas laser light source, the generated laser light is a beam of light, so it may be applied to the cylindrical lens 122 as is. On the other hand, when the light source 121 is a semiconductor laser light source, the generated laser light is two-dimensionally diffused, that is, in a planar shape. After the light is converged, it may be applied to the cylindrical lens 122. Furthermore, when the light source 121 is a light emitting diode light source or a tungsten lamp light source,
Since the generated light is not a beam of light, it is sufficient to convert it into a beam of light using an appropriate means and then apply it to the cylindrical lens 122.

The scanning device 14 is, for example, a rotating mirror device including a mirror 141 for reflecting the slit light and a rotation drive device 142 for rotating the mirror 141 at a constant angular velocity ω about a rotation axis parallel to the direction of expansion of the slit light. It is configured. The scanning device 14 may also include a table (not shown) on which the slit light generating device 12 is placed, and a rotation drive device (not shown) for rotating the table at a constant angular velocity ω. may have been done.

The object to be measured is placed in the measurement area of the object measuring device according to the present invention, and is irradiated with the slit light provided by the light projection device 10 .

The light receiving device of the object measuring device according to the present invention converges the slit light reflected by the object to be measured, that is, the reflected slit light, and generates an image of the object to be measured, that is, an image of the reflection point P of the slit light. Imaging device 3 for forming an image
1 and the object to be measured 20 imaged by the imaging device 31
an image capturing device 32 for capturing an image of the reflection point P of the slit light, and a scanning device 1 included in the light projection device IO.
The scanning detection device 33 is disposed near 4 and detects that the measurement area is being scanned by the slit light.

The imaging device 31 is formed of a converging lens that looks into the measurement area, that is, the area scanned by the slit light, and converges the single reflected slit light.

The imaging devices 32 are appropriately arranged in a matrix in order to capture an image similar to the object to be measured, that is, an image of the reflection point P of the slit light, formed by converging the reflected slit light by the imaging device 31. A plurality of optical sensors, such as optical transistors (hereinafter, this case will mainly be explained, but there is no intention to limit it thereto) 321°, 32L
2. ..., 3211°: 321□1.321□2.
..., 321□n:"・;321+a+, 321mg
, -,321,I, the first optical sensor device 32
1 and a phototransistor 321 .1 belonging to the first photosensor device 321 . ,．． 321+2°..., 321. ,+32
1. ,．． 3212. , ・−,3212,:・−・:3
21. ,l,.

321□2. ..., 321. , , a plurality of comparison amplifier circuits 322 .
,．． 322.2..., 322. n:322□,,32
2□a, ---, 322□. ;3221. ,,． 322
II12°..., 322°, and multiple comparison amplifier circuits 3
22. ,．． 322. □..., 322. ,+322□,,
322□2.・-, 322□. :322ff1. ．． 32
2. ,.

..., 1 for each output end of each row of 322□
at least one storage device 324I connected in a pair l;
324□,...,324. and a storage device 324,
, 324□, ..., 324ffi, and a counting circuit 325 whose output terminal is connected to the input terminal of the counting circuit 325, and whose output terminal is connected to the input terminal of the counting circuit 325, which outputs a clock pulse C of a constant period.
A clock pulse generation circuit 326 that generates LP, and a plurality of storage devices 3243242, . . . , 324. A plurality of output terminals are connected one-to-one to the control terminals of the six storage devices 324□3242.6, each including a decoder circuit 327 that generates a designation signal GE. ..., 32
4□ all have the same configuration, so for convenience, the storage device 324 will be explained here (i=1.2
．． ..., m). That is, the storage device 3241 includes a plurality of comparison amplifier circuits 3221322, . . . , 322 . ,
A logical sum circuit OR, whose input terminals are connected to the output terminal of the logical sum circuit OR, in a ratio of 1:1, a pulse center detection circuit PC6 whose input terminal is connected to the output terminal of the logical sum circuit OR, and a pulse center detection circuit PC1. a random access memory RAM whose trigger terminal is connected to the output terminal and whose input terminal is connected to the output terminal of the counting circuit 325; and a plurality of comparison amplifier circuits 322. ,
．． 322. The input terminal is connected to the output terminal of □, ...322, and the output terminal is a random access memory RAM.
, an encoder circuit ENC connected to the address input terminal of
, and includes.

The scanning detection device 33 is an optical sensor, such as a phototransistor, which is opposed to the mirror 141 and detects the slit light reflected by the mirror 141 (this case will be described below, but is not intended to be limited thereto).
331 and a comparison amplifier circuit 332 arranged between the output terminal of the optical transistor 331 and the reset terminal of the counting circuit 325 of the imaging device 32.

Reference numeral 40 denotes a data processing device of the object measuring device 10 according to the present invention, which includes storage devices 324 and 32' in the light receiving device's ear.
b,...,324. That is, a read signal S for selecting and specifying storage addresses in the random access memories RAM, RAM,..., RAMff1 one by one.
Generates EL and stores its storage device 3241.324t,...
・, 324. and a read signal generation circuit 41 for providing to the decoder circuit 327, an output terminal of the read signal generation circuit 41, and a memory device 324 in the light receiving device 30.
24□, . ...324
, S (in detail, random access memory RAMRAM
t, . The reflection point P of the slit light on the object to be measured 20 is determined based on the contents of the image data IMG.
It includes an arithmetic circuit 43 that calculates the position of. The data processing device 40 further includes, if desired, another storage device 44 which is connected to the calculation circuit 43 and stores the calculation results, that is, the position of the reflection point P of the slit light on the object to be measured 20, and other storage devices. A display device 45 such as a cathode ray tube which is connected to the device 44 to visually display the stored contents; and a recording device such as a floppy disk which is connected to the other storage device 44 and which records the stored contents. It includes 46.

Next, the operation of an embodiment of the object measuring device according to the present invention will be described in detail with reference to FIGS. 1 to 4.

In order to keep the following explanation concise and easy to understand,
First, we will introduce a three-dimensional coordinate system.

That is, the center of the imaging device 31 is set as the origin ○, and the imaging device 3
1, that is, the Z-axis is taken to pass through the origin 0 and parallel to the expansion direction of the slit light, that is, the rotation axis M of the mirror 141, and a line segment OM that connects the imaging device 31, that is, the origin 0, and the rotation axis M of the mirror 141. The X-axis lies on the base line (its length is a) and is orthogonal to the Z-axis, and passes through the imaging device 31, that is, the origin O, and the X-axis and Z
Take the Y axis perpendicular to the axis. Furthermore, the angle between the slit light and the
In addition, the angle that the reflected slit light passing through the origin O makes with the Y axis in the XY plane is 08, and the angle it makes with the Y axis in the YZ plane is β2. Reflected at the reflection point P (X, Y, 21
The reflected slit light that has passed through the center of 1, that is, the origin O, is
An imaging surface or phototransistor 321 .separated from the imaging device 31 by a distance f. .

321+z, =・, 32L-: 321z+, 321z
z,...',321zo:...:321□,,32
1□2. ..., 321i. Let the coordinates of the point Q imaged above (that is, the image of the reflection point P) be (x, y, zl).

Reflection point P (X, Y, 21 (7) The projection points on the X, Y, and Z axes are RfX, 0.ol, s (
0, Y, 01. T (0,0,21 to.

At this time, as is clear from FIG. 1, the relationship OM=OR+RM holds true, so +YCOtα holds true for a=Ytanβ, and by rearranging this, the relationship Y=a [tarl x + cota] − can be obtained. Since tanBx = x f -', it can be expressed as Y=af [x+f cota] -'.

Furthermore, since the relationship 0R=O3tanBx holds true, the relationship X=Ytanβ× can be obtained. Here, since tanβx=xf-', it can be expressed as X=ax [x+f cota]-'.

Similarly, since the relationship OT-'03tanβ2 holds true, the relationship Z=Ytanβ2 can be obtained. Here, since ta mouth β2=zf-', Z=az [x+f cota] -' -----
It can be expressed as (3).

In addition, the scanning angle α is the scanning detection device 33 in the XY plane.
An angle between the line segment connecting the mirror 141 and the X-axis, that is, the reference scanning angle α. , the constant angular velocity ω of the mirror 141, and the times t and t'', it can be expressed as α=ω(t−to)+α.−−−−−−−+4).

Here, the time t is calculated from the time when the slit light reflected by the mirror 141 is detected by the scanning detection device 33, that is, from the reference time (for example, °°0°), the phototransistors 321++, 32Li, . . . , 32Ln;
g+, 321g□,..., 321. n;-・-;32
11. The pulse center detection circuits PC+, Pct,...・, is the time obtained by adding the delay time t° in pc-. Therefore time t-t
” is determined from the time when the slit light reflected by the mirror 141 is detected by the scanning detection device 33, that is, the reference time (for example, °゛O”), the phototransistor 321.
,．． 32112.・-, 3211n+321z+, 32
1g! ,”',321zn:...-;321ffl,,
This is the time required until the reflected slit light is imaged by the imaging device 31 for each column of 321111□, . . . 321, n.

When measuring an object to be measured, first the storage device 324 included in the light receiving device. ．． 324□,..., , 324
ff, and thus random access memory RAM, RA
The memory contents of M, . . . , RAM are stored by appropriate means (
(not shown) and a specific value (e.g. 0°
°).

In the light projection device IO, a slit light generator 12 generates slit light. That is, the beam light generated by the light source 121 is converted into slit light by the cylindrical lens 122. The slit light is transmitted to the mirror 14 of the scanning device 14.
1 is irradiated. At this time, since the mirror 141 is rotated by the rotation drive device 142 at a constant angular velocity ω, the slit light is reflected by the mirror 141 and then directed toward the measurement area at a constant rotational speed, that is, at a constant rotational angular velocity ω. It is sent out for scanning.

Here, when the phototransistor 331 of the scanning detection device 33 is irradiated with the slit light reflected by the mirror 141 of the scanning device 14, it is made conductive and generates a current (2) corresponding to the amount of the snot light. The current I is amplified as desired by a comparison and amplification circuit 332 attached to the phototransistor 331 and compared with a reference value, and then provided to the counting circuit 325 of the imaging device 32 as a scanning reference signal SI.

The counting circuit 325 is the comparison amplifier circuit 3 of the scanning detection device 33.
The scanning reference signal SI given from 32 is used as a reset signal, and when the scanning reference signal SI is given, the counting contents are reset and the counting start time is adjusted.
Counting of the number of clock pulses CLPO given from the clock pulse generation circuit 326 is started again. Counting circuit 325
The count contents are based on the reset signal, that is, the scanning reference signal SI.
When reset by the minimum value (e.g. °'O
”), and is incremented by l each time the clock pulse CLP arrives.The count contents of the counting circuit 325 are stored in the storage devices 324..324□, . . .
324□Furthermore, random access memory RA! , 1.
, RAM, ..., RAM1. , is given at the input end of .

Further, the slit light linearly illuminates the object to be measured 20 in the region to be measured. At this time, since the traveling direction of the slit light is changed by the scanning device 14 at a constant angular velocity ω, the object to be measured 20 irradiated with the slit light
area has moved accordingly. Therefore, the position of the reflection point p (x, y, z+) of the slit light due to the rotation of the object to be measured is changing.

The slit light reflected by the object to be measured 20, that is, the reflected slit light, is converged by the imaging device 31 of the light receiving device 30, and is focused on the imaging surface of the imaging device 32, that is, the plurality of phototransistors 32111, 321. □,...,321.
, l;32121.32122. ..., 321zn:
...-:3211. l,,321. ,,...321
, is imaged above. Image formation position Q of reflected slit light
(x, y, z) are a plurality of optical transistors 321° 321,
,...-,321,n;321. ,．． 32122.
=・=,321m,;-・-;321ffi,,321
．． 2. . . . is gradually moving in the direction of the 321□ column. When the reflected slit light is imaged, the phototransistor 32
1. ,．． 321. □,..., 321□. :321□,
, 321□2゜..., 321zn;"・;321.,
．． 321-,,-...,321. , , are conductive, respectively, and a light reception signal, that is, a pulsed light reception current I I I + I12 according to the light intensity of the imaged reflected slit light.
．． "'+ Ln: Iz+, Iz□, "', I2
n:” ' :11111.l1ll11゜...+l
Generate lllT1. Pulsed photodetection current ■, □,
..., Ln: Ia+, Ia□, ..., Imn: ...
': Im+, IIR/l+...Imn are phototransistors 32L+, 321+□, respectively.

=", 321..: 32b+, 321a2..-, 32
1,n;-...,32Lffi,.

Comparison amplifier circuits 322□, 322+z, ..., 32 attached one-to-one to 321, □, ..., 321□
2. n: 322□1.32222°・-, 322,. ;
...;322. ,．． 322. ,．． 322ff1. After being amplified as desired by and compared with a reference value, the trigger signal S1. ,SI,□,...,Sl,ll;
SI2. ,SI2□,...Sl,, ;---: Sl
,R,,Sl,,,2. -..., Sl,. as storage devices 324. ．． 324□,..., 324. given to.

Storage device 324. ．． 3242. ..., 324□ are trigger signals SL+, SI+z, .=, SI+. :SIz
+, 5Izz, ..., 5I2n:=・SI,,,,
, SI, , . . . , SI, , , are given, substantially the same operation is performed. Therefore, for convenience, the storage device 324. (i=1.
2. ...m).

Storage device 324. Then, the trigger signal 5111.5I12
Each time ゜..., Sl,, becomes high level, the logical sum circuit OR, outputs its trigger signal S1. ,,Sl,2. ...
, SI, , (hereinafter also referred to as "trigger signals SI++, SI+□, ..., SI,").

) is output and given to the pulse center detection circuit PC6. The pulse center detection circuit PC1 detects the high level signal (that is, the trigger signal 5I11.5I12.--) every time a high-level signal is given from the OR circuit OR.
, Sl, n), and detects the pulse center time position To of the pulse center time position To, and detects the pulse center time position To from the pulse center time position To by delay time t1 or less "Tst".
A pulse center detection signal that rises (or falls) with a delay of r° is generated and is applied as a trigger signal TI+ to the trigger terminal of the random access memory RAM. At this time, encoder circuit E
NC, is the trigger signal SI, , , Sl, □, ---, S
In response to the arrival of I, , a predetermined address signal ADl is generated and applied to the address input terminal of the random access memory RAIJ, so that the random access memory RAM
+ is the trigger signal SI, ..., SI, □, ..., SI, ...
In turn, the phototransistors 32L, 32L2.・−、
The count contents CON given from the counting circuit 325 are stored and held at the storage address corresponding to 32L. At this time, the storage devices 3241324□, . . . , 324.
Furthermore, random access memory RA111I, RAM
2. . . , the storage contents of RAl, 1ffl are transferred to the phototransistor 321 . ,．． 321. □、 、−、321、n+
321. ,．． 321□2.・・3212゜；・・：32
1. ,．． 321. ! ,..., 321. , corresponding to time t,,t+□,...,tzn:tz+,jz□,
...,t2n;'・-+11It,,...+jll
ll'l.

The data processing device 40 generates a read signal SEL from a read signal generation circuit 41, and generates a read signal SEL from a decoder circuit 32 in the light receiving device ear.
7 and storage device 324. ．． 324. ,...,324. ,
Furthermore, random access memory RAM, , RA
It is given to M, ,..., RAl, l□. The read signal SEL given to the decoder circuit 327 is made into the designation signal CE in the decoder circuit 327, and the storage device 3
24+, 321□, ”', 324nl and random access memory RAM1. RAM2...., R
AM, 1. The storage devices 324324□, . . . , 324. Furthermore, the random access memory RAM, , RAM2 . ..., R.A.
M, , is specified. Also, the storage device 324, ,
324□,...,3241. In addition, random access memory RAM +, RAIJ2,..., R
AI! The read signal SEL directly applied to the random access memories RAn, , depending on its contents is
RAM1... specifies a storage address within RAM. The storage device 324 according to the designation of the read signal SEL.
, ,324□,..., 324. Random access memory RA! ,! , , RAM2 ,・
..., RAMff1 has its memory content, that is, the time t
'++,j+□,...,jl,,:j21. t2□,・
...j2n:...:t,,,1. t,,,,・
. . + j @ n is sequentially outputted as imaging data IMG to a storage device 42 which is equivalent to a data processing device.

The storage device 42 stores image data IMG given from the light receiving device 4, that is, storage contents j I I + j + 2
+..., jl. :ta 1. tz□,...,t!
ll;...:t□, t□2. ..., t□ is memorized and retained. Imaging data I&4G stored in storage device 42
are given to the arithmetic circuit 43, where the position (X, Y,
21.

That is, the arithmetic circuit 43 includes the optical transistor 321++3
2La, ・=, 321+n: 321g+, 321zz
, ・=J21z, :=・:321, . 321.2.
--・, 321. r, respectively, α■2ω (tz−t”) +α0 αth=ω α In”ω (1, □−t”) ten α according to the above equation (4).

(tzn-t”) +α.

α2. =ω (tz+-t”) +α.

α2□=ω (tza-t”) +α.

α2. , = ω (tzn-t”) + α.

α1=ω (t, +-t”) +α.

0m2=ω (t,,-t'') +α.

The scanning angle α is calculated as α11111”ω (t, n-t”) +α0. This scanning angle α is α, ,α
1□,..., αlo; α23. α2□, ...α2
o;...:α1. α1□, ..., α, above m~(
3) By substituting into the equation, the phototransistor 321
+ +, 32Li, ” ', 321+n:321
i+, 321gg, ” ', 321g, :...
;321□, 321ffi2. -, 321ffi, the position (X, Y, Z) of the reflection point P imaged on, that is, the reflection point PII+Prz+PIn;P! In
P2! + ”'+ P zn:...'; P ml+
P m2...-, P,, (7) Position (X+I, Y++
, Z+, l, (X1i, Y, -, 212) -..., (
X, n, Y, ,,Z,,l, (X,,,Y,,,
22. ), (X, , Y2..

222)-=・, (X2o, Y2n, Z2nl;・
=: (xff, 1.y-+, z-+1(X, 2.Y,
,,,,Z,,,2+, ・-,fX-,,Y-,,
Calculate Z,,l.

The configuration of the pulse center detection circuit PCI will be described with reference to FIGS. 5 and 6.

The calculation results of the calculation circuit 43, that is, the calculation results of the position (X, Y, ZI) of the reflection point P of the slit light on the object to be measured, are given to another recording/obstruction device 44, where they are stored and retained. The stored contents of 44 can be visually displayed on a display device 45 if desired, and can also be displayed on a recording device 46.
recorded by.

Here, the pulse center detection circuit P in the light receiving device 30 described above
The configuration and operation of CI will be explained in detail.

(i=1-m).

The pulse center detection circuit PCI may be configured as shown in FIGS. 5 and 6, for example. This will be explained in detail below.

The input terminal of the pulse center detection circuit Pct is connected to the output terminal of the OR circuit OR1, and the input terminal of the pulse center detection circuit Pct is connected to the output terminal of the OR circuit OR1.
As mentioned above, the input pulse, that is, the l trigger signal S1
．． ．． (Illustrated here as a rectangular pulse. The same applies hereinafter.j=1-m) is input, the pulse width measuring circuit A measures the pulse width T and outputs it as a pulse width signal S0.
The input terminal is connected to the output terminal of the pulse width measuring circuit A, and the content of the pulse width signal SQ (that is, the pulse width T) is inputted to the pulse center time position T of the input pulse, that is, the trigger signal Sr. A division circuit B that divides by a divisor corresponding to , that is, 2, and outputs it as a division signal S3Q;
The input terminal is connected to the output terminal of the division signal S5.
A subtraction circuit C that subtracts the contents of ゜ (that is, time width T/2) from a desired set delay time T3Ea (=t゛: the same applies hereinafter) and outputs it as a delay command signal SF, and an output terminal of the subtraction circuit C. The input end is connected to the random access memory RAM, and the output end is connected to the trigger end of the random access memory RAM, which generates a pulse center detection signal in response to the delay command signal SF, and generates the above-mentioned trigger signal T1. The output circuit includes an output circuit for providing a trigger terminal of a random access memory RAM by outputting the output signal.

The operation of the pulse center detection circuit Pct will now be described with reference to FIGS. 5 and 6.

The pulse width measuring circuit A of the pulse center detection circuit PCI measures the time width, that is, the pulse width T, when an input pulse, that is, the trigger signal SI, is given to the input terminal from the OR circuit OR, and generates a pulse width signal S0. Output as .

The division circuit 1 converts the output of the pulse width measurement circuit Δ, that is, the content of the pulse width signal So (that is, the pulse width T) into an input pulse, that is, the trigger signal S1. pulse center time position T.

Calculate T/2 by dividing by the divisor corresponding to , that is, 2,
It is output as a division signal Sso.

The subtraction circuit C receives the output of the division circuit B, that is, the division signal S.
By subtracting the content T/2 of 9Q from the predetermined set delay time To, the required delay time T, , T-T/2 is calculated and output as the delay command signal S.

The output circuit outputs the output of the subtraction circuit C, i.e., the content of the delayed command signal SF (i.e., delayed from the rear end time position of the input pulse, i.e., the trigger signal 5IIJ (i.e., T0+T/21) by a time corresponding to the content of the delayed command signal SF (i.e., T5ET-T/21). A pulse center detection signal is generated at the time position (i.e., T.TsET) and output as a pulsed trigger signal T1. (shown here as a rectangular pulse; the same applies hereinafter) to the trigger end of the random access memory RAM. do.

Specifically, the above-mentioned pulse center detection circuit Pct may be configured as shown in FIGS. 7 and 8, for example. This will be explained in detail below.

The configuration of the pulse center detection circuit PCI will be described with reference to FIGS. 7 and 8.

The pulse width measurement circuit A receives a clock pulse signal S eX from a clock pulse generation circuit CLK included in the control circuit to one input terminal, and receives a clock pulse signal S eX from an OR circuit OR to the other input terminal. Input pulse or trigger signal S1. , and within the time when the input pulse, that is, the trigger signal 5IIJ arrives (i.e., the time corresponding to its pulse width T), the clock pulse signal S c
The clock pulse signal S cx is passed through m and is output from the output terminal.
” AND circuit as a gate circuit that outputs
and an AND circuit AND for the clock pulse input terminal GK.
The counter CNT is connected to the output terminal of the counter CNT and is supplied with a clock pulse signal SCK@ during the time when the input pulse, that is, the trigger signal SI, J arrives.

In the division circuit 1, the data input terminal A is connected to the output terminal Q of the counter CNT included in the pulse width measuring circuit Δ, and the count contents of the counter CNT (that is, the trigger signal 5
After the pulse width T) of IIJ is input as the pulse width signal SQ, it is used as the input pulse, that is, the trigger signal 5IIJ.
pulse center time position T.

The result of dividing by the divisor corresponding to , that is, 2, is T/2
It includes a shift register SHT that outputs .

The subtraction circuit has a NOT circuit NOT whose input terminal is connected to the output terminal Q of the shift register SHT included in the division circuit, and a data input terminal B which is connected to the output terminal of the NOT circuit NOT. a full adder ADD to which a carry signal "゛1°° is inputted to the carry input terminal C;
The output terminal is connected to the other data input terminal A of the full adder ADD, and the desired delay time TsE is set (the set delay time T!JET is referred to as ``door opening at set delay''). It includes a setting circuit SET.

The output circuit 1 has a data input terminal A connected to an output terminal F of a full adder ADD included in the subtraction circuit 1, and outputs a pulse center detection signal in response to a delay command signal SF output from the full adder ADD. generates a trigger signal T1. Close output end Q
It includes a down counter DCNT which is output from the random access memory RA to the random access memory RA.

The control circuit E is a control circuit that constitutes a part of the pulse width measurement circuit Δ, the division circuit B, and the output circuit, but here, for convenience of explanation, the pulse width measurement circuit Δ, the division circuit Δ, and the output circuit Illustrated separately from. That is, in the control circuit 1, the above-mentioned clock pulse generation circuit CLK and the clock pulse input terminal GK are connected to the output terminal of the clock pulse generation circuit CLK, and the clear input terminal CL is connected to the output terminal of the down counter DCNT. The control input terminal CT includes a control pulse generating circuit CTR connected to an OR circuit OR, which is a source of input pulses, ie, a trigger signal SI, . Further, the control pulse generation circuit CTR has a first output terminal (that is, a clear output terminal I
Q, is a counter CNT included in the pulse width measuring circuit Δ
is connected to the clear input terminal CL of the second . The third output terminal (that is, the load output terminal and shift output terminal IQ2.03) is connected to the load input terminal LD and shift input terminal ST of the shift register SHT included in the division circuit B, respectively, and the fourth. 5 (ie, the other load output terminal and clock pulse output terminal) Q4.
Q5 is connected to a load input terminal LD and a clock pulse input terminal CK of a down counter DCNT included in the output circuit, respectively.

The operation of the pulse center detection circuit PC2 will now be described with reference to FIGS. 7 and 8.

In the control circuit E, a clock pulse signal Sett is outputted from the clock pulse generation circuit CL, and the clock pulse signal Sett is outputted from the clock pulse generation circuit CL to one input terminal of the AND circuit AND included in the pulse width measurement circuit Δ and the clock of the control pulse generation circuit CTR. It is given to the pulse input terminal GK.

In this state, a trigger signal S1. which is an input pulse, that is, a pulsed amplified voltage, is sent to the other input terminal of the AND circuit AND included in the pulse width measurement circuit A. , arrives from the OR circuit OR, the clock is output from the output terminal of the AND circuit AND in response to the period of its H level (this case will be described as an example below), that is, the pulse width T of the input pulse, that is, the trigger signal 5IIJ. The clock pulse signal ScX# is output from the counter C
The counter CNT counts the number of pulses included in the clock pulse signal Sc,+6 since it is applied to the clock pulse input terminal CK of the clock pulse signal NT. The count contents of the counter CNT correspond to the pulse width T of the input pulse, that is, the trigger signal SI, and the pulse width signal SQ is output from the output terminal Q of the counter CNT.
is applied to the data input A of the shift register SHT which is included in the divider circuit.

When the input pulse, that is, the trigger signal 5IIJ arrives from the OR circuit, after its H level ends, the output terminal Q of the control pulse generation circuit CTR included in the control circuit is output.
A load signal S SLD is outputted from the divider circuit 2 and applied to the load input terminal LD of the shift register SHT included in the divider circuit. As a result, the shift register SHT reads the contents of the pulse width signal Sa applied to the data input terminal A.

Thereafter, a shift signal SssA is generated from the output terminal Q3 of the control pulse generation circuit CTR and applied to the shift input terminal ST of the shift register SHT. As a result, the shift register SHT shifts the contents of the pulse width signal S0 inputted from the counter CNT by one bit in the direction of the lower bits, and sets 0 to the most significant bit which has become blank. As a result, the content of the pulse width signal SQ input from the counter CNT becomes the input pulse, that is, the trigger signal S1. ,
pulse center time position T. is divided by a divisor corresponding to , that is, 2. As a result, the time width T/2 of the input pulse, that is, the trigger signal SI, from the desired pulse center time position T to the trailing end time position is calculated.

The division result in the shift register SHT is given from its output terminal Q as a division signal Sso to the NOT circuit NOT included in the subtraction circuit Ω. The NOT circuit NOT inverts the division signal Sso and supplies it to the data input terminal B of the full adder ADD as an inverted division signal S3°. In the subtraction circuit SET, the desired setting delay time T is set for the setting circuit SET.
aEt is set, and its contents are applied from the output terminal to the data input terminal A of the full adder ADD as a set delay signal Sg.

In the full adder ADD, the setting delay signal S3 inputted to the data input terminal A and the inverted division signal S MQ inputted to the data input terminal B are used as a carry signal "l" inputted to the carry input terminal C. is added to the set delay time TsET set as a result for the setting circuit SET.
By subtracting the division result T/2 in the division circuit from T-tt-
T/2 is calculated.

The result is transmitted from the output terminal F of the full adder ADD to the down counter D included in the output circuit as a delay command signal SF.
It is applied to the data input terminal A of the CNT.

At this time, the load signal S is output from the output terminal Q4 of the control pulse generation circuit CTR. Lf+ is generated and the down counter DCN
Since it is applied to the load input terminal LD of T, the contents of the delay command signal S7 applied to the data input terminal A are read, and the contents of the delay command signal SF are held in the down counter DCNT. Ru.

After that, the output terminal Q of the control pulse generation circuit CTR.

Since the clock pulse signal S ocx is generated from and given to the clock pulse input terminal CK of the down counter DCNT, the down counter DCNT receives the content input as the delay command signal S from the full adder ADD (i.e. Each time the clock pulse signal SDCX applied to the clock pulse input terminal CK arrives, one is subtracted from the actual delay time TsET-T/2). The number of clock pulses corresponding to the content input as the delay command signal SF (ie, the actual delay time Tst - T/2) is the clock pulse signal S. When the clock pulse CK is applied to the input terminal CK, the count content of the down counter DCNT becomes 0, so a pulse center detection signal is generated, and a pulse-like pulse J is generated from the output terminal Q.
Ga signal T1. The signal is output as a signal and applied to the trigger terminal of the random access memory RAM+.

Pulse center detection signal or trigger signal TI.

is applied to the clear input terminal CL of the control pulse generation circuit CTR, clearing the contents of the control pulse generation circuit CTR, and preparing for the arrival of the subsequent input pulse, that is, the trigger signal ST, .

Prior to that, the control pulse generating circuit CTR outputs the output terminal Q.
A clear signal SCL is generated from I and applied to the clear input terminal CL of the counter CNT to clear the counter CNT and prepare for the arrival of the subsequent input pulse, that is, the trigger signal SI.

Further, the pulse center detection circuit PCI may be configured as shown in FIGS. 9 and 10, for example.

This will be explained in detail below.

The configuration of the pulse center detection circuit PC1 will be explained with reference to FIG. 9 and FIG. 1O.

The pulse width measurement circuit A receives a clock pulse signal S from a clock pulse generation circuit CLK included in the control circuit E at one input terminal. X is applied to the other input terminal, and an input pulse, that is, an l trigger signal S1. j is given and an input pulse, that is, a trigger signal S1. , (that is, the time corresponding to its pulse width T), the clock pulse signal S
A clock pulse signal S c is passed through ek from the output terminal.
AND circuit A as a gate circuit that outputs as x
AND circuit A for ND and clock pulse input terminal CK
The output end of ND is connected to receive an input pulse, that is, a trigger signal S1. The division circuit B includes a counter ACNT to which the clock pulse signal S CX is applied within the time period in which the clock pulse signal S CX'' arrives. Input terminal A is connected, and the count content of counter ACNT (that is, pulse width T of trigger signal 5IIJ) is pulse width signal SAQ.
After that, it is input as an input pulse, that is, a trigger signal S1. , the pulse center time position T.

The result of dividing by the divisor corresponding to , that is, 2, is T/2
The shift register 5l (includes T) outputs .

The subtraction circuit C includes a NOT circuit NOT whose input terminal is connected to the output terminal Q of the shift register SHT included in the division circuit B, and a data input terminal B which is connected to the output terminal of the NOT circuit NOT. A full adder ADD has a carry input terminal C to which a carry signal °゛1'' is input, and an output terminal is connected to the other data input terminal A of the full adder ADD, and a desired delay time T str Setting of (set delay time T,
It includes a setting circuit SET which performs the following.

In the output circuit, the data input terminal A is connected to the output terminal F of the full adder ADD included in the subtraction circuit C, and the pulse center is detected in accordance with the delay command signal S output from the full adder ADD. A signal is generated at the output end Q as a trigger signal TI.
The output terminal Q is connected to the data input terminal B of the comparator circuit C1,lP which outputs data to the random access memory RAM + from the comparator circuit CMP, and the clear input terminal is connected to the output terminal Q of the comparator circuit C11lP. counter BC
Contains NT.

The control circuit Δ is a control circuit that constitutes a part of the pulse width measurement circuit Δ, the division circuit B, and the output circuit, but here, for convenience of explanation, the pulse width measurement circuit Δ, the division circuit Δ, and the output circuit Illustrated separately from. That is, the control circuit E has the above-mentioned clock pulse generation circuit CLK, the clock pulse input terminal GK is connected to the output terminal of the clock pulse generation circuit CLK, and the clear input terminal CL is connected to the output terminal of the comparison circuit CMP. Control input terminal CT
includes a control pulse generating circuit CTR connected to an OR circuit OR, which is a source of input pulses, that is, a trigger signal SI. In addition, the control pulse generation circuit CTR
, the first output terminal (that is, the clear output terminal) Q is connected to the clear input terminal CL of the counter ACNT included in the pulse width measuring circuit Δ, and the second . The third output terminal (i.e. load output terminal and shift output terminal IQ,
Q3 is connected to the load input terminal LD and shift input terminal ST of the shift register SHT included in the division circuit B, respectively, and the fourth output terminal (that is, the clock pulse output terminal) Q4 is included in the output circuit B. counter BCN
It is connected to the clock pulse input terminal C of T.

The operation of the pulse center detection circuit PC1 will now be described with reference to FIGS. 9 and 10.

In the control circuit E, the clock pulse signal Sck is outputted from the clock pulse generation circuit CLK, and the clock pulse signal Sck is output from the clock pulse generation circuit CLK to one input terminal of the AND circuit AND included in the pulse width measurement circuit A and the clock pulse of the control pulse generation circuit CTR. It is given to the input terminal CK.

In this state, the input pulse, that is, the trigger signal S1. , arrives from the OR circuit OR, the period of its H level (this case will be exemplified below), that is, the input pulse, or the trigger signal S1. A clock pulse signal S CX'' is outputted from the output terminal of the AND circuit AND corresponding to the pulse width T of . Since the clock pulse signal S CX'' is given to the clock pulse input terminal GK of the counter ACNT, The counter ACNT counts the number of pulses included in the clock pulse signal SCK. The count of the counter ACNT corresponds to the pulse width T of the input pulse, that is, the trigger signal SI,
The division circuit B outputs the pulse width signal SAG from its output terminal Q.
is applied to the data input terminal A of the shift register SHT included in the data input terminal A.

The input pulse, that is, the trigger signal SI, is connected to the logical sum circuit OR
, and after the H level ends, the output terminal Q of the control pulse generation circuit CTR included in the control circuit E
Load signal S IILD is output from divider circuit B
Load input terminal LD of shift register SHT included in
given to. As a result, the shift register SHT reads the contents of the pulse width signal SAQ applied to the data input terminal A.

Thereafter, a shift signal SsgA is generated from the output terminal Q3 of the control pulse generation circuit CTR and applied to the shift input terminal ST of the shift register SHT. As a result, the shift register SHT shifts the contents of the pulse width signal SAQ input from the counter ACNT by one bit in the direction of the lower bits, and sets 0 to the most significant bit which has become blank. As a result, the contents of the pulse width signal SAO input from the counter A(:NT) are divided by the divisor, that is, 2, corresponding to the pulse center time position T of the input pulse, that is, the trigger signal 5IIJ. That is, the time width T/2 from the desired pulse center time position T0 to the rear end time position of the trigger signal S1.
is calculated.

The division result in the shift register SHT is applied from its output terminal Q to a NOT circuit NOT included in the subtraction circuit C as a division signal Sso. The NOT circuit NOT inverts the division signal Ssa and supplies it to the data input terminal B of the full adder ADD as an inverted division signal Sso. In the subtraction circuit C, a desired setting delay time T is set for the setting circuit SET.
sET is set, and its contents are applied from the output terminal to the data input terminal A of the full adder ADD as a set delay signal Ss.

In the full adder ADD, the setting delay signal S8 inputted to the data input terminal A and the inverted division signal Ssa inputted to the data input terminal B are converted into a carry signal ゛1°° inputted to the carry input terminal C. is added to the set delay time TsET set as a result for the setting circuit SET.
By subtracting the division result T/2 in division circuit B from T IIET
−T/2 is calculated.

The result is given as a delay command signal SF from the output terminal F of the full adder ADD to the data input terminal A of the comparator circuit CMP included in the output circuit. At this time, a clock pulse signal Ssex starts to be generated from the output terminal Q4 of the control pulse generation circuit CTR in accordance with the rear end time position of the input pulse, that is, the trigger signal SL, and is applied to the clock pulse input terminal CK of the counter BCNT. Therefore, the counter BCNT starts counting the number of pulses included in the clock pulse signal Sacx. Since the count value of the counter BCNT is given to the data input terminal B of the comparator circuit CMP as the count value signal SBQ, the count value is applied to the delay command signal S, which is given to the data input terminal A of the comparator circuit CMP. When the contents match the actual delay time TsET-T/2, a pulse center detection signal is generated in the comparator circuit CMP, and a pulse-shaped trigger signal T1. Random access memory RA
M, is applied to the trigger end of M.

The pulse center detection signal, that is, the trigger signal TI, is applied to the clear input terminal CL of the control pulse generation circuit CTR and the clear input terminal CL of the counter BCNT, and clears the contents of the control pulse generation circuit CTR and the counter BCNT. Input pulse or trigger signal 5IIJ
be prepared for the arrival of

Prior to that, the control pulse generating circuit CTR outputs the output terminal Q.
, generates a clear signal SCL from counter ACNT.
, and clears the counter ACNT, and the subsequent input pulse, that is, the trigger signal S1.
Be prepared for the arrival of J.

In the above description, the comparison amplifier circuit 322□.

322,...,322. I,;322□,,32
2゜2. ..., 3222°:...:322,,. 3
22.2. ..., 322. Although the case where n is included has been described, the present invention is not limited to this, and also includes the case where these are removed.

In addition, in the above description, the case where the imaging device 32 is formed by a plurality of optical sensors arranged in a matrix has been mainly described, but the present invention is not limited to this, and can be formed into a desired shape (for example, a curved It also includes the case where an imaging device is formed by arranging a plurality of optical sensors in the form of (a).

Furthermore, although the light projector pressure generates the slit light, the present invention is not limited to this. For example, when it is desired to ensure the intensity of the light generated by the light projector, the light projector can be It also covers cases where the device generates a beam of light. In this case, the optical sensors of the imaging device may be arranged in one row.

In addition, although the imaging device 32 includes a decoder circuit 327, the present invention is not limited to this, and the decoder circuit 327 is removed and the storage device 3241.324□
,..., 324. Random access memory R of Il
A.M.

The RAM, . . . , RAL and the storage device 42 of the data processing device 40 may be shared and formed into a single storage device.

(3) Effects of the Invention As is clear from the above, the object measuring device according to the present invention has the following advantages.

(a) A light projector that generates light for scanning the measurement area; (b) The light generated by the projector is reflected by a measurement object placed in the measurement area (c) an imaging device that converges the reflected light to form an image of the light reflection point on the object to be measured; (c) an imaging device that is operated by the image of the reflection point formed by the imaging device and that a first optical sensor device comprising a plurality of optical sensors arranged to form at least one group along the scanning direction of the measurement area; (e) a reset end connected to the second photosensor device and a scanning reference generated by light sensing of the second photosensor device; a counting circuit that counts the number of clock pulses applied to the input terminal after being reset by a signal; (f) attached one to one for each group of optical sensors belonging to the first optical sensor device; (g) each of the optical sensors belonging to the first optical sensor apparatus; (g) each of the optical sensors belonging to the first optical sensor apparatus; At least one pulse that is attached to the group on a one-to-one basis and that detects the pulse center of the light reception signal output by the optical sensor belonging to the first optical sensor device and provides a trigger signal to the random access memory according to the detection result. a center detection circuit; and (h) a data processing device that receives memory content from the random access memory, calculates a scanning angle of the reflection point by the light projector, and then calculates the position of the reflection point from the calculated scanning angle. Therefore, (i) it has the effect of reducing the mounting area of the obstacle device and, in turn, its mounting cost, and (11) image formation on the plurality of optical sensors belonging to the first optical sensor device. It has the effect of maintaining high resolution even if the optical sensor is out of focus, and (iii) even if there is variation in the sensitivity of components such as a plurality of optical sensors belonging to the first optical sensor device, the pulse width of the light reception signal changes. This has the effect of being able to correct the problem, and also has the effect of avoiding a decrease in accuracy of object measurement due to focus deviation or variation in component sensitivity.

[Brief explanation of the drawing]

FIG. 1 is a perspective view showing an embodiment of the object measuring device according to the present invention, FIGS. 2 and 3 are both enlarged partial circuit diagrams showing a part of the embodiment shown in FIG. 1, and FIG. 1 is an enlarged partial circuit diagram showing a part of the embodiment shown in FIG. 1, and FIG.
A block circuit diagram showing a part of the diagram enlarged, FIG.
7 is a detailed block circuit diagram embodying FIG. 5, FIG. 8 is a time chart diagram for explaining the operation of FIG. 7, and FIG.
The figure is another detailed block circuit diagram embodying FIG.
FIG. 10 is a time chart for explaining the operation of FIG. 9. 10................................................................................... Light projecting device 12................................................................... Slit light generating device 121...・・・・・・・・・・・・Light source 1
22......Cylindrical lens 14...
・・・・・・・・・・・・・・・Scanning device 141 ・
.........Nofu 142...
...Rotary drive device Measured object 30 ...... Light receiving device 31 ...... ......Imaging device 32......Imaging device 3
21°~321□...Phototransistor 322,,
~322□. ... Comparison amplifier circuits 3241 to 324
□ ...Storage device 325 ......
...Counting circuit 326...Clock pulse generation circuit 327...Decoder circuit 33
・・・・・・・・・・・・・・・Scanning detection device 3
31・・・・・・・・・・・・・Phototransistor 33
2・・・・・・・・・・・・Comparison amplifier circuit RAIJ
,・・・・・・・・・・・・・・・Random access memory

Claims (5)

[Claims] (1) (a) A light projector that generates light for scanning a measurement area; (b) The light generated by the light projector is reflected by a measurement object placed in the measurement area. (c) an imaging device configured to converge the reflected light obtained by the imaging device to form an image of the light reflection point on the object to be measured; (c) operated by the image of the reflection point formed by the imaging device, and a first optical sensor device comprising a plurality of optical sensors arranged to form at least one group along the scanning direction of the measurement area by the light projection device; (e) a reset terminal is connected to the second photosensor device, and the reset terminal is connected to the second photosensor device; (f) a counting circuit that counts the number of clock pulses applied to the input terminal after being reset by the scan reference signal that has been reset; and (f) attached one to one for each group of optical sensors belonging to the first optical sensor device (g) at least one random access memory in which the counting contents of the counting circuit are input and stored when the optical sensor belonging to the first optical sensor device is operated; It is attached one-to-one to each group of optical sensors, detects the pulse center of the light reception signal output by the optical sensor belonging to the first optical sensor device, and provides a trigger signal to the random access memory according to the detection result. at least one pulse center detection circuit; (h) a data processing device that receives memory content from the random access memory, calculates the scanning angle of the reflection point by the light projector, and then calculates the position of the reflection point from the calculated scanning angle; An object measuring device comprising: (2) The pulse center detection circuit includes (a) a pulse width measurement circuit that measures the pulse width of the light reception signal and outputs it as a pulse width signal, and (b) a light reception signal that is input as a pulse width signal from the pulse width measurement circuit. By dividing the pulse width of by 2, calculate the time width from the pulse center time position of the received light signal to the trailing edge time position,
(c) A pulse center detection signal is output from the rear end time position of the received light signal by subtracting the time width input as the division signal from the division circuit from the desired delay time. (d) a subtraction circuit that calculates the time width to the desired time position and outputs it as a delay command signal; The object measuring device according to claim 1, further comprising an output circuit that generates a pulse center detection signal at a time position and outputs it as a trigger signal to a storage device. (3) The pulse center detection circuit has: (a) one input end connected to the output end of the clock pulse generation circuit and the other input end connected to the optical sensor belonging to the first optical sensor device; a gate circuit that allows a clock pulse signal given from a clock pulse generation circuit to pass during a period when a light reception signal is arriving from the optical sensor to which the optical sensor device 1 belongs; (b) a clock input terminal for the output terminal of the gate circuit; (c) a counter for counting the number of pulses included in the clock pulse signal passed through the gate circuit, measuring the pulse width of the light reception signal, and outputting the pulse width signal as a pulse width signal; a control pulse generation circuit whose control terminal is connected to the optical sensor belonging to the optical sensor device and whose clock pulse input terminal is connected to the output terminal of the clock pulse generation circuit; (d) data input to the output terminal of the counter; The load input terminal and shift input terminal are respectively connected to the load output terminal and shift output terminal of the control pulse generation circuit, and the time width of the received light signal input as a pulse width signal from the counter is divided by 2. (e) A shift register that calculates the time width from the pulse center time position to the trailing edge time position of the received light signal and outputs it as a division signal; By subtracting the time width input as the division signal from the desired delay time, the time width from the rear end time position of the received light signal to the time position where the pulse center detection signal should be output is calculated, and the time width is calculated as the delay command signal. (f) a data input terminal is connected to the output terminal of the subtraction circuit, and a load input terminal and a clock pulse input terminal are respectively connected to the other load output terminal and clock pulse output terminal of the control pulse generation circuit; When the number of pulses corresponding to the time width input as the delay command signal from the subtraction circuit is given as a clock pulse signal from the control pulse generation circuit, a pulse center detection signal is generated, and the pulse center detection signal is output from the output terminal to the storage device. The object measuring device according to claim 1, further comprising a down counter that outputs a trigger signal toward the object. (4) The pulse center detection circuit has: (a) one input terminal connected to the output terminal of the clock pulse generation circuit and the other input terminal connected to the optical sensor belonging to the first optical sensor device; (b) a gate circuit that allows a clock pulse signal given from a clock pulse generation circuit to pass during a period when a light reception signal is received from an optical sensor belonging to the optical sensor device 1; (b) a clock input terminal for the output terminal of the gate circuit; (c) a counter for counting the number of pulses included in the clock pulse signal passed through the gate circuit, measuring the pulse width of the light reception signal, and outputting the pulse width signal as a pulse width signal; a control pulse generation circuit whose control terminal is connected to the optical sensor belonging to the optical sensor device and whose clock pulse input terminal is connected to the output terminal of the clock pulse generation circuit; (d) data input to the output terminal of the counter; The load input terminal and shift input terminal are respectively connected to the load output terminal and shift output terminal of the control pulse generation circuit, and the time width of the received light signal input as a pulse width signal from the counter is divided by 2. (e) A shift register that calculates the time width from the pulse center time position to the trailing edge time position of the received light signal and outputs it as a division signal; By subtracting the time width input as the division signal from the desired delay time, the time width from the rear end time position of the received light signal to the time position where the pulse center detection signal should be output is calculated, and the time width is calculated as the delay command signal. (f) A clock pulse input terminal is connected to the clock pulse output terminal of the control pulse generation circuit, and after the input pulse is removed, the clock pulse is output from the clock pulse output terminal of the control pulse generation circuit. (g) A counter whose data input terminal is connected to the output terminal of the subtraction circuit and whose data input terminal is connected to the output terminal of the other counter. Another data input terminal is connected, and when the time width inputted as a delay command signal from the subtraction circuit and the count value inputted as a count value signal from another counter match, a pulse center detection signal is generated; An object measuring device according to claim 1, further comprising a comparison circuit that outputs a trigger signal from an output end to a storage device. (5) The subtraction circuit includes: (a) a not circuit whose input terminal is connected to the output terminal of the shift register and which inverts the division signal given from the shift register and outputs it as an inverted division signal; (b) as desired (c) One data input terminal is connected to the output terminal of the NOT circuit, and the other data input terminal is connected to the output terminal of the setting circuit. is connected, and by adding 1 to the inverted division signal input from the NOT circuit and the setting delay signal input from the setting circuit, the pulse center detection signal is output from the rear end time position of the received light signal. Claims (3) or (4), comprising a full adder that calculates the time width to the desired time position and outputs it as a delay command signal.
Object measuring device described in section.