JPH0272408A - Programmable controller - Google Patents

Abstract

PURPOSE:To shorten the processing time of the sequence instructions by detecting automatically the end of a sequence circuit for sequence instructions supplied continuously and carrying out en bloc the sequence instructions of one sequence circuit. CONSTITUTION:The last sequence instruction of a sequence circuit supplied from an input means 100 serves as output instruction for the sequence arithmetic result, e.g., the instructions for the write to a memory, the display on a display device, and the output to a printer. These specific sequence instructions are detected by a detecting means 200 and the divisions of the sequence instructions supplied continuously are detected. Then the codes showing the divisions are stored in a memory means 300. As a result, an arithmetic process means 400 can carry out en bloc the sequence instructions for each sequence circuit. Thus the shift processes are decreased for various arithmetic programs which are executed in accordance with execution of the sequence instructions. Then the processing time can be shortened for the sequence instructions.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a programmable controller that controls the operation of electronic equipment according to sequence commands.

(Prior Art) Conventionally, programmable controllers store sequence commands input from a programming device called a loader in a user program memory within the programmable controller, and execute sequence commands input from the programming device in response to sequence execution commands input from the programming device. The sequence instructions stored in the user program memory are read and executed.

Recently, it has become possible to input sequence commands in correspondence with the graphics of the sequence circuit, making the input operation easier for the operator and shortening the input operation time.

(Problem to be Solved by the Invention) However, there is still room for improvement in shortening the execution processing time of sequence instructions of a programmable controller.

This point will be explained in detail.

FIG. 8 shows the circuit configuration of a sequence circuit input to the programmable controller, and is shown in the form of a loader diagram.

This sequence circuit shows the following sequence operation processing. That is, add the value of the relay contact "'WBO" of the data memory in the programmable controller and the value of the relay contact "BI) 0°°. Next, divide the addition result by the value indicated by °'d123°°. , and stores the division result in the relay contact "WBIOoo" of the data memory. In addition, the above addition result is multiplied by the numerical value ""d123°", and the multiplication result is applied to the relay contact "BDI" of the data memory.
”.

The operator inputs such a sequence command using the character keys and graphic keys of the loader, and displays the input graphic on the display on the loader to confirm the sequence command to be input.

On the other hand, the programmable controller analyzes the sequence circuit input in the form of a graphic, converts it into a sequence command in a high-level language or a simple language, and stores it in a user program memory inside the programmable controller.

FIG. 9 shows a memory map of the user program memory, and shows an example in which the sequence circuit shown in FIG. 6 is converted into sequence instructions and stored.

In FIG. 9, °'IN" represents a data read command. Corresponding to this "IN" command, the addresses °'WBO, BDO°° of the tip of the blade and the display position "0'' of this address data on the display (Line) “1′° (Line) is stored in each area.

Note that the “10” instruction is an addition instruction, the “CON” instruction is a sequence instruction connection instruction, and the “÷PA” instruction is a division instruction “X”.
The "instruction" means a multiplication command, and the "OUT command °' means a data write command. Further, "E" is an end code indicating a break in sequence operations.

Next, the operation of the central processing unit (CPU) of the programmable controller when such a sequence command is input in the form of a graphic and when executing the sequence command will be explained with reference to FIG. 1O and the 11th flowchart. explain.

When the operator inputs a sequence command from the loader using character keys and graphic keys, the input interrupt process shown in FIG. 8 is executed every time this sequence command is input. That is, the CPU analyzes the input character code or graphic code and its input position, and converts it into a code representing a sequence command.

Subsequently, data related to the calculation command storage area, display position storage area, delimiter code storage area, calculation data storage area, and cutting edge address storage area shown in FIG. 9 are stored, respectively. (Steps 510-530).

In addition, the CPU causes the input command to be graphically displayed on the display of the loader in response to this input. (Step 540).

After the sequence command is stored in the user program memory in this way, when the operator instructs the execution of this sequence command from the loader, the CPII detects the input of the sequence command and follows the program execution procedure shown in FIG. (Steps 510→520-550).

In this program execution process, the CPU reads one sequence instruction in the knee subprogram memory, converts the sequence instruction into machine language for operating the CPU, and then executes this sequence instruction. For example, in the sequence circuit shown in FIG.
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In order to execute the sequence instruction ``6 times, instruction reading, machine language conversion, and arithmetic processing are performed six times.

However, in order to transition from, for example, an instruction reading program to a machine language conversion program, the CPU must perform execution program transition processing.

In the above example, three program execution processes and two program migration processes are performed for one sequence instruction. Therefore, 12 program transfer processes must be performed using six sequence instructions.

If it is possible to batch-process sequence instructions for one sequence circuit unit, it is possible to complete the batch reading of sequence instructions, batch translation of sequence instructions into machine language, batch execution of machine language, and two program migration processes. can be predicted.

However, since the number of sequence commands input by an operator in one sequence circuit is unspecified, the CPU in a conventional programmable controller selects the sequence command at the beginning of the sequence circuit from among the sequence commands input continuously. It was not possible to automatically detect the end sequence instruction. As a result, since the above-mentioned read processing, machine language conversion processing, and machine language execution processing must be performed for each sequence operation instruction, the problem is that the CPU's program transfer processing increases and the sequence program execution processing time becomes longer. was occurring.

Therefore, the purpose of the present invention is to solve this problem,
To provide a programmable controller capable of automatically detecting the end of a sequence circuit of continuously inputted sequence commands and shortening the processing time of sequence commands by collectively executing the sequence commands of one sequence circuit.

[Means for Solving the Problems] In order to achieve such an object, a first form of the tree invention includes an input means for inputting a sequence command, and a sequence command inputted from the input means is inputted into one sequence circuit. A detection means for detecting a specific sequence command located at the end of one sequence circuit, and a detection means for storing a sequence command sequentially inputted from the input means, When a sequence command is detected, a delimiter code is added to the sequence command and stored in the storage means;
The present invention is characterized by comprising an arithmetic processing means for reading out and executing one or more sequence instructions sandwiched between delimiter codes all at once in response to an instruction to execute a sequence operation.

A second form of the tree invention is an input means for inputting sequence commands, a storage means for storing sequence commands sequentially inputted from the input means, and a specific sequence located at the end of the sequence circuit of the storage means. The present invention is characterized in that it includes a readout unit that detects an instruction and reads out the sequence instruction from the storage unit in units of sequence circuits, and an arithmetic processing unit that collectively executes the sequence instructions read out from the readout unit.

(Function) The present invention focuses on the fact that the last sequence instruction of the sequence circuit is an instruction to output the sequence operation result, for example, an instruction to write to memory, display on a display, output to a printer, etc. In the first embodiment of the present invention, by detecting these specific sequence commands with a detection means, a break in sequentially input sequence commands is detected, and is stored by adding a ρ means and a code indicating this break. I'll keep it. As a result, it becomes possible to execute sequence instructions in batches in units of one sequence circuit, and the transition processing of various arithmetic programs that is performed in conjunction with the execution of sequence instructions is greatly reduced, so the processing time for sequence instructions is also significantly reduced. It will be shortened to .

In the second embodiment of the present invention, when reading the sequence commands stored in the storage means, the reading means detects the output command and detects the break in the sequence circuits, so that the sequence commands are executed in batch for each sequence circuit. becomes possible.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows the basic circuit configuration of an embodiment of the present invention.

In FIG. 1, 1,100 is an input means for inputting sequence commands.

200 is a detection means for detecting that the sequence command input from the input means is a specific sequence command located at the end of one sequence circuit.

300 stores the sequence commands sequentially inputted from the input means, and when the detection means detects a particular sequence command located at the end of one sequence circuit, it adds a delimiter code to the sequence command. This is a storage means for storing additional information.

Reference numeral 400 denotes an arithmetic processing means that is stored in the storage means and reads out and executes one or more sequence instructions sandwiched between the delimiter codes all at once in response to an instruction to execute a sequence operation.

FIG. 2 shows a specific circuit configuration of an embodiment of the present invention.

In FIG. 2, a block 10 surrounded by a dashed line indicates a programmable controller.

In the programmable controller 1o, l executes the sequence command input by the user and outputs the external device 30.
This is the central processing unit (CPIJ) that controls the operation of the computer.

2 is a random access memory (R
AM).

3 is a program for translating the sequence instructions stored in the user program RAM 2 into machine language, a well-known system program for controlling the operation of each component in the programmable controller IO, and a book shown in FIGS. 4 and 5. This is a read-only memory (ROM) for a system that stores in advance a control program related to the invention.

4 is a data RAM that temporarily stores data exchanged between the external device 30 and the loader 20; Reference numeral 5 denotes an interface (Ilo) for manually outputting data exchanged with the loader 20 and external equipment 30.

20 is a program input device called a loader, which has a keyboard for inputting sequence commands and a display for displaying input information. The keyboard also includes a control processing instruction key 20-1 which is related to the present invention and which instructs batch input of sequence commands in sequence circuit units.
is provided.

Here, the input means corresponds to the loader 20, the detection means and the arithmetic processing means correspond to the CPUI, and the eleventh line means corresponds to the user program RAM 2.

FIG. 3 shows a memory map of the user program RAM 2 shown in FIG.

The memory map shown in this figure has the same memory area configuration as the conventional memory map shown in FIG. 9.

However, in the embodiment of the present invention, the end code is additionally stored only in the 'OUT' instruction indicating the end of the sequence circuit, whereas in the conventional example shown in FIG. has been done.

4 and 5 show a control procedure for batch processing of sequence instructions executed by the CPU 2 shown in FIG.

The operation of the embodiment of the present invention will be explained with reference to FIGS. 4 and 5.

Note that the sequence command to be input is the sequence command shown in FIG. 8, which was used to explain the prior art.

In FIG. 4, when the operator inputs a sequence command from the loader 20, the CPII I confirms that the input information is a sequence command and writes the sequence command to the program RAM 2 for 1,:I-1' (step 5looo). -sno-5120-5130).

? The CI" 111 displays the input sequence command in the form of a sequence circuit graphic on the display of the loader 20 (step 5140). When input, CPIJl becomes “0IJ” as shown in Figure S3.
The end code (E) is written to the user program RAM 2 together with the T” command (steps 5120→512
5 → 5130).

When inputting a sequence command is completed and the operator instructs execution of the sequence program from the loader 20, the CP
IJI responds to this instruction (step 100→5110→
5150), the process moves to the sequence instruction execution process shown in FIG.

In FIG. 5, the CPU 1 reads one or more sequence instructions sandwiched between end codes, converts them into machine language, and then executes the sequence instructions in the machine language form at once (steps 5151-5152-515:l).

In this embodiment, in order to execute sequence instructions in one sequence circuit level, the 8-line processing of the program performed by CPt11 is the transition process from the 6-arithmetic instruction read processing program to the machine language conversion program and the machine language conversion program. There are only two transfers from the program to the arithmetic processing program. As explained in the prior art, in the conventional example, when executing a sequence circuit consisting of 6 sequence instructions, 12 (6X
2) Since multiple line processing is required, the CPU processing time is shortened by the reduction in program migration processing.

In addition, in the conventional example, a delimiter code (end code) was written to each sequence instruction when writing the sequence instruction to the user program memory each time a sequence instruction was input. In the embodiment, since it is possible to write the delimiter code for each sequence circuit unit, the @ writing process of the delimiter code is also reduced, and the CP
Contributes to shortening UI processing time.

Although this embodiment shows an example in which sequence commands are input in graphical form, the present invention can also be applied to programmable controllers in which sequence commands are input in a high-level language such as Hessic or Fortran, or in a simple language created by each manufacturer. Needless to say, it is applicable.

FIG. 6 shows the basic configuration of a second embodiment of the present invention.

In FIG. 6, 500 is an input means for inputting sequence commands.

Reference numeral 600 denotes a storage means for storing the sequence commands sequentially inputted from the input means.

Reference numeral 700 denotes a reading unit for detecting a specific sequence command located at the end of a sequence circuit in the storage unit and reading out the sequence command from the storage unit in units of sequence circuits.

800 is an arithmetic processing means that collectively executes the sequence instructions read out from the reading means.

The specific configuration of the second embodiment can be almost the same as that of the first embodiment shown in FIG.
The difference is that No. 1 executes the control procedure shown in FIG. 7 instead of the control procedure shown in FIG.

FIG. 7 shows the sequence program execution procedure in the second embodiment of the present invention. That is, in this example, C
The PU 1 sequentially stores sequence commands input from the loader 30 as an input means into the user program RAM 2 as a storage means.

At this time, the end code is not additionally stored. Next, when the CPU 1 serving as a reading means reads out a sequence instruction from the M2 to the user program R to execute the sequence instruction (step 5200), when it detects that the read instruction is an output instruction, the CPt1l The reading of the sequence command is finished, and the conversion process to machine language and the sequence command in machine language form are executed (steps 5203→5204).

In this embodiment, the knee subprogram l'l
There is no need to store the end coat in AM2, which has the advantage of saving memory capacity.

[Effects of the Invention] As described above, according to the first embodiment of the present invention, the last sequence instruction of the sequence circuit is an instruction to output a sequence operation result, for example, write to a memory, Focusing on the fact that the commands are to be displayed on a display, output to a printer, etc., the first embodiment of the present invention detects these specific sequence commands using a detection means, thereby detecting the break between successive input sequence commands. is detected, and a storage means and a code indicating this delimiter are added and stored. As a result, it becomes possible to execute sequence instructions in batches in units of one sequence circuit, and the transition processing of various arithmetic programs that is performed in conjunction with the execution of sequence instructions is greatly reduced, so the processing time for sequence instructions is also significantly reduced. It will be shortened to .

In the second JFs mode of the present invention, when reading out the sequence commands stored in the recording means, the reading means detects the break in the output command sequence circuits, so that the sequence commands are executed in batch for each sequence circuit. You can get the effect that it is possible.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the basic circuit configuration of the embodiment of the present invention, Figure 2 is a circuit diagram showing the specific circuit configuration of the embodiment of the invention, and Figure 3 is the user program of the embodiment of the invention. 4 and 5 are flowcharts showing the control procedure executed by the CPIII shown in FIG. 2; FIG. 6 is a block diagram showing the basic configuration of the second embodiment of the present invention; FIG. 7 is a flowchart showing the control procedure executed by the CPIII shown in FIG. 2, FIG. 8 is a circuit diagram showing the configuration of a sequence circuit shown in the form of a ladder diagram of the conventional example, and FIG. 9 is a diagram of the user program memory of the conventional example. Memory map showing memory configuration. FIGS. 1O and 11 are flowcharts showing control means executed by a conventional CPU. 1... CPU, 2... User program RAM, 3... System ROM, 4... Data RAM, 5... Bow 10, lO... Programmable controller, 20... Loader, 30... ··External device. 10 ゛O'7 skill map, ・Refsito 0-ra \ somden, j column 0 times Tito section 2 \ light mouth moon z text, 0 flow diagram 4 2 u 1 pu ゛ flop RAM) Also, the four main points are the f column, the first one, and the RAM2, < 5-:, l ma,
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Claims (1)

[Claims] 1) An input means for inputting a sequence command, and detecting that the sequence command inputted from the input means is a specific sequence command located at the end of one sequence circuit. a detection means for storing the sequence commands sequentially input from the input means, and when the detection means detects a specific sequence command located at the end of one sequence circuit, dividing the sequence command into the sequence command; a storage means for adding and storing codes; and an arithmetic processing means for reading out and executing one or more sequence instructions stored in the storage means and sandwiched between the delimiter codes at once in response to an instruction to execute a sequence operation. A programmable controller characterized by comprising: 2) input means for inputting sequence commands; storage means for storing the sequence commands sequentially input from the input means; and storage means for storing a specific sequence command located at the end of the sequence circuit in the storage means It is characterized by comprising: a reading means for detecting and reading out the sequence instructions from the storage means in units of sequence circuits; and an arithmetic processing means for collectively executing the sequence instructions read from the reading means. programmable controller.