JPH02672U - - Google Patents
Info
- Publication number
- JPH02672U JPH02672U JP7898888U JP7898888U JPH02672U JP H02672 U JPH02672 U JP H02672U JP 7898888 U JP7898888 U JP 7898888U JP 7898888 U JP7898888 U JP 7898888U JP H02672 U JPH02672 U JP H02672U
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- printed circuit
- energized
- deterioration
- original
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000006866 deterioration Effects 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 238000012423 maintenance Methods 0.000 description 2
Landscapes
- Testing Electric Properties And Detecting Electric Faults (AREA)
Description
第１図は本考案の劣化度測定回路を搭載したプ
リント基板の一実施例の構成概念図、第２図は第
１図に示すプリント基板の回路図、第３図は測定
回路に使用したコイルのおおよその劣化特性図で
ある。
符号の説明、１……プリント基板、２……実装
部品、３……プリント基板の劣化度測定回路、４
……抵抗、５……コイル、６……電源、７……ア
ースライン、Ｌ……コイルのインダクタンスＬ、
Ｔ……通電時間（劣化度の目安とする）、Ｌ０…
…メインテナンス時のコイルのインダクタンス、
Ｔ０……メインテナンス時までの通電時間。
Figure 1 is a conceptual diagram of the configuration of an embodiment of a printed circuit board equipped with the deterioration measurement circuit of the present invention, Figure 2 is a circuit diagram of the printed circuit board shown in Figure 1, and Figure 3 is a coil used in the measurement circuit. FIG. 2 is an approximate deterioration characteristic diagram of Explanation of symbols, 1...Printed board, 2...Mounted components, 3...Printed board deterioration measurement circuit, 4
...Resistance, 5...Coil, 6...Power supply, 7...Earth line, L...Coil inductance L,
T...Electrification time (as a guide to the degree of deterioration), L0 ...
...Coil inductance during maintenance,
T 0 ...Electrification time until maintenance.
Claims (1)
させてそのプリント基板上に実装し、且つ本来の
回路への通電時に同時通電されるように電源を共
通としたプリント基板の劣化度測定回路。 A circuit for measuring the degree of deterioration of a printed circuit board, in which electrical parts are mounted on the printed circuit board independently of the original circuit of the printed circuit board, and a common power source is used so that the electric parts are energized at the same time when the original circuit is energized.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7898888U JPH02672U (en) | 1988-06-15 | 1988-06-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7898888U JPH02672U (en) | 1988-06-15 | 1988-06-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02672U true JPH02672U (en) | 1990-01-05 |
Family
ID=31303877
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7898888U Pending JPH02672U (en) | 1988-06-15 | 1988-06-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02672U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011097153A (en) * | 2009-10-27 | 2011-05-12 | Fujitsu Ltd | Printed circuit board and information processing apparatus |
-
1988
- 1988-06-15 JP JP7898888U patent/JPH02672U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011097153A (en) * | 2009-10-27 | 2011-05-12 | Fujitsu Ltd | Printed circuit board and information processing apparatus |
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