JPH0266624A - Data processor - Google Patents

Abstract

PURPOSE:To perform a series of arithmetic actions at a high speed by adding plural computing elements connected to a shared bus to an instruction executing means and supplying data again through an exclusive register which stores the arithmetic result with no intervention of the shared bus. CONSTITUTION:A barrel shifter 16 transfers the arithmetic subject data and the arithmetic result data via the internal buses BUS1, BUS2 and BUS3 serving as the shared buses, receives the arithmetic subject data with no intervention of those internal buses and also stores the arithmetic result data. In other words, the exclusive registers 28 and 29 are prepared for the shifter 16. The output terminal of the register 28 is connected to the BUS1 as well as to the input terminal of a selector 22. The output terminal of this selector 22 is connected to one of two input terminals of the shifter 16. The output terminal of the register 29 is connected to the BUS2 as well as to the input terminal of a selector 24 whose output terminal is connected to the other input terminal of the shifter 16.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to data processing devices, as well as the configuration of arithmetic units and registers for arithmetic and logic operations, and is a technology that is effective when applied to, for example, microprogram-controlled processors. It is related to.

[Prior art]

The execution unit of a data processing device such as a processor includes an arithmetic and logic unit, a barrel shifter, and various registers called source registers and destination registers. Conventionally, these registers share one or more internal buses. combined. When performing the required calculations in such an execution part.

The data in the source register is given to the arithmetic unit via the internal bus, and the result of the arithmetic operation is stored in the destination register. In such an operation cycle, the data to be operated on is always given to the required arithmetic unit from the internal bus, and the operation result is returned to the required register via the internal bus, so basically one operation cycle Only arithmetic units can be operated.

An example of a document that describes the configuration of the arithmetic units and registers included in the execution section is rI published in May 1981.
EEE Micro” pages 26 to 38.

[Problem to be solved by the invention]

In the conventional configuration, in which the data to be operated on is always given from the register to the arithmetic unit via the shared bus, and the operation result data is also returned to the required register via the internal bus, it is necessary to avoid contention of transferred data on the internal bus. Basically, only one arithmetic unit can be operated in one arithmetic cycle, so when a series of arithmetic operations is performed cyclically using multiple arithmetic units, the operation corresponds to the number of times the arithmetic unit is used. Steps were required, and there was a limit to speeding up arithmetic processing. For example, when multiplying an n-bit multiplicand by an n-bit multiplier by adding and shifting using an arithmetic logic unit and a barrel shifter, 20 bits are generated with 0 in the upper n bits and the multiplier in the lower n bits. . When the least significant bit of these 2n bits is 1, add the multiplicand to the upper n bits, and when it is 0, add 0 to the upper n bits, and for this result, move the 2n bits as a whole to the right (
Then, the same operation is repeated n times, and the remaining 2n bits are used as the multiplication result. At this time, the values obtained from individual addition operations and values obtained from shift operations are stored in shared registers, respectively.
In order to transfer the values obtained from the addition operation and the values obtained from the shift operation to the shared register, the internal bus shared by each arithmetic unit must be used. Such a multiplication requires at least 2n operating cycles to avoid conflicts in transferred data.

An object of the present invention is to provide a data processing device that can speed up a series of arithmetic operations using a plurality of arithmetic units.

The above and other objective and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the execution means for executing instructions is provided with a plurality of arithmetic units connected to a shared bus, and data can be supplied to the arithmetic units again from a dedicated register that stores the results of five operations without passing them through the shared bus. It consists of:

At this time, it is desirable to be able to selectively supply the output data of the dedicated data register or the data given from the shared bus to the arithmetic unit via a selector in order to make general use of the arithmetic unit. Various calculation controls including selection control of input data by the selector can be controlled by microinstructions.

[For production]

According to the above-mentioned means, when a certain arithmetic unit processes data given from a shared bus and gives the processing result to the shared bus, other arithmetic units process data given from a dedicated register or send the result of the operation to the shared bus. This allows multiple arithmetic units to perform parallel arithmetic processing in the same arithmetic cycle by avoiding contention on the shared bus. Works to achieve high speed.

〔Example〕

FIG. 4 shows a processor which is an embodiment of the data processing apparatus according to the present invention. Processor 1 shown in the figure
is formed on a single semiconductor substrate such as a silicon substrate by a known semiconductor integrated circuit manufacturing technique, although it is not particularly limited.

This processor 1 has a control form in which a macro instruction is fetched from an external program memory (not shown) connected via an input/output circuit 2, and the instruction is executed by an execution unit 3 based on microprogram control.

A microprogram describing various arithmetic processing procedures by the execution unit 3 is stored in a micro ROM (read-only memory) 4. This micro ROM4 is
The microinstructions constituting the microprogram are sequentially read out by being accessed by the output of an instruction decoder 6 that decodes the instruction code of the macroinstruction fetched by the instruction fetch unit 5 and the output of the sequence controller 7.

The instruction fetch unit 5 fetches macro instructions provided from a memory (not shown) via the input/output circuit 2 and the instruction fetch bus 8. The instruction decoder 6 accesses the micro ROM 4 based on address information obtained by decoding the instruction code included in the macro instruction.

As a result, the first microinstruction of a series of microinstructions for performing the arithmetic processing specified by the macroinstruction is read out. For the second and subsequent microinstructions in a series of microinstructions for performing arithmetic processing instructed by the macroinstruction, the information in the netast address field of the microinstruction read immediately before is supplied to the sequence controller 7. Directed by what is done. The micro-instructions read out from the micro-ROM 4 in this manner are supplied to the micro-instruction decoder 9. This microinstruction decoder 9 decodes the applied microinstruction and generates a control signal 10 for the execution unit 3 and the like.

The execution unit 3 performs data and address calculations based on the control signal 1o output from the microinstruction decoder 9, and is coupled to the input/output circuit 2 via the internal data/address bus 11. Furthermore, the internal data/address bus 11
The selection of which of the instruction fetch buses 8 to interface with the outside is controlled based on instructions from the sequence controller 7, and the instruction fetch bus 8 is selected in the instruction fetch cycle.

FIG. 1 shows an example of a data calculation system included in the execution section 3.

The data calculation system of this execution unit 3 is not particularly limited, but
Arithmetic logic unit 15. It is provided with a 1-bit shifter 17 and a barrel shifter 16 as arithmetic units, and also has three shared registers 18-20. These computing units 15 to 17
and the shared registers 18 to 20 are not particularly limited, but
Basically, internal buses BUSI, BUS2 .
Share BUS3. That is, the operation results by the arithmetic and logic operator 15 and the shift operation results by the barrel shifter 16 are applied to the internal bus BUS3, and the input terminals of the shared registers 18 to 2o are coupled to the internal bus BUS3. The bus BUSI is coupled to the output terminal of the shared register 19 and the input terminal of the shifter 17, and also to one input terminal of the arithmetic and logic unit 15 via the selector 21, and further to one of the barrel shifter 16 via the selector 22. It can be connected to the input terminal of Above internal bus BUS2
is coupled to the output terminal of the shared register 18.20, and can be connected to the other input terminal of the arithmetic and logic unit 15 via the selector 23, and further to the other input terminal of the barrel shifter 16 via the selector 24. It looks like this.

The barrel shifter 16 performs a shift operation of an arbitrary number of bits on data applied to both input terminals via the selectors 22 and 24, although this is not particularly limited. here,
The barrel shifter 16 transfers calculation target data and calculation result data to an internal bus BUSI.

BUS2. In addition to communicating via BUS3, these internal buses BUSI, BU32, and BUS as shared buses
3, data to be calculated can be received and the data resulting from the calculation can be stored. That is, dedicated registers 28 and 29 are provided for the barrel shifter 16, and the output terminal of one of the dedicated registers 28 is coupled to the input terminal of the selector 22 together with the internal bus BUS1. The output terminal of this selector 22 is the barrel shifter 16
is coupled to one input terminal of In addition, the output terminal of the other dedicated register 29 is connected to the barrel shifter 1.
The input terminal of the selector 24, which is coupled to the other input terminal of the selector 6, is coupled together with the internal bus BUS2. and,
The input terminals of the dedicated registers 28 , 29 are coupled to the output terminals of the barrel shifter 16 . In addition, the barrel shifter 1
Between the output terminal of 6 and the internal bus BUS3, when only the dedicated register 28 or 29 takes in the output of the barrel shifter 16, there is a connection so that other data on the internal bus BUSa is not destroyed by such output data of the barrel shifter 16. In order to achieve this, a gate 30 is provided which can selectively assume a high output impedance state.

Selection control of the selectors 22 and 24, input/output control of the dedicated registers 28 and 29, output control of the gate 30, and shift operation by the barrel shifter 16 are controlled according to a microprogram.

The arithmetic and logic unit 15 performs addition and subtraction on data supplied from both input terminals via the selectors 21 and 23, although this is not particularly limited. Here, the arithmetic and logic unit 15 exchanges operation target data and operation result data via internal buses BUSI, BUS2, and BUS3, and also uses these internal buses BUSI and BU as shared buses.
Data to be calculated can be received without passing through the S2° BUS3, and data resulting from the calculation can be stored.

That is, a dedicated register 25. for the arithmetic logic unit 15.
26, and the output terminal of one of the dedicated registers 25 is coupled to the input terminal of the selector 21 along with the output terminal of the shifter 17 and the internal bus BUSI. The output terminal of the selector 21 is coupled to one input terminal of the arithmetic and logic unit 15. Also, the other dedicated register 26
The output terminal of is coupled to the input terminal of the selector 23 whose output terminal is coupled to the other input terminal of the arithmetic and logic unit 15. This selector 23 is adapted to receive 4-bit logic "0" data in addition to the data supplied from the dedicated register 26 and the internal bus BUS1, although this is not particularly limited. The input terminals of the dedicated registers 25 and 26 are coupled to the output terminal of the arithmetic and logic unit 15. Note that when only the dedicated register 25 or 26 takes in the output of the arithmetic and logic unit 15 between the output terminal of the arithmetic and logic unit 15 and the internal bus BUS3,
In order to prevent other data on the internal bus BUS3 from being destroyed by such output data of the arithmetic and logic unit 15, a gate 27 is provided which can selectively assume a high output impedance state.

Selection control for the selectors 21 and 23, input/output control of the dedicated registers 25 and 26, output control of the gate 27, and arithmetic operations by the arithmetic and logic unit 15 are basically controlled according to a microprogram. There is. Although not particularly limited, in the selector 23,
In controlling whether to select logical "0" data or data from internal bus BUS2, the least significant bit OFB overflowed by the shift operation of barrel shifter 16 is referred to. Such control is required exclusively for multiplication, the details of which will be explained later.

FIG. 2 shows the selectors 21, 23. Dedicated register 25
, 26, and gate 27 are shown. In the figure, a bus signal line BUS1i for 1 bit of internal buses BUSI, BUS2 and BUS3 is shown.

The configuration regarding BIS2i and BUS3i is shown as a representative.

Although not particularly limited, the dedicated register 25 includes a 2-bit static latch circuit for 1 bit of the bus signal line, and clocked inverters 32 and 33, respectively.
The output of the arithmetic and logic unit 15 is selectively given through an input gate consisting of the following. Although not particularly limited, one static latch circuit includes an inverter 34 and a clocked inverter 35 coupled in feedback to the inverter 34, and similarly, the other static latch circuit includes an inverter 36 and a clocked inverter 37 coupled in feedback to the inverter 34. Consisted of. The clocked inverters 32 and 33 as input gates are selectively controlled by the input control signals φi and φ12, which are part of the control signals 10, and in response, the clocked inverters 35 and 37 are controlled by the control signals φill and φ12. The control gate is controlled by In this embodiment, various clocked inverters are controlled to take a high output impedance state by a low-level control signal, and to be able to output an inverted level of an input signal by a high-level control signal.

The selector 21 includes, but is not particularly limited to, a clocked inverter 38 that receives data from the shifter 17 at its input terminal, a clocked inverter 39 that receives data supplied from the bus signal line BUS 1 i at its input terminal, and the selector 25. a clocked inverter 40 whose input terminal is coupled to the output terminal of an inverter 34, 36 included in the clocked inverter 40;
, 41, and their clocked inverters 38, 39,
It includes a logic matching inverter 42 which is wired-OR coupled to the output terminal of 40°41. The clocked inverters 38, 39, 40, and 41 are selectively controlled by selection control signals φ131 φ141 φ1g+φiG, which are part of the control signal 10.

Similar to the dedicated register 25, the dedicated register 26 also includes a 2-bit static latch circuit for 1 bit of the bus signal line, and each clocked inverter 44.
The arithmetic logic unit 1 is connected to the
5 outputs are selectively given. Although not particularly limited, one static latch circuit includes an inverter 46 and a clocked inverter 47 coupled in feedback thereto, and similarly, the other static latch circuit includes an inverter 48 and a clocked inverter 49 coupled in feedback thereto. Consisted of. Clocked inverters 44, 45 as input gates receive input control signals φ171 φio which are part of 10 of the above control signals.
In response, the control gates of the clocked inverters 47 and 49 are controlled by control signals φlt+φiIl.

The selector 23 includes, but is not particularly limited to, clocked inverters 50 and 51 whose input terminals are coupled to the output terminals of the inverters 46 and 48 that constitute the dedicated register 26;
A clocked inverter 52 whose input terminal is coupled to the bus signal line BUS2i, and these clocked inverters 5
It includes a logic matching inverter 53 which is wired-OR coupled to the output terminals of 0, 51, and 52. The clocked inverters 50, 51, and 52 receive selection control signals φ191 and φi, which are part of the control signal 10. , φi, is selected and controlled. Further, as selection logic for multiplication, a clocked inverter 54 whose input terminal is coupled to the bus signal line BUS2i, and a clocked inverter 55 which receives logic "0" data at its input terminal are connected to the input terminal of the inverter 53 by wired OR. be combined. clocked inverter 5
4 is a multiplication designation control signal φ, which is one of the control signals 1o.
The clocked inverter 55 is selectively controlled by the output of the AND gate 56 which has mtP and the overflow bit OFB.
The selection is controlled by the output signal of an AND gate 57 which uses the inverted signal of the signal outputted from the multiplication designation control signal φmtp and the multiplication designation control signal φmtp. In this multiplication selection logic, when the multiplication designation control signal φm t p is asserted at a high level, if the overflow bit OFB is at a high level, the data supplied from the bus signal line BUS2i is sent to the arithmetic and logic unit 15. Available.

If the overflow bit OFB is at a low level, logical rOJ data can be supplied to the arithmetic and logic unit 15 in place of the data supplied from the bus signal line BUS2i. When the multiplication designation control signal φmtp is negated to low level, the clocked inverters 54 and 55
Both are placed in a high output impedance state.

The gate 27 includes, but is not particularly limited to, a logic matching inverter 60 whose input terminal is coupled to the output terminal of the arithmetic logic unit 15, and a logic matching inverter 60 whose output terminal is coupled to the input terminal and which is connected to a control terminal. is constituted by a clocked inverter 59 to which a selection control signal φ112, which is one of the control groove signals 10, is supplied.

Incidentally, the selectors 22, 24 and the dedicated registers 28, 29 on the barrel shifter 16 side can basically be constructed in the same manner as shown in FIG.

In this way, the barrel shifter 16 and the arithmetic logic operator 15
In calculations using
, the flow of data is obtained from BUS2 and returned to the internal bus BUS3.

It is now possible to select a data flow in which the data to be operated on is obtained from a dedicated register and the result of the operation is returned to the dedicated register.For example, the arithmetic and logic unit 15 transfers the data to be operated on to the internal bus BUSI.

When performing calculations obtained from BUS2, dedicated registers 28.
If you use the data of 29, barrel shifter 1
The shift operation by 6 and the operation to store the result of the operation are as follows.
This can be performed in parallel with the arithmetic and logic operations performed by the arithmetic and logic unit 15 and the operation of storing the operation results. Conversely, the barrel shifter 16 transfers the operation target data to the internal bus BUSI,
If the data in the dedicated registers 25 and 26 is used when performing a shift operation obtained from BUS2, the arithmetic and logic operation by the arithmetic and logic unit 15 and the operation of storing the result of the operation can be performed by the shift operation and the like by the barrel shifter 16. This can be done in parallel to the operation of storing the calculation result.

Next, the operation of this embodiment will be explained using multiplication as an example.

For example, the multiplicands stored in the shared register 20 are
blb, and the multiplier c stored in the shared register 18, Q2
Multiplication with Q1c0 will be explained. The multiplication method at this time is a repeating method of addition and shift operations, and the addition result by the arithmetic and logic unit 15 is stored in the shared register 19, and the result of the shift operation by the barrel shifter 16 is stored in the dedicated register 29. . Note that the control signal φm t p is asserted during the multiplication.

First, the multiplication is performed roughly as shown in the following formula, + c c Xb b, b, b.

aff4 al13a02aolao.

+ c c X b b.

”14 at3a12 atz4 uni+cXbbb
b a24 a23 azz a24yu1 The calculation result to be obtained is a34a33a22a31a3゜a2゜al.

ao. It is said that

A detailed example of such a multiplication processing procedure is shown in FIG. 3, and the addition operation will be described below without also referring to FIG.

The shared register 19 is initially set to all 4 bits of 0, and first the multipliers c and Q2Q stored in the shared register 18 are
1c is set in the dedicated register 29 from the internal bus BUS2 through the barrel shifter 16 in a non-operating state.

In the next cycle, the initialized data oooo of the shared register 19 is transferred to the internal bus Bus 1.

And the multiplicands stored in the shared register 20, b
zbxbo is output to internal bus BUS2.

As a result, the barrel shifter 16 takes in the data oooo from the internal bus BUS1, and also takes in the multipliers c and c2cic0 from the dedicated register 29, and shifts it by 1 bit to the lower side, and the overflowed least significant bit c0 is set as the overflow bit OFB by the selector 23. given to. On the other hand, the arithmetic and logic unit 15 uses the internal bus BUS.
In addition to importing data 0000 from 1, the selector 23
Data ooo is sent from the selector 23 according to the level of bit C0 as overflow bit OFB given to
o or the multiplicands s, b, b□b0 are given, so that the arithmetic and logic unit 15 substantially performs C6xb, b2b,
By adding the value of b and data 0000, the calculation result a
Obtain 03a02ao engineering a0°. At this time, the barrel shifter 16 performs a process of returning the lower 4 bits Oc, c2c1 obtained by the shift operation at that time to the dedicated register 29 in parallel with the addition operation. The addition result a03a02a01ao obtained by the arithmetic logic unit 15. is stored in the shared register 19.

Then, in the next cycle, data a of the shared register 19
offa02alllaoo is stored on the internal bus BUSI and the multiplicand stored in the shared register 20, b,
blbo is output to internal bus BUS2.

As a result, the barrel shifter 16 takes in the data a o3 a o2 a l, z a 0° from the internal bus BUS1, and also takes in the data OcmC, C from the dedicated register 29.
, is taken in and shifted by one bit to the lower order side, and the overflowed least significant bit c1 is given to the selector 23 as the overflow bit OFB.

On the other hand, shifter 17 transfers data from internal bus BUS1 to data a0.
3 C02aax a,. Data a is taken in and shifted one bit to the lower side, and the most significant bit is taken in the carry CAR output from the arithmetic and logic unit 15 in the previous cycle. 4a03a02a01 is given to the arithmetic and logic unit 15. The arithmetic logic unit 15 receives the data a. 4a0
3a02aOL is taken in, and data 0000 or multiplicand b2bib is given from the selector 23 according to the level of the bit C as the overflow bit OFB given to the selector 23, so that the arithmetic and logic unit 15 substantially , Xb, the values of b2b1b0 and data a04a.

Perform addition with 3aOZall and get the calculation result aL3a11
ayo1a□. get. At this time, the barrel shifter 16
The lower 4 bits a obtained by the shift operation at that time in parallel with the addition operation. The addition result a processing 1azza□, al, obtained by the arithmetic and logic unit 15, which performs the process of returning oc3c2 to the dedicated register 29, is stored in the shared register 19.
is stored in

In the subsequent next cycle, the data in the shared register 19 is alffalZaliaL. is on internal bus BUS 1,
And the multiplicands stored in the shared register 2o, b
2b□b, is output to the internal bus BUS2.

As a result, the barrel shifter 16 transfers the data a1. a engineering aai1a engineering. At the same time, the data a0°Oc, C2 is taken in from the dedicated register 29, and shifted by 1 bit to the lower order side, and the overflowed least significant bit c2 is given to the selector 23 as the overflow bit OFB.

On the other hand, the shifter 17 transfers data from the internal bus BUSI to
A-work 2A-work tax. is taken in and shifted one bit to the lower side, and the uppermost bit is assigned to the arithmetic logic unit 1 in the previous cycle.
Data a1 that captures the carry CAR output from 5
4a□, a□zaz□ are given to the arithmetic and logic unit 15.

The arithmetic logic unit 15 processes the data a14ai3a
At the same time, data 0OoO or multiplicand b is fetched from the selector 23 according to the level of bit c2 as the overflow bit OFB given to the selector 23.
3b2b1b is given, and thereby the arithmetic and logic unit 15 substantially adds the values of c2Xb, b, bibo and the data a 14 a 13a za za □ to obtain the operation result a23a22a21ago. At this time, the barrel shifter 16 outputs the lower 4 bits a1゜ao obtained by the current shift operation in parallel with the addition operation. Oc3
A process is performed to return the data to the dedicated register 29 again. The addition result a23a2 obtained by the arithmetic and logic unit 15! a21am.

is stored in the shared register 19.

Furthermore, in the next cycle, data a of the shared register 19
Z3 azz C21a. is stored on the internal bus BUSI and the multiplicand b3b2 is stored in the shared register 20.
b is output to the internal bus BUS2.

As a result, the barrel shifter 16 takes in the data a23aZ□a2□a2° from the internal bus BUS1 and also takes in the data a2 from the dedicated register 29. ao. Oc, is taken in, shifted one bit to the lower order side, and the overflowed least significant bit C1 is given to the selector 23 as the overflow bit OFB.

On the other hand, the shifter 17 receives data az from the internal bus BUS1.
Take in +az2az□a2゜ and shift it to the lower side by 1 bit, and the uppermost bit is set to arithmetic logic unit 1 in the previous cycle.
Data a2 that captures the carry CAR output from 5
4aZ3aZ2aZL is given to the arithmetic and logic unit 15.

The arithmetic logic unit 15 calculates the data a24a23aZ□
azt is taken in, and data 00oO or the multiplicand b2b is sent from the selector 23 according to the level of bit c3 as the overflow bit OFB given to the selector 23. As a result, the arithmetic and logic unit 15 substantially adds the value of c3Xb, b, b, b and the data aZ4a23a2xaz□ to obtain the operation result a33 C32aaz C3°. At this time, the barrel shifter 16 outputs the lower 4 bits a2°al obtained by the current shift operation in parallel with the addition operation. Processing is performed to return a and oO to the dedicated register 29 again. The addition result a33a3□a3□a, obtained by the arithmetic and logic unit 15. is stored in the shared register 19.

Then, in the last cycle, the data a33 C32C3z C3G of the shared register 19 is transferred to the internal bus BUS 1, and the multiplicand stored in the shared register 20 is transferred to the internal bus BUS 1.
b2b1bo is output to internal bus BUS2.

As a result, the barrel shifter 16 takes in data a33 a32 a3L a3° from the internal bus BUS1, and data aZ11aillao from the dedicated register 29.

0 is taken in and shifted one bit to the lower side, and the overflowed least significant bit O is given to the selector 23 as the overflow bit FB.

On the other hand, the shifter 17 receives data "j3" from the internal bus BUSI.
a32a3□a,. is taken in and shifted by 1 bit to the lower side, and the uppermost bit is transferred to the arithmetic logic unit 15 in the previous cycle.
Data a34 that captures the carry CAR output from
a33a32a3□ is given to the arithmetic and logic unit 15. The arithmetic logic unit 15 calculates the data a34a33a3□a
3□, data 0000 is given from the selector 23 according to bit 0 as the overflow bit OFB given to the selector 23, and thereby the arithmetic and logic unit 15 reads oooo and data a34a33.
Perform addition with a311a31 and get the calculation result a34a33
Obtain a32a31.

At this time, the barrel shifter 16 transfers the lower 4 bits a30a obtained by the current shift operation in parallel with the addition operation.
20a engineering. ao. A process is performed to return the data to the dedicated register 29 again. Addition result a34a obtained by arithmetic logic unit 15
33a32a3□ is stored in the shared register 19.

Through such arithmetic cycles, the stored data a34a33a32a31 of the shared register 19 and the dedicated register 29
Stored data a, . By a20aLOa11°.

Multiplicand b 3 b z b 1b a and multiplier C3QzQ
Data a34 a33 a3 which is the result of calculation with lc.
2 aax a30 a2゜a engineering.

ao. is obtained.

According to the above embodiment, the following effects are obtained.

(1) The addition operation by the arithmetic and logic unit 15 and the shift operation by the barrel shifter 16 are generally performed in parallel, and when the addition result by the arithmetic and logic unit 15 is stored in the shared register 19, the result obtained by the shift operation of the barrel shifter is The result is stored in the dedicated register 29 without going through the internal bus BUS3. Therefore, the number of cycles required to multiply the multiplicands b, b□b, and the multiplier c3c2cmco is 6 cycles even including the cycle for first setting the 5 multiplier C1C2ClCo in the dedicated register 29; In the conventional configuration without the register 29, the shift operation by the barrel shifter 16 and the addition operation by the arithmetic and logic unit 15 must be performed in different cycles.
Eight cycles are required because the results of the add operation and the result of the shift operation are stored in the predetermined registers because their data may conflict or be disrupted on the internal bus. Therefore, when performing multiplication or the like in the execution section of this embodiment, it is possible to improve the arithmetic processing capacity or the arithmetic processing speed.

(2) In calculations using the barrel shifter 16 and arithmetic logic unit 15, data to be calculated is transferred to internal buses BUSI, B
It is now possible to select between a data flow in which data is obtained from US2 and returned to the internal bus BUS3, and a data flow in which data to be operated on is obtained from a dedicated register and the result of the operation is returned to the dedicated register.For example, arithmetic logic The arithmetic unit 15 transfers the data to be calculated to the internal buses BUSI and BUS.
If the data in the dedicated registers 28 and 29 is used when performing calculations obtained from 2, the shift calculation by the barrel shifter 16 and the operation of storing the result of the calculation can be performed by the arithmetic and logic operation by the arithmetic and logic unit 15 and its operation. This can be done in parallel to the operation of storing the calculation result. Conversely, the barrel shifter 16 transfers the operation target data to the internal buses BUSI and BUS.
When performing a shift operation obtained from 25.2, the dedicated register 25.
By using the data of 26, the arithmetic and logic operations by the arithmetic and logic unit 15 and the operation of storing the operation results can be performed in parallel with the shift operation and the operation of storing the operation results by the barrel shifter 16. can. Therefore, in addition to multiplication, the arithmetic logic unit 15 and the barrel shifter 1
It is possible to improve the efficiency of various calculations using 6 and 6.

(3) The above effects can also contribute to reducing the number of steps in a microprogram for arithmetic processing using a plurality of arithmetic units, such as multiplication.

(4) Since the use of the dedicated registers 25, 26, 28, and 29 can be selected, versatility for various calculations is also high.

Although the invention made by the present inventor has been specifically described above based on examples, the present invention is not limited to the above-mentioned examples and can be modified in various ways without departing from the gist thereof.

For example, the arithmetic unit is not limited to one arithmetic and logic unit and one barrel shifter, but can be changed to a plurality of appropriate arithmetic units, and for example, the number of arithmetic and logic units can be increased. In particular, in the present invention, which allows multiple arithmetic units to operate in parallel, if the number of arithmetic units increases, the number of arithmetic units that can operate in parallel can also increase accordingly. The degree can also be increased.

Further, in the above embodiment, the operation was explained using multiplication as an example, but the type of operation that enables parallel operation of a plurality of arithmetic units is not limited to this, and can be applied to other operations as well. For example, when including multiple arithmetic and logic units,
It can also be used in cases where one arithmetic and logic unit is used for addition processing and the other arithmetic units are used as counters to perform required operations. Even in such calculation processing, the calculation processing speed is approximately twice that of the conventional method. Note that the procedure for the multiplication operation is not limited to the procedure shown in FIG.

In the above explanation, the invention made by the present inventor was mainly applied to a microprogram control type processor, which is the field of application that formed the background of the invention, but the present invention is not limited thereto, The present invention can be widely applied to peripheral controllers having the following functions, as well as various central processing units for office computers, engineering workstations, etc. The present invention can be applied to systems that are equipped with at least a plurality of arithmetic units and perform data processing.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, by including an arithmetic unit configured so that data can be supplied again from a dedicated register that stores the arithmetic result without passing it through the shared bus, even if multiple arithmetic units perform parallel operations in the same arithmetic cycle, the shared bus By preventing data conflicts for parallel operations, it is possible to supply operation target data and store operation result data. Parallel operation has the effect of speeding up a series of arithmetic operations using a plurality of arithmetic units. In particular, when the data processing device is microprogram controlled, it can contribute to reducing the number of microprogram steps for calculations.

By making it possible to selectively supply the output data of the dedicated data register or the data given from the shared bus to the arithmetic unit via the selector, the arithmetic unit can be used for general purposes.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of an execution section included in a processor that is an embodiment of the present invention, and FIG. A circuit diagram showing an example; FIG. 3 is an explanatory diagram showing an example of a multiplication processing procedure that can be executed by the processor of this embodiment; FIG. 4 schematically shows the entire processor that is an embodiment of the present invention. It is a block diagram. DESCRIPTION OF SYMBOLS 1... Processor, 3... Execution unit, 4... Micro ROM, 15... Arithmetic logic unit, 16... Barrel shifter, 17... Shifter, 18, 19.20...
Shared register, 21, 22, 23.24... Selector, 25°26... Dedicated register, 28.29... Dedicated register, BUSI, BUS2. BUS3...internal bus, OFB...overflow bit, φmtp.
...Multiplication specification control signal. Q3i1 G35 Q:j2031Figure 3Figure 4

Claims (1)

[Claims] 1. An execution means for executing an instruction, the execution means includes a plurality of arithmetic units coupled to a shared bus, and the arithmetic units send their operation results through the shared bus. A data processing device that can be supplied with data again from a dedicated register that stores data without any interruption. 2. The dedicated data register of the above-mentioned arithmetic unit is provided for each shared bus connected to the input terminal of the arithmetic unit, and the input terminal of the arithmetic unit is coupled to the internal bus and the output terminal of the dedicated register via a selector. The data processing device according to claim 1. 3. The data processing apparatus according to claim 2, further comprising control storage means for storing instructions to be executed, and operations by said execution means are controlled in accordance with microinstructions read out sequentially from said control storage means.