JPH0266034U - - Google Patents

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Publication number
JPH0266034U
JPH0266034U JP14538288U JP14538288U JPH0266034U JP H0266034 U JPH0266034 U JP H0266034U JP 14538288 U JP14538288 U JP 14538288U JP 14538288 U JP14538288 U JP 14538288U JP H0266034 U JPH0266034 U JP H0266034U
Authority
JP
Japan
Prior art keywords
input
switching
converter
input terminals
digital signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14538288U
Other languages
Japanese (ja)
Other versions
JPH073698Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988145382U priority Critical patent/JPH073698Y2/en
Publication of JPH0266034U publication Critical patent/JPH0266034U/ja
Application granted granted Critical
Publication of JPH073698Y2 publication Critical patent/JPH073698Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例におけるＡ／Ｄ変換
装置の回路ブロツク図、第２図は第１図に示した
テーブルの詳細を示す概念図、第３図は第１図に
示したＡ／Ｄ変換装置を端末ユニツトの主要部と
したシステムのブロツク図、第４図は従来のＡ／
Ｄ変換装置を用いて構成したシステムのブロツク
図、第５図は第４図に示したシステムにおけるセ
ンタユニツトと端末ユニツトとの間のデータ送受
信を説明するための説明図である。 １……ＣＰＵ、１Ａ……Ａ／Ｄコンバータ、１
Ｂ……テーブル、２……増幅回路、４……Ｄｉｇ
スイツチ、３００〜３１５……アナログスイツチ
、Ａｉ０〜Ａｉ１５……アナログ信号入力ポート
、Ｐｏ０〜Ｐｏ１５……制御信号出力ポート、Ｐ
ｉ０〜Ｐｉ３……制御信号入力ポート、ＡＩ０〜
ＡＩ１５……アナログ入力端子。 FIG. 1 is a circuit block diagram of an A/D converter according to an embodiment of the present invention, FIG. 2 is a conceptual diagram showing details of the table shown in FIG. 1, and FIG. Figure 4 is a block diagram of a system in which the A/D converter is the main part of the terminal unit.
FIG. 5 is a block diagram of a system configured using a D converter, and is an explanatory diagram for explaining data transmission and reception between the center unit and terminal units in the system shown in FIG. 4. 1...CPU, 1A...A/D converter, 1
B...Table, 2...Amplification circuit, 4...Dig
Switch, 300-315...Analog switch, Ai0-Ai15...Analog signal input port, Po0-Po15...Control signal output port, P
i0~Pi3...Control signal input port, AI0~
AI15...Analog input terminal.

Claims (1)

【実用新案登録請求の範囲】 アナログ信号を取込むための複数の入力端子と
、 該複数の入力端子に入力するアナログ信号を切
換えることによつて順次取込む入力切換手段と、 該入力切換手段の切換えによつて取込まれたア
ナログ信号をデイジタル信号に変換するＡ／Ｄコ
ンバータと、 前記複数の入力端子のうち、前記入力切換手段
の切換えによつてアナログ信号を取込むことがで
きる入力端子の数を設定する入力量設定手段と、 該入力量設定手段によつて設定された数に応じ
て前記Ａ／Ｄコンバータで変換されたデイジタル
信号にアドレスを割付けるアドレス割付け手段と
を具えたことを特徴とするＡ／Ｄ変換装置。[Claims for Utility Model Registration] A plurality of input terminals for inputting analog signals, an input switching means for sequentially inputting analog signals by switching the input terminals, and the input switching means. an A/D converter that converts an analog signal taken in by switching into a digital signal; and an input terminal that can take in an analog signal by switching the input switching means among the plurality of input terminals. an input amount setting means for setting a number; and an address assignment means for assigning an address to the digital signal converted by the A/D converter according to the number set by the input amount setting means. Characteristic A/D conversion device.
JP1988145382U 1988-11-09 1988-11-09 A / D converter Expired - Lifetime JPH073698Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988145382U JPH073698Y2 (en) 1988-11-09 1988-11-09 A / D converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988145382U JPH073698Y2 (en) 1988-11-09 1988-11-09 A / D converter

Publications (2)

Publication Number Publication Date
JPH0266034U true JPH0266034U (en) 1990-05-18
JPH073698Y2 JPH073698Y2 (en) 1995-01-30

Family

ID=31413921

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988145382U Expired - Lifetime JPH073698Y2 (en) 1988-11-09 1988-11-09 A / D converter

Country Status (1)

Country Link
JP (1) JPH073698Y2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5970247U (en) * 1982-11-02 1984-05-12 日立電子エンジニアリング株式会社 Time division selection processing device for multiple analog inputs
JPS60237527A (en) * 1984-05-11 1985-11-26 Mitsubishi Electric Corp A-d converting device
JPS6121524A (en) * 1984-07-10 1986-01-30 Mitsubishi Heavy Ind Ltd High speed data collecting system
JPS6156517A (en) * 1984-08-28 1986-03-22 Toshiba Corp Analog-to-digital converter

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5970247U (en) * 1982-11-02 1984-05-12 日立電子エンジニアリング株式会社 Time division selection processing device for multiple analog inputs
JPS60237527A (en) * 1984-05-11 1985-11-26 Mitsubishi Electric Corp A-d converting device
JPS6121524A (en) * 1984-07-10 1986-01-30 Mitsubishi Heavy Ind Ltd High speed data collecting system
JPS6156517A (en) * 1984-08-28 1986-03-22 Toshiba Corp Analog-to-digital converter

Also Published As

Publication number Publication date
JPH073698Y2 (en) 1995-01-30

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