JPH0265528A - Sem modulation system - Google Patents

Abstract

PURPOSE:To cancel the DC component of a conversion data and to generate a high efficient code satisfying the RLLC rule by applying code conversion according to main and sub conversion tables so that a DSV integration value revised at each conversion is converged to zero in the system where a 7-bit data is code-converted into an 8-bit data. CONSTITUTION:A master conversion table stored in a conversion ROM 13 converts a 7-bit data into a balanced code with a null DSV or an unbalanced code with a positive DSV and a sub conversion table converts a 7-bit data into a balanced code or an unbalanced code with a negative DSV. The 7-bit data being a conversion object is fed to the conversion RDM 13 via a D flip-flop circuit 12, converted into a 13-bit data according to either of the master and sub conversion tables and a low-order 8-bit and a high-order 5-bit are supplied to a D flip-flop circuit 14 and a DSV integration circuit 15. The sub conversion table is selected when the DSV integration value is zero or positive by the DSV integration circuit 15 and the master conversion table when the DSV integration value is negative and the code conversion is applied in a direction where the DSV integration value is converged to zero.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is an SE system suitable for digital processing of video and audio.
Regarding M modulation method.

[Prior Art J] The benefits of digitizing video signals are significant, and have gone beyond just improving image quality to the point where it has become possible to perform complex image processing associated with computer graphics.

On the other hand, from the perspective of recording video signals, digital recording with almost no signal deterioration is attracting attention, and the wave of digitization is also spreading to home video tape recorders.

In general, these digital recording video tape recorders, not only for home use but also for business use, record video data by methods such as reducing the data length through code compression or switching the compression mode according to the movement of the image. A method of compressing the band is used. Normally, an l-field image is decomposed into multiple blocks, and each block is divided into a matrix and each of the multiple pixels obtained is sampled with the number of matrix bits depending on the specified mode. It is.

In this type of video data processing method, as illustrated in Fig. 6, a block obtained by dividing an l-field image into 2550 parts is further divided into 64 sample pixels in a matrix, and the video data for each pixel is divided into 2550 blocks. A method is used in which the data is sampled with a number of quantization bits of 2, 4, or 5 depending on the specified mode. Since the sampled video data is compressed using an adaptive code compression method, the 0th sample pixel is quantized with 7 bits regardless of the mode, and
For sample pixels, 5 bits in E mode, If
quantization bits of 4 bits are used in the and 12 modes, and 2 bits are used in the CI, 02, and F modes. For this reason,
(2) The video data of the block is converted into signal bits of 322 bits, 259 bits, and 133 bits, each of which is a multiple of 7 bits, depending on the mode.

By the way, the rotating transformer used for transmitting and receiving signals between the rotating magnetic head of a VTR and the outside has a DC blocking characteristic, so when recording video signals digitally, it is necessary to suppress the DC component contained in the video data. It is desirable to average the bit inversion intervals, and for this reason, conventionally, ENM modulation or the like has been used to convert video data symbolized in units of 8 bits into 9-bit data, for example.

The 8/9 encoder l shown in Fig. 7 converts 8-bit video data into 9-bit data using the conversion ROM 2J that stores a conversion table, and integrates the DSV indicating the DC balance of the 9-bit data. When I went to
Two main and sub conversion tables are prepared so that the DSV integrated value converges to zero, and one of the main and sub conversion tables is selected in response to a command from the table selection circuit 3 that integrates the DSV. . In addition, DSV takes the high level of the signal waveform of 9-bit data as +■ point, the low level as 1 point,
It represents the total number of points accumulated as the 9-bit data progresses, and it can be said that the smaller the absolute value of the DSV, the fewer the direct current components and low frequency components of the 9-bit data, which is converted data, and the more the above-mentioned recording conditions are met.

[Problems to be Solved by the Invention] The conventional 8/9 encoder 1 requires only one redundant bit at the minimum due to code conversion, and furthermore, when the bit interval is T, the minimum code inversion interval T sin is Although it can be extended up to 0.89T, the maximum sign inversion interval T l1ax is quite large at 20T, so there are issues such as the recording frequency band becoming wider, and the recording frequency band is extended to 7 bits! When using a video data processing method that allows data within a block to be symbolized without fractions, there is a problem in that the symbolization itself in 8-bit units, which produces fractions, is incompatible. Also, in contrast to the 8/9 encoder 1 with 1 redundant bit, the 8/! encoder 1 has 2 redundant bits. 0 encoder (not shown) also has a minimum code inversion interval T sin of 0
．． Since it is relatively small such as 8T, the maximum recording frequency inevitably becomes high, and the resolution of the recording system must be increased, which poses problems such as being unsuitable for high-density recording.

[Means for Solving the Problems] This invention solves the above problems, and is an SEM modulation method for code-converting 7-bit data into 8-bit data, in which 8-bit data obtained by code conversion is
A main conversion table that converts 7-bit data into a balanced code or an unbalanced code with a positive DSV by dividing data into a balanced code with a zero DSV indicating DC balance and an unbalanced code with a non-zero DSV, and a main conversion table for converting 7-bit data into a balanced code or an unbalanced code with a positive DSV. Prepare a sub-conversion table that converts DSV into a balanced code or an unbalanced code with negative DSV, so that the DSV integrated value updated every time the conversion converges to zero.
This system is characterized in that code conversion is executed according to either a main or sub-conversion table.

[Function] This invention converts 8-bit data obtained by SEM modulation of 7-bit data into D.
A main conversion table that divides 7-bit data into a balanced code or an unbalanced code with a positive DSV, and a main conversion table that converts 7-bit data into a balanced code or an unbalanced code with a negative DSV. DSV integrated value This cancels the DC component of the converted data while keeping it within a certain limit, making it possible to generate a high-efficiency code that satisfies the RL L 0 law.

[Embodiments] Examples of the present invention will be described below with reference to FIGS. 1 to 5. FIG. 1 is a circuit diagram showing an embodiment of a 7/8 encoder to which the SEM modulation method of the present invention is applied, and FIGS. 2 to 5 show the circuit configuration of the 7/8 encoder shown in FIG. It is a figure which shows the conversion table of a main sub pair used for code conversion.

In FIG. 1, a 7/8 encoder 11 converts 7-bit data into 8-bit data (5 even eight bits data).
This method performs code conversion so that the DSV integrated value of the converted data converges to zero while using a pair of main/sub conversion tables prepared in advance. The main/sub conversion table is 7-bit data! 1 from (00)H to (7F)H in hexadecimal representation
The main conversion table converts 7-bit data into a balanced code with zero DSV or an unbalanced code with positive DSV, and the sub-conversion table converts 7-bit data into a balanced code with a positive DSV. In the embodiment in which data is converted to a balanced code or an unbalanced code with a negative DSV, the main conversion table consists of 70 data from (00)H to (45)H, as shown in FIGS. 2 to 5. 8-bit data with a DSV of 0 is made to correspond to 7-bit data, and 8-bit data with a DSV of +2 is made to correspond to 56 7-bit data from (46)H to (7D)H. The remaining (7E)H and (7P) n l
: Corresponds to 8-bit data with a DSV of +4. In addition, the sub-conversion table H, (OO) H~(45)
o (070 7-bit data correspond to exactly the same 8-bit data used in the main conversion table, and further 56 7-bit data from (46)H to (7D)u, DSV corresponds to 8-bit data of -2, and DSV is - for the remaining (7E)H and (7F)u.
This corresponds to 4 8-bit data.

Note that DSv of S-bit data obtained by conversion is
It is expressed as a 2's complement number, and the second digit of the 8-bit data is combined as 5-bit data and stored in each table.

Here, the 7-bit data to be converted is first sent to the conversion ROM 13 via the first-stage D flip-flop circuit 12. After being converted into 13-bit data according to either the main or sub conversion table stored in the conversion ROM 13, the lower 8 bits and upper 5 bits are transferred to the D flip-flop circuit 14 and DS for external output, respectively.
It is supplied to the V integration circuit 15. The DSV integration circuit 15 is
The previous DSV is output to the upper 5 bits of the conversion ROM13.
Adding circuit 16 that updates the DSV integrated value by adding
and a D-flip flop circuit 17 that latches the output of this adder circuit 16.
The output of the frib 70 tube circuit I7 is used as the addendum input of the adder circuit 16.

The most significant bit of the output of the D flip-flop circuit 17 is D
It represents the positive or negative of the SV integrated value, and therefore f) When the SV integrated value is negative or positive, selection of the 11 conversion table is executed with the low level latch output of the D flip-flop circuit 17. Also, when the DSV integrated value is negative, D
The main conversion table is selected when the flip-flop circuit 17 outputs a high level.

Now, if the DSV integrated value is 00010, that is +
2, 1011311 as 7-bit data
Suppose that you have been sent. In this case, the output of the D flip-flop circuit 17 is at a low level, and code conversion is performed according to the sub-conversion table, so data 1111001100001 corresponding to address (5F) o is output. Note that the upper 5 bits of the output data + 1110 are 8
It represents DSV-2 with bit data 01100001, which is DSV8! The previous DS in the fj circuit 15
As a result of being added to the V integrated value +2, the DSV integrated value is returned by 01.

In this way, the 7-bit data sent one after another is sent to the DS
The code is converted in the direction of converging the V integrated value to zero, but for the bit interval T of 7-bit data, 8
Bit interval of bit data, that is, minimum sign inversion interval T
lll1n is expressed as 7/8·T (ξ0.875T). And the maximum sign inversion interval T, which is said to be better as it is shorter
11ax, 8-bit data is 11000000,0
By assuming the worst case of 0000111, the period during which 11 “0°” persists, that is, 1ITai
n (=9.625T).

In this way, the 7/8 encoder II is configured so that the sub-conversion table is selected when the DSV integrated value is 0, so that the maximum limit of the DC component of the conversion data can be suppressed to -4 to +2. Can be done. Furthermore, since the maximum sign inversion interval occurs when two beats of the same type are consecutive, it can be suppressed to 77/8 times the bit interval T, thereby making it possible to suppress the highest recording frequency.

Furthermore, the 8/9 encoder II reads out 8-bit data from a pair of conversion tables on the main side stored in the conversion ROM 13 having 128 addresses in accordance with the DSV integrated value of the DSV integration circuit 15, thereby achieving minimum code inversion. Interval Tmi
n is 0.875T, maximum sign inversion interval T 1ax is 9.
625T, RL L C with detection window width Tw of 0.875T
(Run Length Lis+1tedCode)
Since 8-bit data that satisfies the rules can be obtained, small-scale RO
It is possible to simplify the configuration of the entire circuit by making use of the characteristics of PI and A, and in particular, it is possible to simplify the configuration of the entire circuit.
For video data subjected to band compression processing by PCM), it is suitable for processing in units of 7-bit data,
Furthermore, since the 7-bit differential data that appears frequently is converted to 8-bit data with a DSV of zero, the DC component in the common range can be suppressed as much as possible.

[Effect of the invention] As explained above, the present invention allows 7-bit data to be
The 8-bit data obtained by EMR adjustment is divided into a balanced code with a DSV of zero, which indicates the DC balance of each data, and an unbalanced code with a non-zero DSV, and the 7-bit data is divided into a balanced code or an unbalanced code with a positive DSV. A main conversion table for converting 7-bit data into a balanced code or a sub-conversion table for converting 7-bit data into an unbalanced code with a negative DSV is prepared. Since the code conversion is executed according to any suitable conversion table, the maximum limit of the DC component of the converted data can be suppressed within ±4, and the maximum code inversion interval is as follows.
This occurs when 11 bits of the same type are consecutive.
It is possible to suppress the bit interval to 77/8 times, which makes it possible to suppress the highest recording frequency.In addition, a pair of main and sub conversion tables are stored in a conversion ROM with 128 addresses, and DSV integration is carried out in this ROM. By adding a circuit,
Since 8-bit data that satisfies the RLLC rule can be obtained, it is possible to create a PLA that takes advantage of the characteristics of a small-sized ROM and to simplify the overall circuit configuration. There is a method that is suitable for processing data in the m order, and by converting frequently occurring 7-bit differential data to 8-bit data with zero DSV, the DC component of the converted data in the common range can be reduced as much as possible. It has excellent effects such as being able to suppress the

[Brief explanation of the drawing]

FIG. 1 shows application 1 of the SEM modulation method of the present invention. . FIGS. 2 to 5 are circuit configuration diagrams showing one embodiment of a 7/8 encoder, and FIGS. 2 to 5 are diagrams showing a pair of main/sub conversion tables used for code conversion of the 7/8 encoder shown in FIG. , Figure 6 is
FIG. 7 is a diagram showing the pixel arrangement of video data.
FIG. 2 is a circuit configuration diagram showing an example of a /9 encoder. +1. ,．． 7/8 encoder, +3. ．． ．． Conversion ROM, 15
．． ,,DSVI arithmetic circuit.

Claims (1)

[Claims] SEM that converts 7-bit data to 8-bit data
It is a modulation method that divides 8-bit data obtained by code conversion into a balanced code with zero DSV, which indicates the DC balance of each data, and an unbalanced code with non-zero DSV, and converts 7-bit data into balanced code or DSV. Main conversion table for converting to positive unbalanced code and converting 7-bit data to balanced code or D
A sub-conversion table for converting SV to a negative unbalanced code is prepared, and code conversion is performed according to an appropriate conversion table, either main or sub-table, so that the DSV integrated value updated each time converges to zero. Characteristic SEM modulation method.