JPH0265392A - Video signal reproducing device - Google Patents

Abstract

PURPOSE:To attain the noise suppression of less after-image generation, etc., by providing an arithmetic circuit to suppress the noise, which is included in a signal based on difference with a signal almost before one field, independently to a luminance signal and a carrier chrominance signal concerning a signal which is separated to the luminance signal and carrier chrominance signal. CONSTITUTION:Data selectors 14 and 21 and switches 27 and 28 are connected to an N-side in a figure. Then, the output of an arithmetic circuit 9 is induced through the data selector 14 to an adder circuit 15 and the output of an arithmetic circuit 17 is induced through a chrominance modulating circuit 22 and the data selector 21 to the adder circuit 15 respectively. Thus, a video signal, for which a noise component is suppressed, is obtained. In a subtracting circuit 10a, the noise component extracted in a coefficient circuit 11 is subtracted from the luminance signal, which is separated in a Y/C separating circuit 8, and the output of the subtracting circuit 10a, namely, the output of the arithmetic circuit 9 obtains the luminance signal, for which the noise component is suppressed. On the other hand, the suppression of the noise component is executed in the arithmetic circuit 17 wholly samely as the luminance signal concerning the chrominance signal. However, concerning the chrominance signal, the carrier chrominance signal separated in the Y/C separating circuit 8 is converted to two color difference signals, for which time-division multiplexing is executed, in a chrominance demodulating circuit 16.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention reproduces a color video signal (hereinafter also simply referred to as a video signal) recorded on a video disk or the like, and particularly The present invention relates to a video signal reproducing device equipped with suitable means for suppressing and outputting noise components contained in a video signal.

[Conventional technology]

As a device for suppressing noise components contained in a reproduced video signal, for example, as described in Japanese Patent Application Laid-open No. 57-55671, there is a device that uses correlation between fields of a video signal, or a device that uses correlation between frames. Some methods using correlation are known.

FIG. 16 shows the configuration of such a device.

The input video signal is sent to the subtraction circuit 31a in the arithmetic circuit 30.
and joins 31b. On the other input side of the subtraction circuit 31b, a color image signal phase adjustment circuit 33 is read out from an image memory 34 such as a field memory or a frame memory.
The subtraction circuit 31b outputs an inter-field or inter-frame difference signal. Subtraction circuit 3
The difference signal outputted from 1b passes through the coefficient circuit 32 and is input to the other input side of the subtraction circuit 31a.

The input/output characteristics of the coefficient circuit 32 have non-linear characteristics such that the coefficient value is large when the input signal level is low and the coefficient value is small when the input signal level is high. Extract noise components contained in a video signal. The subtraction circuit 31a subtracts noise components from the input video signal, and outputs the noise-suppressed video signal to the outside and to the image memory 3.
Supply to 4.

The color signal phase adjustment circuit 33 separates a luminance signal and a carrier color signal (hereinafter also simply referred to as a color signal) from the input video signal, inverts the phase of the carrier color signal by 180 degrees, and then converts the luminance signal again. As is well known, NT acts as an addition to
In an SC color video signal, the color subcarrier phase of the carrier color signal is inverted line by line and frame by frame. Therefore, a color signal phase 5I adjustment circuit 33 is provided in order to prevent the subcarrier phase of the carrier color signal from differing depending on the ldT of the signals subjected to subtraction in the subtraction circuit 30b. When the image memory 32 is a frame memory, the color signal phase adjustment circuit 33 inverts the phase of the color signal of the video signal that is constantly input and outputs it.

Furthermore, when the one-image memory 32 is a field memory and the video signal delay time is switched between 262 and 263 times the horizontal period (H) of LH (H is the horizontal scanning period) for each field, , the phase of the monochromatic signal is inverted when the delay time is 263H.

In the manner described above, noise components can be suppressed by using the field correlation or frame correlation of the input color video signal.

[Problem to be solved by the invention]

In the noise suppression device described above, how to select the input/output characteristics of the coefficient circuit 32 is important in terms of noise suppression characteristics. For example, if the input/output characteristics of the coefficient circuit 32 are determined solely with the aim of increasing the amount of noise suppression, side effects such as the afterimage that occurs when inputting a moving image become noticeable. On the other hand, if you try to minimize the occurrence of afterimages, you will not be able to obtain a sufficient amount of noise suppression.Therefore, when determining the input/output characteristics of the coefficient circuit 32, fine adjustments should be made so that the amount of noise suppression and afterimages are compatible. You need to make settings.

By the way, in a video signal reproduced from a medium such as a video disk, the noise level contained in the luminance signal and the noise level contained in the color signal differ due to the influence of PM noise in the color signal caused by jitter during reproduction. are not consistent. Furthermore, there is a difference in visual sensitivity to afterimages and the like between luminance signals and color signals. When trying to process such a video signal with the above-mentioned noise suppression device, for example, in order to obtain sufficient noise suppression for color signals, luminance afterimages are noticeable or monochromatic signals are highly saturated. Due to noise in the chrominance signal, the signal input to the coefficient circuit 32 reaches a large amplitude region, causing problems such as not being able to sufficiently suppress noise in the luminance signal. It was difficult to achieve a sufficient noise suppression effect against the noise.

An object of the present invention is to provide a video signal reproducing device having sufficient noise suppression characteristics even for inputs in which luminance signals and color signals have different noise levels. The noise suppression effect of the luminance signal does not change for images with high color saturation or images that are close to 100%, and even if sufficient noise suppression effect is provided for the brown signal, afterimages may occur when inputting a video. An object of the present invention is to provide a video signal reproducing device that has sufficiently few side effects such as those typified by.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a video signal reproducing device equipped with an image memory for considering a video signal, with means for separating a color video signal reproduced from a medium into a luminance signal and a carrier color signal. In addition, for each of the luminance signal and carrier color signal (or color difference signal demodulated from the carrier color signal) separated by one field, an arithmetic circuit is provided that suppresses noise contained in the signal based on the difference from the signal approximately one field before. , luminance signal and carrier color signal (or color difference signal)
These are provided separately and independently for each of them.

[For production]

A video signal reproduced from the medium is separated into a luminance signal and a carrier chrominance signal by a luminance/chrominance signal separation means. The separated luminance signal and the carrier color signal (or the color difference signal obtained by demodulating the carrier color signal) are input to respective dedicated arithmetic circuits. on the other hand.

The signals read from the image memory are also input to the luminance signal and color signal calculation circuits, respectively, and noise suppression processing is performed using the correlation between fields of each signal. The coefficient circuit that extracts noise components in each arithmetic circuit can independently determine the input/output characteristics according to the noise level contained in the separated luminance signal and carrier color signal (or color difference signal). .

In this way, the arithmetic circuit that suppresses noise in the luminance signal can provide characteristics most suited to the noise level of the luminance signal, and can also process color signals in the same way. As a result, it is possible to realize a video signal reproducing device equipped with a noise suppressing device that can exert a sufficient noise suppressing effect on both luminance signals and color signals, and has fewer side effects such as generation of afterimages.

〔Example〕

An embodiment of the present invention will be described below.

FIG. 1 shows the configuration of a video signal reproducing apparatus which is an embodiment of the present invention.

The video signal reproducing apparatus includes a disk 1 on which a video signal is recorded, a motor 2 for driving the disk 1, a head 3 for reading signals recorded on the disk 1, and an FM demodulator 4 for demodulating the output signal of the head 3 into a video signal. ．． A low-pass filter (hereinafter referred to as LPF) 5 that limits the band of the output of the FM demodulator 4, a time base collector (hereinafter referred to as TBC) 6 that removes time axis fluctuations of the video signal that is the output of the LPF 5, and a TBC 6. A converts the output into a digital signal
A Y/C separation circuit 8 that separates the digital video signal output from the D converter 7 and the AD converter 7 into a luminance signal component and a carrier color signal. The luminance signal separated by the Y/C separation circuit 8 and the output from the field memory 12, which will be described later, are input, and the output of the arithmetic circuit 9 and the arithmetic circuit 9 is made up of subtraction circuits 10a and 10b, a coefficient circuit 11, and a switch 27. Field memory 12. A synchronization addition circuit 13 for adding a synchronization signal to the output of the field memory 12. A data selector 14 for switching and selecting the output of the arithmetic circuit 9 and the output of the synchronization addition circuit 13. A color demodulation circuit 16 demodulates the carrier color signal separated by the Y/C separation circuit 8 into color difference signals such as R-Y and B-Y and time division multiplexes the output of the color demodulation circuit 16 and a field memory 20 to be described later. an arithmetic circuit 17 . which takes the output as an input and comprises subtraction circuits 18 a and 18 b , a coefficient circuit 19 , and a switch 28 . a field memory 20 that stores the output of the arithmetic circuit 17; a data selector 2J that switches between the output of the arithmetic circuit 17 and the output of the field memory 20;
A color modulation circuit 22 modulates the color difference signal output from the data selector 21 into a carrier color signal, and a video signal is generated by adding the luminance signal output from the data selector 14 and the carrier color signal output from the color modulation circuit 22. An adder circuit 15 that converts the output of the adder circuit 15 into an analog signal and outputs it.
Converter 23, a synchronization separation circuit 24 that separates a playback synchronization signal from the output video signal of the TBC 6, and a reference synchronization generation circuit 25 that generates a reference synchronization signal that serves as a memory read reference during special playback. Synchronization separation circuit 24 and reference synchronization generation circuit 2
The memory control circuit 26 receives the synchronization signal output from the field memory 5 and generates a control signal for controlling write addresses, subsequent addresses, etc. of the field memories 13 and 20.

In the configuration shown in FIG. 1, the data selectors 14 and 21 and the switches 27 and 28 are connected to the N side in the figure, and the output of the arithmetic circuit 9 is passed through the data selector 14 and
The output of the arithmetic circuit 17 is sent to the color modulation circuit 22. By guiding each signal to the adder circuit 15 via the data selector 21, a video signal with suppressed noise components can be obtained.

That is, +! ! To obtain the 11 degree signal, first, the subtraction circuit 10b calculates the difference between the luminance signal separated by the Y/C separation circuit 8 and the luminance signal read from the field memory 12 about one field period ago. The difference signal obtained by the subtraction circuit fob is applied to the coefficient circuit 11. Coefficient circuit 11
has non-linear input/output characteristics such that the coefficient value is large when the input signal level is low and the coefficient value is small when the input signal level is high.The noise component is extracted from the input difference signal, and the switch 27 to the subtraction circuit 10a. In the subtraction circuit 10a, the Y/C separation circuit 8
The noise component extracted by the coefficient circuit 11 is subtracted from the luminance signal separated by , thereby obtaining a luminance signal with suppressed noise components at the output of the subtraction circuit LOa, that is, the output of the arithmetic circuit 9.

On the other hand, the noise component of the color signal is also suppressed in the arithmetic circuit 17 in exactly the same manner as the luminance signal.However, for the color signal, the carrier color signal separated by the Y/C separation circuit 8 is Converts into two time-division multiplexed color difference signals.

FIG. 2 shows an operation timing chart of the color demodulation circuit 16.

In Fig. 2, (a) shows the waveform of the carrier color signal in the reproduced video signal, and the circle mark indicates A.
This is a sample point in the D converter 7. It is convenient to set the sampling frequency to four times the color subcarrier frequency fsc, as will be explained below. (b) is the data of the carrier color signal separated by the Y/C separation circuit 8, and by multiplying each data shown in (b) by s1mθj and eoliθL corresponding to the phase angle OL for each subcarrier, Two color difference signals RY and BY can be obtained.

Since the band of the color difference signal is sufficiently lower than that of the video signal, signal deterioration does not occur even if the sampling frequency is lowered to 1/2 of the original value and the number of samples is thinned out by half. (c) is data of a color difference signal whose sampling frequency has been lowered in this way. (d) is the data shown in (c) that is time-axis multiplexed alternately for each sample.

In the arithmetic circuit 17 and field memory 2o.

Time-division multiplexed color difference signals are handled in a time-division manner. In this way, the capacity of the field memory 20 can be reduced to half that of handling color difference signals separately. In addition.

In this example, as mentioned above, the sampling frequency is set to four times the color subcarrier frequency fsc, so in this case, the previous values of cosθi, sinθL are OLl
, -1, the circuit can be simple. However, the sampling frequency is not limited to 4fsc, and the color difference signal thinning rate is not limited to the aforementioned 1/2 (in the case of 4fsc, the rate is set according to the sampling frequency, such as 1/4, 1/8, etc.). You can set it to .

Further, the color modulation circuit 22 restores the carrier color signal from the color difference signal multiplexed in one time axis by an operation completely opposite to that of the color demodulation circuit 16.

FIG. 3 shows an example of a detailed configuration of the memory control circuit 26.

The reproduced synchronization signal output from the synchronization separation circuit 24 is input to a vertical synchronization detection circuit 40 and a horizontal synchronization detection circuit 4], and a vertical synchronization signal and a horizontal synchronization signal are output, respectively. After the vertical synchronization signal is latched by the horizontal synchronization signal in the latch 42, it is input to the edge detection circuit 43 and the divide-by-one circuit 47. The edge detection circuit 43 detects the rising or falling edge of the input vertical synchronizing signal and generates a write address for the field memories 13 and 20.
While supplying a reset signal to the delay circuit 45, an error reset signal is also supplied to the delay circuit 45. The delay circuit 45 delays the input reset signal by 262H and outputs it to the IH delay circuit 46 and switch 48.The switch 48 follows the output signal of the divide-by-one circuit 47 and delays the output of the delay circuit 45 by 1H for each field. The output of the circuit 46 is alternately switched, and via the switch 49,
A reset signal is supplied to a counter 50 that generates read addresses for field memories 13 and 20. The addresses generated by counters 44 and 50 are switched and selected by address selector 51 and input to field memories 13 and 20.

In this way, as the delay in the reset timing of the counter 50 with respect to the reset timing of the counter 44, the values of 262H and 263H are taken alternately for each field, so the delay time of the signal in the field memories 13 and 20 is delayed for each field. It operates to alternately repeat 262H and 263H.

Therefore, the arithmetic circuits 9 and 17 can perform noise suppression processing using correlation with a signal 262H or 263H ago, which is a signal approximately one field before. Moreover, since the input/output characteristics of each coefficient circuit 11 and 19 can be set independently according to the noise level of the luminance signal and the noise level of the color difference signal, sufficient A noise suppression effect can be obtained.

Note that in an actual circuit, there is a signal delay in the memory input/output buffer, etc., so the delay time in the delay circuit 45 is increased or decreased in consideration of this delay.

Next, the operation when performing special playback in the video signal playback apparatus shown in FIG. 1 will be described.

When performing special playback, data selectors 14 and 2
1 is selected so that the input on the T side in the figure is led to the output, and the switches 27 and 28 are turned to the T side to cut off the negative side inputs of the subtraction circuits 10a and 18a. Then, the synchronization addition circuit 13 adds the reference synchronization signal generated by the reference synchronization signal generation circuit 25 to the luminance signal read from the field memory 12, and the color difference signal read from the field memory 20 is modulated by the color modulation circuit 22. After adding the carrier color signal and the carrier color signal in an adding circuit 15, the signal is restored to an analog signal in a DA converter 23 and output.

Note that instead of using the switch 27 in the arithmetic circuit 9, a data selector 29 may be provided as shown in FIG. 4, and the signal output from the Y/C separation circuit 8 may be directly guided to the field memory 12 during special playback. good.

On the other hand, in the memory control circuit 26, the switch 49 shown in FIG. 3 is connected to the T-side input.

As a result, the method of generating the reset signal for the counter 44 that generates the write address is the same as in the normal playback operation described above, but the method of generating the reset signal for the counter 50 that generates the read address is as described below. become. That is, a vertical synchronization signal is detected from the reference synchronization signal by the vertical synchronization detection circuit 52, and a horizontal synchronization signal is detected from the same reference synchronization signal by the horizontal synchronization detection circuit 53, and the detected vertical synchronization signal is latched by the horizontal synchronization signal. 54, and an edge detection circuit 55 which operates in the same manner as the edge detection circuit 43 performs edge detection to obtain a reset signal for the counter 50.

As described above, the signals reproduced from the disc 1 are intermittently written into the field memories 12 and 20, and read out continuously in accordance with the reference synchronization signal, thereby recording in the CLV (Constant Slow Velocity) method. Even if the playback signal becomes discontinuous when a track jump is performed on a disc that has been
By changing the average moving speed of
Special playback such as slow, still, and fast forward can be realized.

Furthermore, since the phase of the carrier color signal in the output video signal is determined by the color modulation circuit 22, the phase of the output color carrier wave can always be kept continuous.

This is an advantage not available with conventional devices that record composite video signals in field memory or frame memory.

As described above, in this embodiment, the input/output characteristics of the coefficient circuits 11 and 19 can be determined independently for the luminance signal and color difference signal of the video signal reproduced from the disc 1, and a high noise suppression effect can be obtained. It will be done. Also, using the same field memory 12.20 used for noise suppression, CL
Special playback can be achieved even on V-discs, and the continuity of the output color signals and synchronization signals is not lost at this time.

What is shown in FIGS. 5 and 6 is a modification of the arithmetic circuit 9 in FIG. Further, FIG. 7 shows a memory control circuit 26 corresponding to the modified example of FIGS. 5 and 6.
This is an example of the configuration.

In the configuration of the arithmetic circuit 9 shown in FIG. 5, the signal read from the field memory 12 shown in FIG.
1, the signals are alternately switched for each field and input to the subtraction circuit 10b.

On the other hand, the memory control circuit 26 shown in FIG. 7 has an IH delay circuit 46 and a switch 48 from the configuration shown in FIG.
is omitted, and the write address always precedes the read address by 262H during normal playback when the noise suppression operation is performed. As a result, switch 6
The signal output from 1 is the signal output from the subtraction circuit 10a delayed by 262H alternately for each field, and 2.
It is delayed by 63H. Therefore, subsequent operations can be performed in exactly the same manner as the arithmetic circuit 9 shown in FIG.

Further, in the arithmetic circuit 9 shown in FIG. 6, the signal read from the field memory 12 shown in FIG.
A coefficient circuit 63 having a coefficient value of 1/2
After passing through, the signal is input to the subtraction circuit 10b. On the other hand, as described above, the memory control circuit 26 shown in FIG. 7 operates so that the write address always precedes the read address by 262H during normal playback.

As a result, the coefficient circuit 63 outputs the arithmetic average value of the signal output from the subtraction circuit 10a delayed by 262H and the signal delayed by 263H.

According to the configuration shown in FIG. 6, when correlating fields in the subtraction circuit 10b, it is possible to calculate the correlation with the average value of the signals on the scanning lines immediately above and immediately below the previous field.

Note that the configuration shown in FIG. 5 can be applied not only to the luminance signal calculation circuit 9 but also to the color difference signal calculation circuit 17. The same applies to the configuration shown in FIG.

Furthermore, applying the configuration shown in FIG. 5 to the luminance signal,
As for the color difference signals, it is possible to apply the configuration shown in FIG. 6, or vice versa.

In FIGS. 5 and 6, the switch 27 is used to switch between normal playback and special playback.
As shown in the figure, the subtraction circuit 10a may be bypassed.

Next, the configuration shown in FIG. 8 is a modification of the color signal processing section of the video signal reproducing apparatus shown in FIG.

In the configuration shown in FIG. 8, the process of demodulating the carrier color signal into a color difference signal is omitted, and the noise suppression process is performed on the carrier color signal as it is. The field memory 20 has the same configuration as shown in FIG.
The 0 phase detection circuit 70, which alternately repeats a 63H delay and a 263H delay, compares the burst phase of the carrier color signal output from the field memory 20 with the phase of the color subcarrier, which is the operating phase reference of the TBC 6, for example. Inversion circuit 7
1, the subcarrier phase of the carrier color signal output from the field memory 20 according to the output result of the phase detection circuit 70 is
When the subcarrier is in an anti-phase relationship with the reference subcarrier, the output of the field memory 20 is phase-inverted and output. In this way, the subcarrier phases of the carrier color signals reaching the two inputs of the subtraction circuit 18b become equal to each other, and a noise-suppressed carrier color signal is obtained at the output of the arithmetic circuit 17.

The output of the arithmetic circuit 17 passes through the data selector 21 connected to the N side in FIG. 8, and becomes a brightness signal with noise suppressed in the j11 degree brightness section (not shown).

The signals are added in an adder circuit 15 to obtain an output video signal.

On the other hand, when special reproduction is performed using the configuration shown in FIG. 8, the data selector 21 is connected to the T side.

Writing to the field memory 20 is performed in synchronization with the reproduced video signal, and reading is performed in synchronization with the reference synchronization signal.

As described above, with the configuration shown in FIG. 8 as well, noise can be suppressed by giving optimal coefficient circuit input/output characteristics to the luminance signal and color signal, respectively.

Noise suppression and special playback can be performed by sharing field memory. Moreover, the synchronization signal of the output video signal and the phase of the color subcarrier during special playback can be maintained continuously.

In the configuration shown in FIG. 8, the input of the phase detection circuit 70 is taken from the output of the field memory 20, but instead of this, a feedback type configuration may be used in which the output of the inverting circuit 71 is guided to the input of the phase detection circuit 70. Also,
Rather than directly detecting the burst phase of the carrier color signal,
The phase state of the reference color subcarrier at the start of field memory writing is stored in the field memory itself or in a separately provided register, and information regarding the reference color subcarrier and its stored phase state is stored at the time of start of field memory readout. It may be determined whether or not to invert the phase of the carrier color signal in the inversion circuit 71 by referring to .

Like FIG. 8, the configuration shown in FIG. 9 is also a modification of the color signal processing portion of the video signal reproducing apparatus shown in FIG. In the configuration shown in FIG. 9, the carrier color signal output from the arithmetic circuit 17 is demodulated into a time-division multiplexed color difference signal by the color demodulation circuit 72, and written into the field memory 20.
The signal read from 0 is modulated again into a carrier color signal in the color modulation circuit 73, and the subtraction circuit 18b in the arithmetic circuit 17.

It leads to the data selector 21b.

The configuration and operation of other parts are exactly the same as the configuration shown in FIG. Therefore, even in the configuration shown in Fig. 9, noise is suppressed by giving optimal coefficient circuit input/output characteristics to the luminance signal and chrominance signal, respectively, and the phase of the synchronization signal and chrominance subcarrier during special reproduction is maintained continuously. be able to.

Next, a video signal reproducing apparatus according to another embodiment of the present invention will be described using FIG. 10.

In FIG. 10, the same parts as those in the device shown in FIG. 1 are given the same numbers. The difference from the device shown in FIG.
7, a field memory 81 that stores the video signal output from the adder circuit 80, and a field memory 81 that adds the video signal output from the field memory 81 to the luminance signal and the carrier color signal. Y/
A phase detection circuit 83 that compares the burst phase of the carrier color signal output from the C separation circuit 82 and the Y/C separation circuit 82 with the phase of a reference color subcarrier (not shown) that serves as an operation reference for TBC6. and an inversion circuit 84 that inverts the phase of the carrier color signal output from the Y/C separation circuit 82 based on the output result of the phase detection circuit 8/3; An adder circuit 85 which adds the carrier color signal output from the circuit 84 and whose output is connected to the synchronization addition circuit 13; and an addition circuit 85 which adds the carrier color signal output from the circuit 84 and whose output is connected to the synchronization addition circuit 13; A data selector 86 that selects one of the two and outputs it to the DA converter 23 is provided.

When suppressing noise in the reproduced video signal using the configuration shown in FIG. 10, select the data selector 86 to the N side,
The output of the adder circuit 80 is guided to the DA converter 23, and the memory control circuit 26 has the configuration shown in FIG.
Control is performed to alternately repeat 63H, Y/
The C separation circuit 82 has a configuration, for example, as shown in FIG. 11, consisting of a PFloL and a subtraction circuit 102, and separates and outputs a luminance signal as the output of the subtraction circuit 102 and a carrier color signal as the output of BPFIOI. The calculation port +J@9 inputs the luminance signal separated by the Y/C separation circuit 8 and the luminance signal separated by the Y/C separation circuit 82,
After noise suppression is performed using the correlation between fields, the luminance signal is output to the adder circuit 80. Regarding the carrier color signal, the signal is 2 in the field memory 8].
In the case of a delay of 63H, the phase of the carrier color signal separated by the Y/C separation circuit 8 and the carrier color signal separated by the Y/C separation circuit 82 is reversed by 180°.

Therefore, the phase detection circuit 83 and the inversion circuit 84 work to match the subcarrier phase of the carrier color signal input to the arithmetic circuit 17 with the reference subcarrier. Since the phase of the carrier color signal output from the Y/C separation circuit 8 is matched with the reference subcarrier in the TBC 6, the arithmetic circuit 17 suppresses noise by using the correlation between the fields of the two input carrier color signals. can be done. The adder circuit 80 adds the noise-suppressed luminance signal and the noise-suppressed carrier color signal, and sends the noise-suppressed video signal to the DA converter 23 via the data selector 86.

As described above, in the video signal reproducing apparatus shown in FIG.
Noise can be suppressed in the reproduced video signal, and in this case, the input/output characteristics (coefficient characteristics) of the coefficient circuit 11 that extracts the noise of the luminance signal, and the input/output characteristics of the coefficient circuit 19 that extracts the noise of the carrier color signal. (coefficient characteristics) can be set independently from each other, and a sufficient noise suppression effect can be achieved for both the luminance signal and the color signal.

Next, the operation when special reproduction is performed using the apparatus shown in FIG. 10 will be explained. In arithmetic circuits 9 and 17, switch 2
7 and 28 to the T side, and coefficient circuits 11 and 19
The output of YlClC shunt circuit 8 is cut off, and the luminance signal and carrier color signal separated from each other are directly added together in addition circuit 80.

In the field memory 81, a signal equal to the reproduced video signal output from the AD converter 7 is stored, using the synchronization signal separated by the synchronization separation circuit 24 as a write timing reference. From the field memory 81, the reference synchronization generation circuit 2
The video signal read out in accordance with the reference synchronization signal generated in the Y/C9m circuit 82 is separated into a luminance signal and a carrier color signal. The carrier color signal is sent to the phase detection circuit 83.
The signal is then processed by an inverting circuit 84 to match the phase of the reference color subcarrier, and is added to the luminance signal in an adding circuit 85. The output of the adder circuit 85 is sent to the synchronization addition circuit 13, where its synchronization portion is replaced with the reference synchronization signal generated by the reference synchronization generation circuit 25, and then sent to the DA via the data selector 86 selected on the T side. It is supplied to the converter 23.

When performing special playback on CLV discs.

A reproduced video signal that has been discontinuous due to a track jump is intermittently written into the field memory 81 in accordance with its synchronization phase, and the video signal made continuous in accordance with the reference synchronization signal from the base 4 + synchronization generation circuit 25 is generated. In this way, you can perform special playback such as still, slow, fast forward, etc.
This method can also be applied to LV format discs, and the synchronization phase and color subcarrier phase of the output video signal are maintained continuously.

As described above, according to the embodiment shown in FIG. 10, noise suppression is performed using the inter-field correlation of the reproduced video signal, and the input/output characteristics of the coefficient circuit for noise extraction can be set independently for the luminance signal and the color signal. , the noise suppression effect can be enhanced. Furthermore, special playback can also be realized on CLV discs and the like using the same memory used for noise suppression.

At this time, the continuity of the horizontal and vertical synchronization phases and the color subcarrier phase of the output video signal can be maintained. Furthermore, field memory requires only one field of composite video signal, so memory costs are minimal, and when the circuit is integrated into an IC, the number of signal lines between peripheral ICs and memory ICs can be reduced; The number of pins can be reduced.

Note that the position of the synchronization addition circuit 13 in FIG. 10 may be at a stage before the addition circuit 85.

FIG. 12 shows a modification of the digital signal processing section of the video signal reproducing apparatus shown in FIG. 10.

In the configuration shown in FIG. 12, the switches 27 and 28 are omitted in the arithmetic circuits 9 and 17, and the adder circuit and the coefficient circuit are directly connected, and the output of the arithmetic circuit 9 and the output of the synchronization addition circuit 13 are connected directly. , a data selector 91 for selecting one
a, the output of the arithmetic circuit 17, and the output of the inversion circuit 84,
A data selector 91b selects one of the signals, an adder circuit 90 adds the outputs of the data selectors 91a and 91b, and a field memory selects one of the outputs of the adder 90 and the signal input to the Y/C separation circuit 8. 81 is provided.

In the configuration shown in FIG. 12, when performing noise suppression, all data selectors 91a to 91c are selected to the N side. Then, the luminance signal and carrier color signal separated by the Y/C separation circuit 8 and the luminance signal and carrier color signal read from the field memory 81 and separated by the Y/C separation circuit 82 are processed by a calculation circuit. 9, the carrier color signal is processed by the arithmetic circuit 17, and the resulting noise-suppressed luminance signal and the carrier color signal are added to the adder circuit 90.
to obtain the output video signal.

On the other hand, when performing special playback, the data selector 91a
-91c are all selected to the T side. As a result, the reproduced video signal bypasses the arithmetic circuits 9 and 17 and is directly written into the field memory 81. The video signal read from the field memory 81 is separated into a luminance signal and a carrier color signal by a Y/C separation circuit 82, and the color subcarrier phase of the carrier color signal is outputted by a phase detection circuit 83 and an inversion circuit 84. A synchronization signal is added to the luminance signal by the synchronization addition circuit 13, and then both are added again in the addition circuit 90, and the 12th signal is output as a video signal. The configuration shown in the figure can operate exactly the same as the configuration shown in FIG. 10, and the effects are also the same.

Note that the phase detection method in the phase detection circuits shown in FIGS. 10 and 11 is the same as in the case of the configuration shown in FIG.
It may be determined by a feedback type or by referring to the reference color subcarrier phase at the start of reading/writing from the field memory.

FIG. 13 shows another modification of the digital signal processing section of the video signal reproducing apparatus shown in FIG.

In the configuration of Fig. 13, the difference from Fig. 12 is that Y/C
a color demodulation circuit 92 that converts the carrier color signal separated by the separation circuit 8 into a time-division multiplexed color difference signal; a color modulation circuit 93 that modulates the color difference signal selected by the data selector 91b into a carrier color signal; A color demodulation circuit 94 is provided to convert the carrier color signal separated by the /C separation circuit 82 into a time-division multiplexed color difference signal, and the arithmetic circuit 17 processes the color difference signal. . Note that the arithmetic circuit 17 handles time-division multiplexed color difference signals in a time-division manner, as explained using FIG. In FIGS. 10 and 12.

In FIG. 13, the operation of inverting the phase of the carrier color signal by the inversion circuit 84 may be replaced with the operation of inverting the phase of the reference color carrier wave for demodulation in the color demodulation circuit 94, and it is necessary to detect whether or not to perform the inversion. may follow the detection method in the phase detection circuit 83 of FIGS. 10 and 12, and
The color subcarrier that serves as the operation reference for the color demodulation circuit 92 and the one-color modulation circuit 93 may be the same as the reference color subcarrier in the TBC 6 shown in FIG. 10. Also, the reproduced video signal can be separated into a luminance signal and a chrominance signal, and noise suppression processing can be performed by giving each of them optimal coefficient circuit input/output characteristics. Also, C.L.
Special reproduction is also possible for V discs using memory, and the phase continuity of the synchronization signal and color subcarrier in the output video signal at that time is maintained.

Note that in the configuration shown in FIG. 13, an alternative may be provided to invert the phase of the reference color subcarrier of the one-color demodulation circuit 49 to invert the phase of the carrier color signal input to the one-color demodulation circuit 94; Instead of the data selector 91b provided on the input side of the one-color modulation circuit 93, a color demodulation circuit 92 is provided.
A data selector is provided immediately before the carrier color signal separated by the Y/C separation circuit 8 when performing noise suppression, and the carrier color signal separated by the Y/C separation circuit 82 when performing special reproduction. It is also possible to configure such a configuration that the data are selected by respective data selectors and inputted to the color demodulation circuit 92, and the output of the arithmetic circuit 17 is directly inputted to the color modulation circuit 93.

In this case, the configuration of the arithmetic circuit 17 is similar to that of the arithmetic circuit 17 shown in FIG. 10, that is, it has a switch 28. ), the output of the color demodulation circuit 92 is output as is during special playback. Even with such a configuration, effects completely equivalent to those shown in FIG. 13 can be obtained.

FIG. 15 shows a configuration of the Y/C separation circuit 82 in FIGS. 10, 12, and 13, which is different from that in FIG. 11.

In the configuration shown in FIG. 14, from the video signal read from the field memory 81, the LH delay circuit 103 and the subtraction circuit 10
4. A comb filter circuit consisting of a coefficient circuit 105 with a negative coefficient value separates the carrier color signal, and a subtraction circuit 106 removes the carrier color signal from the video signal to separate the luminance signal.

When the configuration shown in FIG. 14 is used for the Y/C separation circuit 82, it is preferable that the signal delay amount of the field memory 81 during the noise suppression operation is always 262H.

Due to the effect of the comb filter of the Y/C separation circuit 82,
The signals input to the arithmetic circuits 9 and 17 via the Y/C separation circuit 82 are output from the arithmetic circuits 9 and 17 and
This is because it is the average value of the signal after 2H and the signal after 263H, and the best correlation between fields can be obtained.

If the Y/C separation circuit 82 having the configuration shown in FIG. 14 is used and the delay amount in the field memory 81 is set to 262H, the Y/C separation #i@
The phases of the carrier color signals separated by paths 8 and 82 are equal to each other, and the phase detection circuit 83 and the inversion circuit 84 are provided in FIGS. 10 and 12, or the color demodulation circuits 9 and 1 are provided in FIG. However, it is not necessary to invert the phase of the reference color subcarrier.

The above is necessary in order to maintain the continuity of the synchronization signal and color subcarrier phase of the output video signal during special lif generation.

FIG. 15 shows another modification of the digital signal processing section of the video signal reproducing apparatus shown in FIG. 10.

In the configuration shown in FIG. 15, the output of the field memory 8]- is directly input to the synchronization addition circuit 13, and the data selector 91d selects and outputs one of the output of the addition circuit 9o and the output of the synchronization addition circuit 13. When performing noise suppression, the data selectors 91c and 91d select the N side, and the luminance signal and carrier color signal separated by the Y/C separation circuit 8 are subjected to noise suppression processing in the calculation circuits 9 and 17, respectively. The signal added by the adder circuit 90, sent as an output to the outside, and written to the field memory 81, which is read out with a delay of 262H in the field memory 81, is configured as shown in FIG. 11 or FIG. 14. The Y/C separation circuit 82 separates the signal into a luminance signal and a carrier color signal, and sends the signals to arithmetic circuits 9 and 17. On the other hand, when performing special playback, the data selector 91c.

91d to the T side, the reproduced video signal is written directly to the field memory 81, and the read signal is sent to the synchronous addition circuit 1.
At step 3, a synchronization signal is added and sent as an output to the outside.

As described above, according to the configuration shown in FIG. 15, it is possible to suppress noise by giving different coefficient circuit input/output characteristics to the luminance signal and color signal, and also to perform special playback on CR, V discs, etc. It is possible. Moreover, the memory capacity is sufficient for one field of the conventional video signal.However, with the configuration shown in Figure 15, it is not possible to maintain the phase continuity of the synchronization signal of the video signal output during special playback and the color subcarrier; It is possible to suppress phase discontinuity to the extent that it does not affect at all on a TV monitor. For example, if the start timing of each reading and writing of the field memory 82 is the rising point of the next color subcarrier from the start timing of a certain scanning line in each field, the output video signal during special playback will be the color subcarrier. The carrier phase is continuous, and the amount of discontinuity in the synchronization phase can be set to -the color subcarrier period.

〔Effect of the invention〕

According to the present invention, a color video signal reproduced from a medium is once separated into a luminance signal and a carrier color signal (or color difference signal), and an arithmetic circuit for noise suppression is provided for each separated signal. The input and output characteristics of the coefficient circuit can be independently set to be optimal for the signals of However, a sufficient noise suppression effect can be obtained, and side effects such as the occurrence of afterimages can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a video signal reproducing device as an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the color demodulation circuit in FIG. 1, and FIG. 4 is a block diagram showing a modification of the arithmetic circuit in FIG. 1; FIG. 5 is a block diagram showing another modification of the arithmetic circuit in FIG. 1; 6 is a block diagram showing another modification of the arithmetic circuit in FIG. 1, FIG. 7 is a block diagram showing another specific example of the memory control circuit in FIG. 1, and FIG. 8 is a block diagram showing another modification of the arithmetic circuit in FIG. FIG. 9 is a block diagram showing another modification of the color signal processing section of the video signal reproducing device in FIG. 1, and FIG. A block diagram showing a video signal reproducing device as another embodiment of the invention, FIG. 11 is a block diagram showing a specific example of the Y/C separation circuit in FIG. 10, and FIG. 12 is a block diagram showing a video signal reproducing device in FIG. 10. 13 is a block diagram showing another modification of the digital signal processing part of the video signal reproducing apparatus in FIG. 10; FIG. 14 is a block diagram showing a modification of the digital signal processing part of the video signal reproduction apparatus in FIG. Y/C in
FIG. 15 is a block diagram showing another specific example of the separation circuit, and FIG. 15 is a block diagram showing another modification of the digital signal processing portion of the video signal reproducing device in FIG. 10 etc. FIG. 16 is a block diagram showing a conventional noise suppression circuit. It is. 8.82...Y/C separation circuit, 9,17...Arithmetic circuit, 12,20.81...Memory, 1;3.Synchronization addition circuit, 14,21.86.91a, 91b, 91C・・・
・Data selector, 16,72,92.94...Color demodulation circuit, 22,73,9:3...Color modulation circuit, 25...
- Reference synchronization generation circuit, 26... Memory control circuit, 27.28... Switch, 29, 91d... Data selector, 49... Switch, 70.83... Phase detection circuit, 71.84. ...Inversion circuit.庬 2 Prisoner Kunisuke's 謬萬 17 fig.

Claims (1)

[Claims] 1. In a video signal reproducing device that reproduces a video signal by demodulating a signal recorded on a medium, a luminance signal/a signal that separates the reproduced video signal into a luminance signal and a carrier color signal; Color signal separation circuit (hereinafter referred to as Y/C separation circuit)
a first arithmetic circuit that suppresses noise components included in the luminance signal separated by the Y/C separation circuit;
A color demodulation circuit that demodulates the carrier color signal separated by the separation circuit into a color difference signal or time-division multiplexed color difference signal, and noise contained in the color difference signal or time-division multiplexed color difference signal output from the color demodulation circuit. The second one suppresses the components.
an arithmetic circuit, a first memory that stores the signal output from the first arithmetic circuit, a second memory that stores the signal output from the second arithmetic circuit, and first and second memories. a reference synchronization generation circuit that generates a reference synchronization signal for determining the timing for reading out a signal stored in the first memory; an additional synchronization addition circuit; a color modulation circuit that modulates the signal output from the second arithmetic circuit and the signal read from the second memory into carrier color signals; and an output from the first arithmetic circuit. a first video signal consisting of a signal outputted from the second arithmetic circuit and a signal passed through the color modulation circuit; a signal read from the first memory and passed through the synchronization addition circuit; and signal selection means for selecting and outputting one of the second video signals read from the memory and passing through the color modulation circuit. Signal regenerator. 2. The first or second arithmetic circuit uses the signal output from the Y/C separation circuit or the color demodulation circuit as a first operation signal, and reads out the signal from the first or second memory. signal as a second signal to be operated, and by calculating both of them, noise components are suppressed, and when the signal selection means selects the first video signal, the first or second signal is The first signal is configured such that the time difference between the first signal to be operated and the second signal to be operated which are computed in the arithmetic circuit is alternately 262 horizontal scanning periods and 263 horizontal scanning periods every one or more field periods. Alternatively, the delay time of the signal read from the second memory is determined based on the timing of the reproduced video signal, and when the signal selection means selects the second video signal, the second video signal is a memory control circuit that determines the delay time of the signal read from the first or second memory based on the timing of the reproduced video signal and the reference synchronization signal so that the synchronization phase of the signal is continuous; When the signal selection means selects the second video signal, the first and second video signals are selected such that the first operand signal is directly guided to the first memory and the second memory. 2. The video signal reproducing apparatus according to claim 1, further comprising means for stopping the operation of the arithmetic circuit or bypassing the first and second arithmetic circuits. 3. The first or second arithmetic circuit uses the signal output from the Y/C separation circuit or the color demodulation circuit as a first operation signal, and reads out the signal from the first or second memory. A signal obtained as the arithmetic mean of the signal and a signal obtained by delaying the signal by one horizontal scanning period is used as the second signal to be operated, and noise is suppressed by calculating both of them. When selecting the first video signal, the time difference between the first operated signal operated in the first or second arithmetic circuit and the signal read from the first or second memory. is 262 horizontal scanning periods, the delay time of the signal read out from the first or second memory is determined based on the timing of the reproduced video signal; When selecting a signal,
The delay time of the signal read from the first or second memory is determined based on the timing of the reproduced video signal and the reference synchronization signal so that the synchronization phase of the second video signal is continuous. When the memory control circuit and the signal selection means select the second video signal, the first operated signal and the second operated signal are sent to the first memory and the second memory. 2. Means for stopping the operation of the first and second arithmetic circuits or bypassing the first and second arithmetic circuits so that the first and second arithmetic circuits are directly guided. Video signal reproducing device. 4. In a video signal reproducing device that demodulates a signal recorded on a medium and reproduces a video signal, a Y/C that separates the reproduced video signal into a luminance signal and a carrier color signal.
a separation circuit; a first arithmetic circuit that suppresses noise components included in the luminance signal separated by the Y/C separation circuit;
a second arithmetic circuit that suppresses noise components included in the carrier color signal separated by the Y/C separation circuit; a first memory that stores the signal output from the first arithmetic circuit; a second memory that stores signals output from the arithmetic circuit; a reference synchronization generation circuit that generates a reference synchronization signal for determining the timing for reading out the signals stored in the first and second memories; a synchronization addition circuit that adds a corresponding portion of the reference synchronization signal to at least the vertical synchronization portion of the signal read from the first memory; and an inversion circuit that inverts the phase of the signal read from the second memory as necessary. and a first video signal consisting of the signal output from the first arithmetic circuit and the signal output from the second arithmetic circuit, and a first video signal read from the first memory and passed through the synchronization addition circuit. and signal selection means for selecting and outputting one of the second video signals formed by combining the signal and the signal read from the second memory and passed through the phase inversion circuit. A video signal reproducing device characterized by: 5. The first or second arithmetic circuit uses the signal output from the Y/C separation circuit as the first signal to be operated on, and the signal read from the first memory or the signal output from the inversion circuit. The noise component is suppressed by calculating both signals as a second signal to be operated, and when the signal selection means selects the first video signal, the first or second signal is The time difference between the first operated signal and the second operated signal operated in the arithmetic circuit of
When the delay time of the signal read from the first or second memory is determined to be 2 horizontal scanning periods and 263 horizontal scanning periods, and the signal selection means selects the second video signal, , the delay time of the signal read from the first or second memory is based on the timing of the reproduced video signal and the reference synchronization signal so that the synchronization phase of the second video signal is continuous. a memory control circuit for determining the second video signal; means for stopping the operation of the first and second arithmetic circuits or bypassing the first and second arithmetic circuits; and when the signal selection means selects the first video signal, When the signal selection means selects the second video signal so that the first signal to be operated on and the second signal to be operated in the second operation circuit have the same phase, the second video signal 5. The video signal reproducing apparatus according to claim 4, further comprising means for controlling the operation of said inversion circuit so that the phase of the carrier color signal in the signal is continuous. 6. The first or second arithmetic circuit uses the signal output from the Y/C separation circuit as the first signal to be operated on, and the signal read from the first memory or the signal output from the inversion circuit. A signal obtained as the arithmetic mean of a signal obtained by delaying the signal and a signal obtained by delaying these signals by one horizontal scanning period is used as the second operand signal, and by calculating both, noise components are suppressed and the signal selection is performed. When the means selects the first video signal, the first operand signal operated in the first or second arithmetic circuit and the signal read from the first memory or the inverting circuit The delay time of the signal read from the first or second memory is determined so that the time difference between the signal and the signal output from the first or second memory is 262 horizontal scanning periods, and the signal selection means selects the second video signal. In this case, the delay time of the signal read from the first or second memory is reproduced and the timing of the reference synchronization signal is adjusted so that the synchronization phase of the second video signal is continuous. When the memory control circuit and the signal selection means select the second video signal, the first signal to be operated on and the second signal to be operated on are connected to the first memory and the second signal to be operated on. means for stopping the operation of the first and second arithmetic circuits or bypassing the first and second arithmetic circuits so that the signals are directly guided to the second memory; When selecting a video signal, the signal selection means selects the second video signal so that the phases of the first signal to be operated and the second signal to be operated in the second arithmetic circuit are equal. 5. The video according to claim 4, further comprising means for controlling the operation of the inverting circuit so that the phase of the carrier color signal in the second video signal is continuous when the second video signal is selected. Signal regenerator. 7. A color demodulation circuit for color demodulating the signal output from the second arithmetic circuit is provided, the signal output from the color demodulation circuit is stored in the second memory, and in place of the inversion circuit, A color modulation circuit that modulates the signal read from the second memory into a carrier color signal is provided, and when the signal selection means selects the first video signal, the Y/
When the signal selection means selects the second video signal so that the phase of the carrier color signal separated by the C separation circuit and the signal output from the color modulation circuit are equal, the signal selection means selects the second video signal. 5. The video signal reproducing apparatus according to claim 4, wherein the phase of the signal output from the color modulation circuit is determined so that the phase of the carrier color signal in the video signal is continuous. 8. In a video signal reproducing device that reproduces a video signal by demodulating a signal recorded on a medium, a first Y/Y signal that separates the reproduced video signal into a luminance signal and a carrier color signal;
a C separation circuit, a first arithmetic circuit that suppresses noise components included in the luminance signal separated by the first Y/C separation circuit, and a carrier separated by the first Y/C separation circuit. a second arithmetic circuit that suppresses noise components included in the color signal; and a signal output from the first arithmetic circuit and the second arithmetic circuit.
a memory for storing a first video signal consisting of a signal outputted from the arithmetic circuit of the second video signal, and a second Y/V signal for separating the signal read from the memory into a luminance signal and a carrier color signal.
A C separation circuit and an inversion circuit that inverts the phase of the carrier color signal separated by the second Y/C separation circuit as necessary, and the first calculation circuit The luminance signal separated by the C separation circuit is used as a first signal to be operated, and the luminance signal separated by the second Y/C separation circuit is used as a second signal to be operated, and both are operated. At the same time, the second arithmetic circuit uses the carrier color signal separated by the first Y/C separation circuit as a first signal to be operated, and suppresses the noise component by using the second Y/C separation circuit. A video signal reproducing apparatus characterized in that the carrier color signal separated by a circuit and passed through the inverting circuit is used as a second signal to be operated, and noise components are suppressed by computing both signals. 9. A reference synchronization generation circuit that generates a reference synchronization signal for determining the timing of reading out a signal stored in the memory; a synchronization addition circuit that adds a corresponding portion of the reference synchronization signal to at least a vertical synchronization portion of a video signal formed by combining the carrier color signal that has been separated by the Y/C separation circuit and passed through the inversion circuit; and the first operation. the first video signal consisting of a signal output from the circuit and the signal output from the second arithmetic circuit, the luminance signal separated by the second Y/C separation circuit, and the second and the carrier color signal that has been separated by the Y/C separation circuit and passed through the inversion circuit, and selects and outputs one of the second video signals that has passed through the synchronization addition circuit. a signal selection means, and when the signal selection means selects the first video signal, the first video signal calculated in the first or second calculation circuit;
read from the memory so that the time difference between the main component of the second signal to be operated on and the main component of the second signal to be operated on is 262 horizontal scanning periods and 263 horizontal scanning periods alternately every one or more field periods. determining the delay time of the signal to be played based on the timing of the reproduced video signal,
When the signal selection means selects the second video signal, the video signal is reproduced with the delay time of the signal read out from the memory so that the synchronization phase of the second video signal is continuous. a first memory control circuit that determines the signal based on the timing of the signal and the reference synchronization signal, and when the signal selection means selects the second video signal, inputs the second video signal to the first Y/C separation circuit. the first
and means for stopping the operation of the second arithmetic circuit or bypassing the first and second arithmetic circuits, and when the signal selection means selects the first video signal, the second arithmetic circuit When the signal selection means selects the second video signal so that the first signal to be operated and the second signal to be operated in the arithmetic circuit have the same phase, means for controlling the operation of the inversion circuit so that the phase of the carrier color signal is continuous;
9. The video signal reproducing apparatus according to claim 8, further comprising: a video signal reproducing apparatus. 10. When the signal selection means selects the first video signal instead of the first memory control circuit, the second operand is operated in the first or second arithmetic circuit. A signal read from the memory such that the main component of the signal is an arithmetic average of a signal obtained by delaying the main component of the first operated signal by 262 horizontal scanning periods and a signal obtained by delaying the main component by 263 horizontal scanning periods. and when the signal selection means selects the second video signal, the delay time of the signal read out from the memory is determined so that the synchronization phase of the second video signal is continuous. 10. The video signal reproducing apparatus according to claim 9, further comprising a second memory control circuit that determines the timing based on the timing of the reproduced video signal and the reference synchronization signal. 11. A reference synchronization generation circuit that generates a reference synchronization signal for determining the timing of reading out a signal stored in the memory, and a reference synchronization signal corresponding to at least a vertical synchronization portion of the signal read out from the memory. a synchronization addition circuit that adds a synchronization section; and a synchronization adding circuit that adds a synchronization signal to the first video signal, which is a combination of the signal output from the first arithmetic circuit and the signal output from the second arithmetic circuit, and the synchronization signal read from the memory; 9. The video signal reproducing apparatus according to claim 8, further comprising signal selection means for selecting and outputting one of the second video signals that has passed through the additional circuit. 12. In a video signal reproducing device that demodulates a signal recorded on a medium and reproduces a video signal, a first Y/C separation circuit that separates the reproduced video signal into a luminance signal and a carrier color signal; A first arithmetic circuit suppresses noise components included in the luminance signal separated by the first Y/C separation circuit, and converts the carrier color signal separated by the first Y/C separation circuit into a color difference signal. Alternatively, a first color demodulation circuit demodulates the time-division multiplexed color difference signal, a second arithmetic circuit that suppresses noise components included in the signal output from the first color demodulation circuit, and a second arithmetic circuit that suppresses noise components included in the signal output from the first color demodulation circuit. a color modulation circuit that modulates the signal output from the first arithmetic circuit into a carrier color signal; and a memory that stores a signal obtained by adding the signal output from the first arithmetic circuit and the signal output from the color modulation circuit. and a second Y/C separation circuit that separates the signal read from the memory into a luminance signal and a carrier color signal, and converts the carrier color signal separated by the second Y/C separation circuit into a color difference signal or a time signal. a second color demodulation circuit that demodulates the divided and multiplexed color difference signal;
The first arithmetic circuit uses the luminance signal separated by the first Y/C separation circuit as a first signal to be operated, and
The luminance signal separated by the /C separation circuit is used as a second signal to be operated, and noise components are suppressed by computing both of them, and the second computing circuit outputs an output from the first color demodulation circuit. The signal to be operated is the first signal to be operated,
A video signal reproducing circuit characterized in that a signal output from the second color demodulation circuit is used as a second signal to be operated on, and noise components are suppressed by computing both signals.