JPH0264838A - Communication controller - Google Patents

Abstract

PURPOSE:To prevent the occurrence of the drop of a data frame since a reception buffer comes to a full state by transmitting a reception buffer full informing flag to an opposite side, and transmitting data from the opposite side by means of the state of the flag. CONSTITUTION:The transmission central processing unit (CPU) 12 of a communication controller (CCE) 1 transmits the reception buffer full information flag on a self side, which is stored in a shared memory 16 to the opposite side, namely a CCE 1' side. On the CCE 1' side, reception CPU 13' sets the reception buffer full flag on the opposite side in a shared memory 16', or resets the flag. Thus, the CCE 1 side can supervise the data stored state of the reception buffer 6 on the CCE 1 side, and it can transmit data to be CCE 1 side by the state, and therefore the overrunning of the reception buffer 6 can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a communication control device that manages the data storage state of a reception buffer used for data communication.

(Prior Art) A communication control device is a type of human output control device, and terminal devices connected thereto are generally located at remote locations, and are connected by a communication line including transmission equipment. This communication control device requires functions such as control and monitoring of transmission equipment and error control for transmission errors occurring on communication lines. Key functions include interface matching, serial-to-parallel conversion, transmission control, and buffering.

FIG. 5 is a block diagram showing this type of conventional communication control device.

In the figure, communication control equipment (hereinafter referred to as CCE) 1.
1' are connected via a full-duplex communication line 2. Each CCEI, 1' is a central processing unit (hereinafter referred to as CP
CPU groups 41, 42...4n and 41' 42, which are host devices, are
'...4n' is connected. CCEl, 1' is
Each of them is provided with a transmission buffer 5.5' and a reception buffer 6.6' for temporarily storing data during transmission and reception.

The CPU selector switches 3 and 3' are CCE 1, respectively.
．． 1' and CPU group 41...4 n and 41'...4
n' in a time-sharing manner.

FIG. 2 is a diagram showing a frame format when either CCE 1 or CCE converts transmission data into a transmission frame in units of transfer and sends it to the communication line 2. As shown in the figure, the transmission frame includes a flag sequence 71 indicating the start and end of this frame, and an identification field (hereinafter referred to as ID) 7 indicating the address of the station that transmits and receives this frame.
2. If this frame is a command, it indicates an operation command to the partner station; if it is a response, it indicates a control field 73 that indicates a response to the command in the command frame, a data section 74 that indicates data information, and a CR that indicates a frame check code.
CC (cyclic redundancy check)
code) 75.

The communication control device configured as described above operates as follows.

First, a transmission command and transmission data are sent from the CPU 4n of the CPU group 41 to 4n, which is a host device on the transmission side, to the CCEI on the same transmission side via the CPU changeover switch 3. When CCEl receives a transmission command, it temporarily stores the transmission data in the transmission buffer 5. And CPU 4 n
Return and report the sending order receipt status. Then C
The CE 1 converts the transmission data temporarily stored in the transmission buffer 5 into the transmission frame shown in FIG. 2, and sends this transmission frame to the communication line 2. The transmission frame sent to the communication line 2 is received by the CCEI' on the receiving side and temporarily stored in the receiving buffer 6' therein. Here, when receiving a receive command from the CPU 4n of the host device, the CCEI' checks whether the ID 72 of the receive frame already stored in the receive buffer 6' matches the ID specified in the above-mentioned receive command. Check.

If the ID72 matches, this received data is sent to the CP.
It is transferred to U4n' and at the same time reports the reception command completion status to CPU4n'.

The above-mentioned operation is similarly carried out in the reverse direction when a transmission command is issued from the CPU 4n to the CCEI'. In this case, a transmission frame is sent from CCEI' to CCE 1, and the data received at CCEI is sent to the CPU
The data is transferred to the CPU 4n in response to a reception command from the CPU 4n.

In the conventional communication control device shown above, one side of the C
If the PU group issues transmission commands frequently, the CC on the receiving side
When an overrun occurs in the H reception buffer, the dropped frame is retransmitted by a program in the host device.

(Problem to be solved by the invention) However, in recent years, as high-speed digital lines have become widespread, data communication speeds have increased, and transmission commands from CPU groups are generated asynchronously. However, it is becoming difficult to synchronize. Therefore, when an overrun occurs in the reception buffer, as described above, if a retry is performed by the program of the host device, there is a problem that the efficiency of using the line decreases.

The present invention has been made focusing on the above points, and
An object of the present invention is to provide a communication control device in which a CE can dynamically monitor the data storage state of a receiving buffer of a CCH on the receiving side, and when capacity is running out, temporarily interrupts transmission commands and prevents reception. That is.

(Means for Solving the Problems) The present invention provides a communication control device that is connected to each host device and connected to each other via a communication line, and controls the transmission and reception of data between them according to commands from the host device. , a reception buffer that receives and temporarily stores data according to a command from a host device; and a reception buffer that detects that the data stored in the reception buffer is greater than or equal to the first specified value when the received data of a first specified value or more is stored in this reception buffer. means for setting a receive buffer full notification flag indicating the first specified value, and resetting the receive buffer full notification flag when the value falls below another second specified value smaller than the first specified value; When transmitting a frame, the reception buffer full notification flag is checked, and if this flag is set, a predetermined bit in the control section of the transmission frame is set to 1.
Set to °°, and 0゛′ when this flag is not set.
a flag setting means for setting and transmitting a transmission frame;
When the transmission frame is received and the predetermined bit of the control unit is ゛1゜, the reception buffer full flag is set to indicate that the reception buffer stores reception data equal to or greater than the specified value. When it is Ooo, there is a means to reset this flag, and when receiving a transmission command from the host device,
The above reception buffer full flag is checked, and if this flag is set, it indicates that the data to be transmitted is not received from the above upper device, and the above reception buffer is storing data in excess of the above specified value in this higher order device. The invention is characterized by having a means for reporting information.

(Function) The above communication control device sets a flag indicating this in the transmission frame and sends it to the transmission side when the reception buffer that receives data is filled with more than a predetermined value according to a command from the host device. . The transmitting side receives and inspects this frame, and transmits data according to the data storage state of the receiving buffer on the receiving side. Thereby, it is possible to prevent data frames from being dropped due to the reception buffer being filled with stored data.

(Example) Examples of the present invention will be described in detail below.

FIG. 1 is a block diagram showing an embodiment of a communication control device of the present invention. In FIG. 1, parts that are the same as or correspond to those in the conventional example shown in FIG. 5 are given the same reference numerals, and their explanation will be omitted as appropriate.

In the figure, CCEl, 1' is connected via a full-duplex line 2 as in the conventional example, and a CPU changeover switch 3
．． 3' to the CPU groups 41, 42, . . . of the host device.
4n and 41'42' . . . 4n'.

The CCE 1.1' includes a transmission buffer 5.5' and a reception buffer 6.6' for temporarily storing transmission data and reception data, respectively. In addition, these CCE 1.1' are
A transmission control section 7.7' is connected to the transmission buffer 5.5' and converts the transmission data into a transmission frame, and a reception control section 8 is connected to the reception buffer 6.6' and converts the reception frame into reception data. .8' Transmission system upper interface (I/F) 9. One side is connected to the CPU changeover switch 3.3', the other side is connected to the transmission buffer 5.5', and interfaces transmission data from the upper device. 9' CPU selector switch 3.
3', and the other is connected to the receiving buffer 6.
．． A receiving system upper interface (I/F) that is connected to 6' and interfaces the received data to the upper device.
10.10' Transmission system upper interface (I/F)
Transmission CPU 12.12' which is connected to 9.9' via common bus 11.11' and executes the transmission system control program respectively;
F) Receiving CPU 13.13' and common bus 11.11, each connected to 10.10' via a common bus 11.11' and executing a receiving system control program, respectively.
Transmission local memories 14.14' are connected to the common bus 11.1F and store the control programs for the transmission system, respectively, and reception local memories 15.15 are connected to the common bus 11.1F and store the control programs for the reception system, respectively.
', respectively connected to the common bus 11.11', and transmitting C
It consists of a shared memory 16.16' which can be commonly accessed by the PU 12.12' and the receiving CPU 13.13'.

Regarding the communication control device of the present invention having the above configuration, FIG.
The operation will be explained according to FIGS. 3 and 4.

3(a) to 3(d) are flowcharts explaining the operation of this embodiment, and FIG. 4 is a flowchart of the receiving CPU 13 on the CCE l side.
It is an explanatory diagram showing operation of.

First, on the CCEI' side, one of the host devices, for example, CPU4.
A transmission command is issued from n' to the transmission CPU 12' via the CPU selector switch 3' and the transmission system upper ink interface (I/F) 9' [Step (a) in FIG. 3]. The transmitting CPU 12' connects to the shared memory 1 via the common bus 11'.
The other side receiving buffer full flag indicating whether the receiving buffer 6 of the other side, that is, the CCE I side, stored in 6' is filled with data is checked [steps (1) and (2) in FIG. 3(a)]. When this receiving buffer full flag on the other side is set, it is reported to the CPU 4n' of the host device that the receiving buffer at the destination, that is, the receiving buffer 6 on the CCEI side is filled with data [Fig. 3 (a) ) step■
Ko. Upon receiving this, the CPU 4n' attempts to send the transmission command again [Step (a) in FIG. 3]. On the other hand, when the above-mentioned receiving buffer full flag on the other party is not set, the transmission data is transmitted to the other party's CCE I side. CCEI
On the side, the reception C is transmitted via the communication line 2 and the reception control section 8.
Under the control of the PU 13, the reception buffer 6 receives the above-mentioned transmission data [step (b) in FIG. 3]. Receiving CPU
Step 13 checks whether the reception buffer 6 has received transmission data equal to or greater than the first specified value [FIG. 3(b) Step 2]. When the first specified value or more is exceeded, a receive buffer full notification flag is set in the shared memory 16 via the common bus 11, indicating that the receive buffer 6 is filled with the first specified value or more [Fig. 3(b) Step■]. After that, a reception command is issued from the CPU 4n of the host device to the reception CPU 13, and the reception data is transferred from the reception buffer 6 to the CPU 4n.
4n [FIG. 3(b) Step ■]. Then, the receiving CPU 13 checks whether the received data stored in the receiving buffer 6 has become equal to or less than the second specified value [step [phase] in FIG. 3(b)]. If it is not less than the second specified value, return to step
Figure (b) Step ■].

In this way, the receiving buffer 6 on the CCEL side becomes ready to receive data at any time. Therefore, on the CCEl side, the higher-level device, for example, the CPU 4n, sends a transmission command to the transmission CPU 12 [FIG. Check buffer full contact flag [
Figure 3 (C) Steps ■, ■]. When this self-side reception buffer full notification flag is set, the sending CPU 1
2 sets the specific bit of the control unit 73 of the transmission frame shown in FIG. Figure 3 (c) Steps ■, ■, ■].CC
On the EI' side, the reception control unit 8' receives the above-mentioned transmission frame from the CCEI side via the communication line 2 under the control of the reception CPU 13' and separates it into data [Fig. 3(d)]
Step■]. Then, the receiving CPU 13' stores the received data in the receiving buffer 6' and inspects the received frame. That is, it is checked whether the specific bit of the received frame control section is 1°' [Steps ■ and ■ in FIG. Set the receive buffer full flag [Figure 3 (d)
) Step ■], otherwise set this flag [Figure 3(d) Step ■]. This allows C.C.
The E1' side becomes ready to transmit data to the CCEl side.

FIG. 4 is an explanatory diagram showing the operation sequence of the receiving CPU 13 on the CCEl side described above.

As explained above, by monitoring the data storage state of the receiving buffer 6 on the CCEI side on the CCEI' side, it is possible to prevent the receiving buffer 6 from overrunning.

In the above embodiment, as shown in FIG. 3(a), if the receive buffer full flag is set on the CCE I side and there is a transmission command from the higher-level device, the receive buffer on the other side is The configuration is such that the status that the data is filled is reported to the higher-level device, which causes the higher-level device to retry sending the transmission command. In this case, while reporting the above to the higher-level device, another flag is also set,
When the reception buffer 6 on the other side becomes equal to or less than a second specified value and the reception buffer full flag is reset, means for notifying the higher-level device by an interrupt that the reception buffer on the other side is empty using this other flag. may be provided.

(Effects of the Invention) The communication control device of the present invention described above sets a flag indicating this when the received data exceeds a predetermined value in the receive buffer and transmits it to the other party, and depending on the state of this flag. By providing a means for transmitting data from the other party, it is possible to easily avoid dropping data frames due to the reception buffer becoming full. Therefore, the data retransmission protocol of the host device due to frame drop can be omitted, and the line can be used efficiently.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the communication control device of the present invention, FIG. 2 is a block diagram showing the format of a transmission frame, and FIGS. FIG. 4 is a flowchart explaining the operation, FIG. 4 is a diagram explaining the operation sequence of the receiving CPU of the embodiment shown in FIG. 1, and FIG. 5 is a block diagram showing a conventional communication control device. 1.1'...Communication control equipment (CCE), 3.3'...
・(Full duplex) communication line, 5.5'...Transmission buffer, 6.6'...Reception buffer, 7.7'...Transmission control section, 12.12'...Transmission CPU . 13.13'...Receiving CPU. 41-4n, 41'-4n - CPU. Figure 4: Operation flow chart of the device shown in Figure 1 Figure 3 (C) Operation flow chart of the device shown in Figure 1 Figure 3 (d)

Claims (1)

[Scope of Claims] A communication control device that is connected to each host device and to each other via a communication line, and controls the transmission and reception of data between them according to commands from the host device, comprising: A receive buffer that receives and temporarily stores data according to a command; and a receive buffer that indicates that the data stored in the receive buffer is greater than or equal to the first specified value when the received data that is greater than or equal to the first specified value is stored in this receive buffer. means for setting a full communication flag and resetting the reception buffer full communication flag when the value becomes equal to or less than a second specified value smaller than the first specified value; and when receiving a transmission command from the higher-level device and transmitting a transmission frame; The reception buffer full communication flag is checked, and if the flag is set, a predetermined bit in the control section of the transmission frame is set to "1", and if the flag is not set, it is set to "0". a flag setting means for transmitting a transmission frame; and a reception unit that receives the transmission frame and, when a predetermined bit of the control unit is “1”, indicates that reception data equal to or greater than the specified value is stored in the reception buffer. means for setting a buffer full flag and resetting the flag when it is "0"; and means for inspecting the receiving buffer full flag when receiving a transmission command from a host device, and when the flag is set, transmitting. 2. A communication control device comprising means for not receiving data from the host device and reporting to the host device that the receive buffer stores data equal to or greater than the first specified value.