JPH0262104A - Nmr signal amplifier - Google Patents

Nmr signal amplifier

Info

Publication number
JPH0262104A
JPH0262104A JP63212476A JP21247688A JPH0262104A JP H0262104 A JPH0262104 A JP H0262104A JP 63212476 A JP63212476 A JP 63212476A JP 21247688 A JP21247688 A JP 21247688A JP H0262104 A JPH0262104 A JP H0262104A
Authority
JP
Japan
Prior art keywords
circuit
input
amplifier
fet
low
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63212476A
Other languages
Japanese (ja)
Inventor
Shigehiro Kameshima
亀島 成弘
Koichi Ono
孝一 尾野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP63212476A priority Critical patent/JPH0262104A/en
Publication of JPH0262104A publication Critical patent/JPH0262104A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To form the amplifier of a low input output noise ratio coefficient with a low impedance input circuit by connecting plural amplifying circuits such as an electric field effect transistor in parallel and increasing the amplification factor of an apparant amplifier. CONSTITUTION:In a parallel circuit to connect the gate and drain of electric field effect transistors FET1 and 2, resistances 8 and 9 and a resistance for a gate bias and a load resistance 3 are made common, source resistances 4 and 5 are made individual and the variance of FET1 and 2 is prevented. Capacitors 6 and 7 are used as the high frequency bypass capacitor of the resistances 4 and 5. Thus, the drain current to flow at the resistance 3 can be made two times as much as the individual FET. Here, an input output noise ratio coefficient NF is reduced by the influence of the input gate capacity of the FET and with the capacity as a part of an input resonance circuit, the influence can be removed. Thus, a low NF amplifier can be formed by the low impedance input circuit.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、高周波用低雑音増幅器、特にMRI装置のN
MR信号用の前置増幅器に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention provides a high frequency low noise amplifier, particularly an N
The present invention relates to a preamplifier for MR signals.

〔従来の技術〕[Conventional technology]

一般にMRI装置におけるNMR信号検出用プローブの
出力インピーダンスは雑音電圧を抑圧する点や信号線路
の取扱い上からも低インピーダンス(Zo=50Ω)に
する方が有利である。このため高入力インピーダンスの
電界効果トランジスタ(以後、FETと略称。)等を用
いる場合、従来はエレクトロニクスレター、27巻、1
975年11月の596頁から597頁(Electr
onicsLetters、596〜697.27t)
+、11.1975)に記載のごとく、トランス回路に
よるインピーダンス変換回路を用いていた。
Generally, it is advantageous to set the output impedance of an NMR signal detection probe in an MRI apparatus to a low impedance (Zo=50Ω) from the viewpoint of suppressing noise voltage and handling of the signal line. For this reason, when using high input impedance field effect transistors (hereinafter abbreviated as FETs), etc., conventionally Electronics Letters, Vol. 27, 1
November 975, pages 596 to 597 (Electr
onicsLetters, 596-697.27t)
+, 11.1975), an impedance conversion circuit using a transformer circuit was used.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来技術における増幅器の回路例を第4図に示す。図で
NMR信号を検出したプローブ44からの信号は同軸線
(通常はZo=50Ω)45を経てインピーダンス変換
回路42より高入力インピーダンスのFET等の増幅素
子41へ伝播され、信号増幅されて負荷43より出力さ
れる。このような回路において問題点はインピーダンス
変換回路42における信号伝播損失である。微小信号を
扱うような前記の回路で損失を小さくすることは一般に
難かしく N F (Noise Figure :入
出力雑音比評価指数)を劣化させる要因でもあった。
FIG. 4 shows an example of a conventional amplifier circuit. In the figure, a signal from a probe 44 that detects an NMR signal is propagated via a coaxial line (usually Zo = 50Ω) 45 to an amplifying element 41 such as a high input impedance FET from an impedance conversion circuit 42, where the signal is amplified and sent to a load 43. It is output from A problem with such a circuit is signal propagation loss in the impedance conversion circuit 42. It is generally difficult to reduce the loss in the above-mentioned circuit that handles minute signals, which is also a factor that deteriorates NF (Noise Figure: input/output noise ratio evaluation index).

〔課題を解決するための手段〕[Means to solve the problem]

本発明は従来より行なわれているインピーダンス変換回
路を用いず、FET等増幅素子を複数個並列に用いた回
路構成とする手段によるものである。
The present invention is based on a circuit configuration in which a plurality of amplifying elements such as FETs are used in parallel without using a conventional impedance conversion circuit.

〔作用〕[Effect]

NFは素子の相互コンダクタンスgm  (入力電圧V
、対出力電流i、の比g @ =l 4 / V t 
)と信号源インピーダンスRsに大きく影響される。本
発明は複数個の増幅素子を並列に用い、見かけ上の増幅
器のg、を上げてRsが低インピーダンス状態において
もNFが劣化することのないようにして前記の目的を成
したものである。
NF is the mutual conductance gm of the element (input voltage V
, to the output current i, g @ = l 4 / V t
) and the signal source impedance Rs. The present invention achieves the above object by using a plurality of amplifying elements in parallel to increase the apparent g of the amplifier so that NF does not deteriorate even when Rs is in a low impedance state.

〔実施例〕〔Example〕

本発明の理解を容易にするため背景となる回路の第5図
、第6図より説明する。第5図はFET51を信号源回
路55にコンデンサ56を通して直結した回路で、先の
第4図に示したインピーダンス変換回路42はない。信
号源55は信号源のインピーダンス(Rs)11と電圧
源(vs)12より成る。抵抗53と54はFET51
のゲートバイアス回路である。出力電圧voは負荷(R
し)52に加えられる増幅信号として取出される。第5
図の回路におけるNF関係は第6図の等価回路より説明
する。第6図で61は第5図のFET51の内部等価路
を示す。このような回路において雑音指数NFは ここで、 hl・Vl である。
In order to facilitate understanding of the present invention, the explanation will be given with reference to FIGS. 5 and 6, which are background circuits. FIG. 5 shows a circuit in which an FET 51 is directly connected to a signal source circuit 55 through a capacitor 56, and the impedance conversion circuit 42 shown in FIG. 4 is not provided. The signal source 55 consists of a signal source impedance (Rs) 11 and a voltage source (vs) 12. Resistors 53 and 54 are FET51
This is a gate bias circuit. The output voltage vo is the load (R
) 52 as an amplified signal. Fifth
The NF relationship in the circuit shown in the figure will be explained using the equivalent circuit shown in FIG. In FIG. 6, reference numeral 61 indicates an internal equivalent path of the FET 51 of FIG. In such a circuit, the noise figure NF is now hl·Vl.

(1)式より明らかなように低周波においてはglIが
、高周波においては入力キャパシタンス0162が影響
する。
As is clear from equation (1), glI influences at low frequencies, and input capacitance 0162 influences at high frequencies.

以下、本発明の実施例を第1図、第2図、第3図を用い
て説明する。第1図はF E ’I’ 1と2のゲート
とドレインを接続した並列回路である。抵抗8と9はゲ
ートバイアス用抵抗と負荷抵抗3は共通化し、ソース抵
抗4と5は個別にしてFETIと2のドレイン電流i 
111. L a2のバラツキを防いでいる。また、コ
ンデンサ6と7は抵抗4と5の高周波パスコンとして用
いる。このようにして抵抗3を流れるドレイン電流i 
a= i aI+ i ax 、みかけ上回路のga 
(g+s=g、t+g噛2;gelとg−2はFETI
、2のglI)は2倍にすることができる。第1図の等
価回路は第6図に全く同じになる。
Embodiments of the present invention will be described below with reference to FIGS. 1, 2, and 3. FIG. 1 shows a parallel circuit in which the gates and drains of F E 'I' 1 and 2 are connected. Resistors 8 and 9 are the gate bias resistor and load resistor 3 are shared, and source resistors 4 and 5 are separate and the drain current i of FETI and 2 is
111. This prevents variations in L a2. Further, capacitors 6 and 7 are used as high frequency bypass capacitors for resistors 4 and 5. In this way, the drain current i flowing through the resistor 3
a= i aI+ i ax , ga of the apparent circuit
(g+s=g, t+g bite 2; gel and g-2 are FETI
, glI of 2) can be doubled. The equivalent circuit of FIG. 1 is exactly the same as that of FIG.

第2図(a)は信号源インピーダンスRs(横軸21)
対NF(縦軸22)の特性線図である。但し1周波数f
は固定とする。図中の特性23は第5図のFETが一段
の場合、特性24は第1図のFET二段並列の場合であ
る。特性24は23を信号源インピーダンスR521の
小さい方向にほぼ並行移動したものとなる。なお、特性
の23゜24いずれもNF最小値の左側は(1)式()
内の第2項の式、左側は第3項の式による影響でNFが
高く(悪く)なるものである。続いて第2図(b)は周
波数f(横軸25)対NF(縦軸26)の特性を表わし
たものである(但し、Rsは一定。)。特性線図27は
第1図および第4図は回路に共通した傾向の特性を示し
たものである。
Figure 2(a) shows the signal source impedance Rs (horizontal axis 21)
FIG. 3 is a characteristic diagram of the NF (vertical axis 22). However, 1 frequency f
is fixed. Characteristic 23 in the figure corresponds to the case where the FET in FIG. 5 is in one stage, and characteristic 24 corresponds to the case in which the FET in FIG. 1 is in two stages in parallel. Characteristic 24 is obtained by moving 23 almost parallel to the direction in which the signal source impedance R521 is smaller. In addition, the left side of the minimum NF value for both 23° and 24 characteristics is expressed by equation (1) ()
The equation on the left side of the second term in the figure shows that the NF becomes higher (worse) due to the influence of the third term. Next, FIG. 2(b) shows the characteristics of frequency f (horizontal axis 25) versus NF (vertical axis 26) (however, Rs is constant). A characteristic diagram 27 shows characteristics that tend to be common to the circuits shown in FIGS. 1 and 4.

周波数fが高くなると(1)式()内筒2項の影響でN
Fが劣下(高くなる。)する。この場合、FETの入力
ゲート容量Ctの影響を取除けばNF特性が良くなる。
As the frequency f increases, due to the influence of the second term of the inner cylinder in equation (1), N
F deteriorates (increases). In this case, the NF characteristics will improve if the influence of the input gate capacitance Ct of the FET is removed.

第3図は2番目の本発明実施例で前記C1を入力の共振
回路の一部として用い、高周波でのNF保障を行なった
ものである。
FIG. 3 shows a second embodiment of the present invention in which C1 is used as part of an input resonant circuit to ensure NF at high frequencies.

図で、共振回路35はインダクタンス31とコンデンサ
32と33および入力ゲート容量34とで構成する。こ
のようにして、第2図(b)で特性線28のごとく所望
の高周波選択位置foでNFを保障する。
In the figure, a resonant circuit 35 includes an inductance 31, capacitors 32 and 33, and an input gate capacitance 34. In this way, NF is guaranteed at the desired high frequency selection position fo, as shown by the characteristic line 28 in FIG. 2(b).

なお、本発明の回路は一般的なF E Tを用いて説明
したが、他のJ F E T 、 G a A s F
 E T 、バイポーラ等の能動素子を用いても容易に
同様回路を構成できることはいうまでもない。
Note that although the circuit of the present invention has been explained using a general FET, other JFET, GaAsF
It goes without saying that a similar circuit can be easily constructed using active elements such as E T and bipolar.

〔発明の効果〕〔Effect of the invention〕

以上詳述した本発明によれば、低インピーダンス信号源
に対して入力に低インピーダンス変換回路を必要とせず
、また前記変換回路を用いたときのNF劣化分がなくな
るため従来困這であった低インピーダンス入力回路で低
NFの増幅、器が容易に構成することができる。
According to the present invention described in detail above, a low impedance conversion circuit is not required for input to a low impedance signal source, and NF deterioration when using the conversion circuit is eliminated. A low NF amplifier can be easily constructed using an impedance input circuit.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明実施例の基本回路図、第2図は本発明の
第1図および第3図の補足説明用NF特性図、第3図は
本発明の応用実施例を示す図、第4図は従来の回路図、
第5図は本発明に関連した補足説明回路図、第6図は第
5図の等価回路図である。 1.2・・・FET、3・・・出力負荷抵抗、4,5・
・・ソース抵抗、6,7.13・・・高周波バイパスコ
ンデンサ、8,9・・・ゲートバイアス用抵抗、10・
・・高周波信号源、31・・・共振用コイル、32.3
3・・・共振用可変コンデンサ、34・・・FETの等
価ゲート容量、35・・・共振回路。 1.1!ニー− 第1図 因 第2図 tVf)
FIG. 1 is a basic circuit diagram of an embodiment of the present invention, FIG. 2 is an NF characteristic diagram for supplementary explanation of FIGS. 1 and 3 of the present invention, and FIG. 3 is a diagram showing an applied example of the present invention. Figure 4 is the conventional circuit diagram,
FIG. 5 is a supplementary explanatory circuit diagram related to the present invention, and FIG. 6 is an equivalent circuit diagram of FIG. 5. 1.2...FET, 3...Output load resistance, 4,5...
...Source resistance, 6,7.13...High frequency bypass capacitor, 8,9...Gate bias resistor, 10.
... High frequency signal source, 31 ... Resonance coil, 32.3
3... Variable capacitor for resonance, 34... Equivalent gate capacitance of FET, 35... Resonant circuit. 1.1! Knee - Figure 1 cause Figure 2 tVf)

Claims (1)

【特許請求の範囲】 1、電界効果トランジスタ等の増幅回路素子を複数個用
いて入力端子および出力端子を共通結線した回路構成を
行なつたことを特徴としたNMR信号増幅器。 2、特許請求の範囲第1項において、複数の増幅素子の
接地電位側端子と接地間に並列である抵抗とコンデンサ
を付加した回路構成を行なつたことを特徴としたNMR
信号増幅器。 3、特許請求の範囲第2項において、入力信号源側と増
幅素子の入力端子間に対してコイルまたはコンデンサ等
を並列に付加した回路構成を行なつたことを特徴とした
NMR信号増幅器。
[Scope of Claims] 1. An NMR signal amplifier characterized in that it has a circuit configuration in which a plurality of amplifier circuit elements such as field effect transistors are used and input terminals and output terminals are commonly connected. 2. An NMR according to claim 1, characterized in that a circuit configuration is implemented in which a resistor and a capacitor are added in parallel between the ground potential side terminals of a plurality of amplifying elements and the ground.
signal amplifier. 3. The NMR signal amplifier according to claim 2, characterized in that the circuit has a circuit configuration in which a coil or a capacitor is added in parallel between the input signal source side and the input terminal of the amplifying element.
JP63212476A 1988-08-29 1988-08-29 Nmr signal amplifier Pending JPH0262104A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63212476A JPH0262104A (en) 1988-08-29 1988-08-29 Nmr signal amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63212476A JPH0262104A (en) 1988-08-29 1988-08-29 Nmr signal amplifier

Publications (1)

Publication Number Publication Date
JPH0262104A true JPH0262104A (en) 1990-03-02

Family

ID=16623277

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63212476A Pending JPH0262104A (en) 1988-08-29 1988-08-29 Nmr signal amplifier

Country Status (1)

Country Link
JP (1) JPH0262104A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008118321A (en) * 2006-11-02 2008-05-22 Renesas Technology Corp Amplifier

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008118321A (en) * 2006-11-02 2008-05-22 Renesas Technology Corp Amplifier

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