JPH0262066A - Packaging of semiconductor chip - Google Patents
Packaging of semiconductor chipInfo
- Publication number
- JPH0262066A JPH0262066A JP63213075A JP21307588A JPH0262066A JP H0262066 A JPH0262066 A JP H0262066A JP 63213075 A JP63213075 A JP 63213075A JP 21307588 A JP21307588 A JP 21307588A JP H0262066 A JPH0262066 A JP H0262066A
- Authority
- JP
- Japan
- Prior art keywords
- case
- semiconductor chip
- resin
- bump
- wiring pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 238000004806 packaging method and process Methods 0.000 title 1
- 229920005989 resin Polymers 0.000 claims abstract description 24
- 239000011347 resin Substances 0.000 claims abstract description 24
- 238000000465 moulding Methods 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 21
- 239000004840 adhesive resin Substances 0.000 claims description 18
- 229920006223 adhesive resin Polymers 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 12
- 230000002950 deficient Effects 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 239000000919 ceramic Substances 0.000 description 3
- 238000001723 curing Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000002904 solvent Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 235000014676 Phragmites communis Nutrition 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体チップを基板上に実装する半導体チップ
の実装方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor chip mounting method for mounting a semiconductor chip on a substrate.
従来の技術
半導体チップを基板上に実装する、いわゆるＣ０Ｂ（チ
ップ中オン・ボード）の従来技術を第２図〜第４図を用
いて説明する。2. Description of the Related Art A conventional technology of so-called C0B (chip on board), in which a semiconductor chip is mounted on a substrate, will be explained with reference to FIGS. 2 to 4.
第２図はワイヤーボンディングによる実装方法を示すも
のであり、この方法は半導体チップ３の下面と基板１上
の配線パターン２を導電性接着樹脂６で接着した後、基
板１上の配線パターン２と半導体チップ３の電極とをＡ
ｕやＡ１等のワイヤー４で接続し、モールド樹脂５で周
囲環境から半導体チップ３を保護するものである。FIG. 2 shows a mounting method using wire bonding. In this method, the lower surface of the semiconductor chip 3 and the wiring pattern 2 on the substrate 1 are bonded with a conductive adhesive resin 6, and then the wiring pattern 2 on the substrate 1 and the wiring pattern 2 on the substrate 1 are bonded together. A with the electrode of the semiconductor chip 3
The semiconductor chips 3 are connected by wires 4 such as U and A1, and the semiconductor chips 3 are protected from the surrounding environment by molding resin 5.
第３図はフリップチップ方式による実装方法を示すもの
であり、半田バンプ７を用いて基板１上の配線パターン
２と半導体チップ３の電極とを接続し、モールド樹脂５
で保護するものである。FIG. 3 shows a mounting method using the flip-chip method, in which the wiring pattern 2 on the substrate 1 and the electrode of the semiconductor chip 3 are connected using solder bumps 7, and the molded resin 5 is connected to the electrodes of the semiconductor chip 3.
It is protected by
第４図はＴＡＢ （テープキャリア）方式による実装方
法を示すものであり、半導体チップ３の電極上のバンブ
８とフレキシブルテープ（図示せず）のフィンガーリー
ド９の一端とを共晶により接合し、フィンガーリード９
を前記テープより切断して、半導体チップ３の裏面と基
板１上の配線パターン２を導電性樹脂６で接着した後、
前記フィンガーリード９の他端を基板１上の配線パター
ン２と半田１０で接合してモールド樹脂５で保護するも
のである。FIG. 4 shows a mounting method using the TAB (tape carrier) method, in which a bump 8 on an electrode of a semiconductor chip 3 and one end of a finger lead 9 of a flexible tape (not shown) are bonded by eutectic. finger reed 9
is cut from the tape, and the back surface of the semiconductor chip 3 and the wiring pattern 2 on the substrate 1 are bonded with a conductive resin 6.
The other end of the finger lead 9 is connected to the wiring pattern 2 on the substrate 1 with solder 10 and protected with mold resin 5.
発明が解決しようとする課題
しかし、前述の従来のＣＯＢ技術には以下の様な問題が
ある。ワイヤーボンディング方式（第２図）はウェッジ
或いはキャピラリのツールを用いるため半導体チップの
電極の大きさ、及び隣接する電極との間隔に限界があり
高集積回路チップに対応できない。フリップチップ方式
（第３図）では半田バンブ経由であるため放熱が十分で
ない。Problems to be Solved by the Invention However, the above-mentioned conventional COB technology has the following problems. Since the wire bonding method (FIG. 2) uses a wedge or capillary tool, there are limits to the size of the electrodes on the semiconductor chip and the distance between adjacent electrodes, and it cannot be applied to highly integrated circuit chips. In the flip-chip method (Fig. 3), heat radiation is not sufficient because the solder bumps are used.
ＴＡＢ方式（第４図）ではフィンガーリードとバンブの
ボンディング及びフィンガーリードと配線パターンのボ
ンディングの２回の接続を必要とし歩留まり低下の原因
となる。The TAB method (FIG. 4) requires two connections: bonding between finger leads and bumps and bonding between finger leads and wiring patterns, which causes a decrease in yield.
さらに接続後半導体チップが不良であるとき、ワイヤー
ボンディング方式とＴＡＢ方式は溶剤が半導体チップと
配線パターンの間に浸入しにくく、またフリップチップ
方式ではフラックスまたは半田が残り２回目の接続に悪
影響を及ぼし、各方式とも交換が難しい。Furthermore, if the semiconductor chip is defective after connection, the wire bonding method and TAB method prevent solvent from penetrating between the semiconductor chip and the wiring pattern, and in the flip chip method, flux or solder may remain and adversely affect the second connection. , each method is difficult to replace.
課題を解決するための手段
前記課題を解決する本発明の半導体チップの実装方法は
、バンブが形成された半導体チップの厚みより短い垂下
寸法の側部を持ち下面が開口されたケース内に半導体チ
ップをバンブがケースの開口側になるように柔軟で熱伝
導性のよい接着樹脂で接着し、ケース内に柔軟で熱伝導
性のよいモールド樹脂を充填した後、バンブと基板上の
配線パターンを位置合わせしてケースを基板側に加圧し
、バンブが配線パターンと接続したときケースの側部と
基板とを固着し、導通確認を行なった後ケース内に充填
したモールド樹脂を硬化するものである。Means for Solving the Problems A method for mounting a semiconductor chip of the present invention which solves the above-mentioned problems is to mount a semiconductor chip in a case having a side portion with a hanging dimension shorter than the thickness of the semiconductor chip in which a bump is formed and an opening at the bottom surface. Glue the bump with a flexible and thermally conductive adhesive resin so that the bump is on the open side of the case, fill the case with a flexible and thermally conductive molding resin, and then position the bump and the wiring pattern on the board. At the same time, the case is pressed against the board side, and when the bumps connect with the wiring pattern, the sides of the case and the board are fixed, and after confirming continuity, the molded resin filled inside the case is cured.
作用
本発明によれば、半導体チップに形成された回路を駆動
することにより発生する熱は熱伝導性の良いモールド樹
脂及び半導体チップをケースに接着する接着樹脂を介し
てケースより放熱することができ、更に基板の配線パタ
ーンへの接続用ボンディングを１回で行なうことができ
るので、隣接する電極との間隔が小さい高集積回路の半
導体チップを高信顆性で基板上に実装することができる
。According to the present invention, the heat generated by driving the circuit formed on the semiconductor chip can be radiated from the case through the molding resin with good thermal conductivity and the adhesive resin that adheres the semiconductor chip to the case. Further, since bonding for connection to the wiring pattern on the substrate can be performed in one step, a semiconductor chip of a highly integrated circuit with a small distance between adjacent electrodes can be mounted on the substrate with high reliability.
そして、バンブと配線パターンを接続した後、モールド
樹脂を硬化する前にケース外側の接着樹脂であらかじめ
固定してから導通確認を行なうことができるので、半導
体チップが不良の時、表面に出ているケース外側の接着
樹脂を除去することにより配線パターンにダメージを与
えることなく容易に交換することができる。After connecting the bump and the wiring pattern, you can check the continuity after fixing the bump with the adhesive resin on the outside of the case before curing the molding resin, so if the semiconductor chip is defective, it will not be exposed to the surface. By removing the adhesive resin on the outside of the case, it can be easily replaced without damaging the wiring pattern.
実施例
以下、本発明の一実施例を第１図にもとすいて説明する
。EXAMPLE An example of the present invention will be described below with reference to FIG.
半導体チップ３の厚みと半導体チップ３に形成されたと
バンブ８の厚みとを会わせた寸法より５０μｍ以上垂下
寸法の短い柱１１ａを持ち下面が開口されたセラミック
や金属などからなるケース１１内へ半導体チップ３をバ
ンブ８がケース１１の開口側になるようにして柔軟で熱
伝導性の良い接着樹脂１２で接着した後、ケース１１内
に柔軟で熱伝導性の良いモールド樹脂１４を充填する。A semiconductor is inserted into a case 11 made of ceramic, metal, etc., which has a short column 11a with a hanging dimension of 50 μm or more below the sum of the thickness of the semiconductor chip 3 and the thickness of the bump 8 formed on the semiconductor chip 3, and has an open bottom surface. After the chip 3 is bonded with a flexible and thermally conductive adhesive resin 12 with the bump 8 facing the opening side of the case 11, the case 11 is filled with a flexible and thermally conductive molding resin 14.
このようにしたものを、基板１の配線パターン２とバン
ブ８を位置合わせした後、ケース１１の加圧面ｆｌｂを
加圧して配線パターン２とバンブ８を接続し、柱１１ａ
の外側と配線パターン２を接着樹脂１３を塗布して硬化
させる。そして、導通確認を行なって半導体チップ３の
良否を判別し、問題がなければモールート樹脂１４を硬
化し、不良であれば溶剤で接着樹脂１３を除去して半導
体チップ３を交換する。この時モールド樹脂１４は接着
樹脂１３より硬化速度の遅いものや、紫外線等硬化方法
の違うものを用いるとよい。又接着樹脂１３とモールド
樹脂１４は例えばシリコーン樹脂を用い、ケース１１に
は例えばセラミックやＡＱ等の金属を用いると良い。接
着樹脂１３には代わりにはんだを用いることもできる。After aligning the wiring pattern 2 of the board 1 and the bump 8, pressurize the pressing surface flb of the case 11 to connect the wiring pattern 2 and the bump 8, and
Adhesive resin 13 is applied to the outside of the wiring pattern 2 and the wiring pattern 2 and hardened. Continuity is then checked to determine whether the semiconductor chip 3 is good or bad. If there is no problem, the moorut resin 14 is cured, and if it is defective, the adhesive resin 13 is removed with a solvent and the semiconductor chip 3 is replaced. At this time, it is preferable to use a molding resin 14 that has a slower curing speed than the adhesive resin 13 or a resin that uses a different curing method such as ultraviolet rays. Further, it is preferable that the adhesive resin 13 and the mold resin 14 are made of, for example, silicone resin, and the case 11 is made of, for example, ceramic or metal such as AQ. Solder can also be used instead of the adhesive resin 13.
このようにすることにより、半導体チップ３より発生す
る熱は柔軟で熱伝導性の良い接着樹脂１２とモールド樹
脂１４及び放熱性のよいセラミックや金属などからなる
ケース１１を介して外部に放熱することが出来、また熱
による接着樹脂１２とモールド樹脂１４からのストレス
を受けず、更にケース１１の熱膨張の影響をなくすこと
が出来る。また接着樹脂１３が表面にでているので溶剤
で容易に除去することができ、不良の半導体チップ３の
交換が容易にできる等の多大の効果がある。By doing so, the heat generated by the semiconductor chip 3 can be radiated to the outside through the adhesive resin 12 and mold resin 14, which are flexible and have good thermal conductivity, and the case 11, which is made of ceramic, metal, etc. with good heat dissipation. In addition, stress from the adhesive resin 12 and mold resin 14 due to heat is not applied, and the influence of thermal expansion of the case 11 can be eliminated. Further, since the adhesive resin 13 is exposed on the surface, it can be easily removed with a solvent, and there are many advantages such as the fact that a defective semiconductor chip 3 can be easily replaced.
発明の効果
以上述べてきたように、本発明によればバンブを蒸着と
メツキにより形成するので半導体チップの電極の大きさ
及び隣接する電極との間隔に制約を受けず、１回のボン
ディングで高信頼性に実装することができ、さらに不良
の半導体チップを容易に交換できる。Effects of the Invention As described above, according to the present invention, bumps are formed by vapor deposition and plating, so there is no restriction on the size of the electrodes of the semiconductor chip or the distance between adjacent electrodes, and high bonding can be achieved with one bonding. It can be mounted reliably, and defective semiconductor chips can be easily replaced.
第１図は本発明の一実施例における半導体チップの実装
方法を示す図、第２図は従来のワイヤーボンディング方
式による半導体チップの実装状態を示す図、第３図は従
来のフリップチップ方式における図、第４図は従来のＴ
ＡＢ方式における図である。
１拳・・基板、２・拳・配線パターン、３・・φ半導体
チップ、８・・番バンブ、１１・・・ケース、 １１ａ
φ拳・柱、 １２・・拳接着樹脂、 １３・命・接着樹
脂、１４拳拳壷モールド樹脂。FIG. 1 is a diagram showing a semiconductor chip mounting method according to an embodiment of the present invention, FIG. 2 is a diagram showing a semiconductor chip mounting state using a conventional wire bonding method, and FIG. 3 is a diagram showing a conventional flip-chip method. , Figure 4 shows the conventional T
It is a figure in AB system. 1. Board, 2. Wiring pattern, 3. φ semiconductor chip, 8. Bump, 11. Case, 11a
φFist・Pillar, 12・・Fist adhesive resin, 13・Life・Adhesive resin, 14・Fist fist pot mold resin.
Claims (3)
垂下寸法の側部を持ち下面が開口されたケース内に、前
記半導体チップを前記バンプ側が前記ケースの開口側に
なるように接着樹脂で接着し前記ケース内にモールド樹
脂を充填した後、前記バンプと基板上の配線パターンの
位置合わせを行い、前記ケースを基板側に加圧して前記
バンプを前記配線パターンと接続させ、次に前記ケース
の側部と基板とを固着するようにしたことを特徴とする
半導体チップの実装方法。(1) The semiconductor chip is bonded with an adhesive resin in a case that has an opening at the bottom and has a side part with a hanging dimension shorter than the thickness of the semiconductor chip on which bumps are formed, with the bump side facing the opening side of the case. After filling the case with mold resin, the bumps and the wiring pattern on the board are aligned, the case is pressed against the board to connect the bumps to the wiring pattern, and then the case is closed. A method for mounting a semiconductor chip, characterized in that a side portion and a substrate are fixedly attached.
れた後に硬化するものであることを特徴とする請求項１
記載の半導体チップの実装方法。(2) Claim 1, wherein the molding resin is hardened after the side part of the case and the substrate are fixed.
A method for mounting the semiconductor chip described.
いものであることを特徴とする請求項１記載の半導体チ
ップの実装方法。(3) The semiconductor chip mounting method according to claim 1, wherein the adhesive resin and the mold resin are flexible and have good thermal conductivity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63213075A JPH0262066A (en) | 1988-08-26 | 1988-08-26 | Packaging of semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63213075A JPH0262066A (en) | 1988-08-26 | 1988-08-26 | Packaging of semiconductor chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0262066A true JPH0262066A (en) | 1990-03-01 |
Family
ID=16633129
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63213075A Pending JPH0262066A (en) | 1988-08-26 | 1988-08-26 | Packaging of semiconductor chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0262066A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03290936A (en) * | 1990-03-20 | 1991-12-20 | Sharp Corp | Method of mounting semiconductor device |
-
1988
- 1988-08-26 JP JP63213075A patent/JPH0262066A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03290936A (en) * | 1990-03-20 | 1991-12-20 | Sharp Corp | Method of mounting semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5888847A (en) | Technique for mounting a semiconductor die | |
| JP3491003B2 (en) | Chip size package semiconductor | |
| US6779260B1 (en) | Overmolded electronic package including circuit-carrying substrate | |
| JP2003017518A (en) | Method for manufacturing hybrid integrated circuit device | |
| JPS63249345A (en) | Flexible mounting substrate | |
| US20040070080A1 (en) | Low cost, high performance flip chip package structure | |
| JP2001352021A (en) | Semiconductor package, mounting structure and manufacturing method therefor | |
| JPH04264758A (en) | Semiconductor chip carrier | |
| JP2000208675A (en) | Semiconductor device and its manufacture | |
| KR100674501B1 (en) | Method for attaching semiconductor chip using flip chip bonding technic | |
| JP2894594B2 (en) | Manufacturing method of know good die having solder bump | |
| JP2949969B2 (en) | Film carrier semiconductor device | |
| JP3332555B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH0262066A (en) | Packaging of semiconductor chip | |
| JP2936819B2 (en) | IC chip mounting structure | |
| JPH0964080A (en) | Semiconductor device and method of manufacturing it | |
| KR101008534B1 (en) | Power semiconductor mudule package and method for fabricating the same | |
| JP3295987B2 (en) | Method for manufacturing semiconductor device | |
| KR100565766B1 (en) | Semiconductor chip package and manufacturing method the same | |
| JPH08340164A (en) | Surface mounting structure of bga type package | |
| JPH09148482A (en) | Semiconductor device | |
| KR20070079654A (en) | Printed circuit board for flip chip bonding and ball grid array package manufacturing method using the same | |
| JPH11260945A (en) | Semiconductor device mounting structure and mounting method | |
| JP3745106B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP3127948B2 (en) | Semiconductor package and mounting method thereof |