JPH0261182B2 - - Google Patents

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a programmable logic array (PLA).
This invention relates to a method of configuring a chip, and in particular to an improvement that can significantly increase chip utilization efficiency and design freedom.

<Prior art> PLA replaces random logic with a regular structure like memory, and includes a programmable AND array section and a programmable or
or a fixed OR array section, and can generate any logical function depending on the program.

This PL is suitable for integration ratio and is a programmable read-only memory (PROM)
It can show greater flexibility compared to .

The most basic structure of PLA is the fourth
The results will be as shown in Figures A and B.

Hereinafter, for the sake of simplicity, programmable and array and programmable or array will be simply referred to as AND array and OR array, respectively.

Generally, the n input logic variables Ii (i=1, 2, 3,..., n) input to the AND array 1 are converted into 2n items by creating complements for each internally, and then converted into one Product term line Pj (j=1, 2, 3,...,
On each of the 2n logical variables, a logical product is calculated between some determined according to the planned program on each of the 2n logical variables, and the result is output to the other end of the product term line Pj.

On each product term line Pj, in order to satisfy the AND logic with only the input signal group of the above-determined combination, at each intersection of each input line Ii and the product term line Pj,
An element configuration is provided that allows selection and determination of whether to enable or disable the AND function at the intersection.

As a specific example of such a configuration, for example, as shown in FIG. 4A, for each input line Ii,
There is a configuration that selects and determines whether the AND function is enabled or disabled depending on whether the gate electrode of the NMOSFET is connected or not.

Such intersections are generally referred to as programmable intersections because the presence or absence of an AND function can be determined depending on the required program.

FIG. 4B is a simplified schematic diagram of the configuration diagram in FIG. 4A. Among the 1×2n programmable intersections in the AND array 1, the gate electrode Intersections with NMOSFETs connected to the input lines, ie programmable intersections capable of exhibiting an AND function, are indicated by the symbol ".".

Hereinafter, a programmable intersection point that can perform such an AND function will be particularly referred to as an "AND function point."

Furthermore, in the OR array 2 to be described later, among the programmable intersections, the programmable intersection programmed to perform the OR function is indicated by the symbol "X" in FIG. 4B. In particular, it is called the "OR function point".

When the programmable intersection points that perform each corresponding function are collectively designated without distinction between AND and OR, these are simply referred to as "function points."

Furthermore, as another convention, when representing the complement or inversion logic of each signal logic, the symbol "~" is added in front of the sign of the signal. Thus, for example, the complement of input logic variable Ii is denoted by ~Ii.

In the case shown in FIG. 4, for example, the logical product of the input logic variables I1 and .about.I2 appears on the product term line P1. Similarly,
The logical expressions of the product term lines P2, P3, . . . , P8 are as follows.

P2=I2・~I3, P3=I1, P4=I2・I3, P5=I3,
P6=~I1・I4, P7=~I1・I2・~I4, P8=I4 Such one product term output Pj is input to OR array 2, and m output lines Ok (k=1 ,2,3,
..., m), a predetermined combination of product term lines is logically summed, and then outputted to the outside via each output line Ok.

The functional elements at each programmable intersection in this OR array 2 also have a MNOSFEH configuration in the case shown in FIG. 4A, and each product term line Pj
Depending on whether the gate electrode is connected to or not, it is possible to disable the OR function of the other programmable intersections, leaving only the necessary locations among the m×1 programmable intersections, depending on the required program.

Now, assuming that the distribution of OR function points is as shown in Figure 4A, each output line Ok
The logic output appearing in the diagram is as follows.

O1=P2+P3=I2・～I3+I1, O2=P5+P8=I3+I4, O3=P1+P4+P6=I1・～I2+I2・I3+～I1・
I4, O4=P2+P7=I2・〜I3+〜I1・I2・〜I4 In addition, in the case of PLA as shown, the power line Vdd
, there is a load transistor between each product term line Pj.
A load transistor TOk (k=1, 2,..., I) is connected between TPj (j=1, 2, 3..., I) and each output line Ok.
3,...,m) are arranged respectively.

As an example of a conventional modification of such a basic PLA, there is also a PLA that adopts a configuration method as shown in FIG.

This was developed by International Business Machines, an American corporation, and is called "fold-dated" PLA, and the corresponding patent is U.S. Patent No. 3,987,287, 1976.

The structural feature of this folded PLA is that the AND array consists of the first and second AND array parts 1a and 1 with the OR array 2 in between.
In the first and second AND arrays, each input line can be cut at any one point as shown by the circled part Ci in Fig. It is possible to input a total of two logical variables, one from each side, without interference. Similarly, as shown enclosed by circles CO and Cm, the output line and the product term line can be placed at any one location within the OR array. Since it is possible to cut the two operation result outputs separately from both sides of the OR array, the number of input lines or the input line pair that handles a pair of complementary logical variables (complement input line pair) Even if the number of
The increase in the number of input lines or the number of complement input lines is limited to the use of the second two AND array parts 1a and 1b, and the increase in the number of input lines or the number of complement input lines in each first and second AND array part To deal with it by increasing logarithmic change, there is.

In particular, to supplement the above, a total of 6 input lines or 6 pairs of complementary input lines are shown in FIG. For each of the AND array parts 1a and 1b, three equal numbers or three pairs are generally used, and even in the case of an odd number, the input of either AND array part is used. Although the number of lines or the number of complement input line pairs is increased by one compared to the other, the number of AND array sections used remains unchanged and is limited to two.

<Problems to be Solved by the Invention> In each PLA as described above, the concept of "area" can be introduced to express the capacity.

That is, for example, in the basic PLA shown in FIG. 4, the area Sa of the AND array 1 can be defined as the number of programmable intersections inside the AND array 1, 2n×1, and similarly, OR The area So of the OR array can be defined by multiplying the number of programmable intersections in the array 2 by m×1.

Therefore, the area S of the PLA as a whole can be expressed as: S=Sa+SO=(2o _+n )1...1.

As a result of programming in accordance with a certain program, let Na be the number of AND function points that perform the AND function in AND array 1, and satisfy the OR function in OR array 2. If the number of OR function points is No, then the total number of function points is N
is naturally expressed as N=Na+NO, and thus the concept of chip utilization rate R can be defined by the above equation 1) and the following equation 2).

R=(Na+NO)/S=N/(2 _o+n )1...2 However, when such a basic PLA is generally used, under actual operating conditions, the chip utilization rate R expressed by the above two equations is is generally quite low, generally between 10% and 20%. Even worse, in this type of PLA, the chip utilization rate R tends to decrease as the capacity of the PLA, ie, the area S, increases. Therefore, in practice, large scale
I have to assume that the chip utilization rate for PLA etc. will be extremely low.

The above-mentioned folded PLA is an attempt to alleviate this poor chip utilization rate. In this folded PLA, as shown in Fig. 5, if the number of inputs, the number of product terms, and the number of outputs are the same as in the basic PLA shown in Fig. 4, the actual number of lines used for each will be the same. Since it is half the size of basic PLA, its area Sf
is Sf=(l/2){n+(m/2)}...3, so the chip utilization rate Rf is Rf≦N/(l/2){n+(m/2)}...4. Become.

Therefore, compared to basic PLA that does not perform folding, Rf/R≦4...5, as shown by the ratio of equations 2) and 4) above, and the chip utilization rate can be raised up to four times as much.

This can be explained diagrammatically as shown in the sixth figure.

For example, in the basic PLA shown in Figure 6A, the shaded areas Sa1, Sa2, Sa3,
Assuming that there are only functional points in each of Sa4, So1, So2, So3, and So4, we can introduce the configuration of the folded PLA shown in Figure 5 and find the geometrically optimal arrangement as shown in Figure 6B. If the relationship is set, the AND area portions Sa1 and Sa2 are placed in the first AND array portion 1a, and the other AND area portion Sa
3, Sa4 is combined into the second AND array part 1b, and the four OR array parts SO1, SO2,
Since SO3 and SO4 can also be contained within one OR array 2, the area as a whole is significantly reduced.

As mentioned above, this can be done by
This is because each input line, each output line, and each product term line can be cut at only one location.

In particular, as in the case shown in the figure, if complements are also included, a total of 2n input lines can be divided into groups #1 to #4 of n/2 lines, and similarly a total of m total output lines can be divided into groups #1 to #4 of n/2. Groups #1 to #4 of m/4 lines each
If we can further divide one total product term line into four groups #1 to #4, which become 1/2 by adding two total product term lines each, then we can solve the normal PLA in Figure 6A. When reconfigured into the folded PLA shown in Figure 6B, the area of the two AND arrays will be 1/4 of the original, and the area of the OR array will also be 1/4 of the original.
It becomes. In other words, the chip utilization rate has quadrupled.

As shown in FIG. 6B, this folded PLA consists of a first PLA consisting of the first AND array 1a and the output line groups #1 and #2 in the OR array 2, and Another second PLA is composed of the second AND array 1b and the output line group #3 and #4 in the OR array 2, that is, equivalently, two mutually independent PLAs.
It can also be seen as being made of PLA.

In any case, these forward-dated
As mentioned above, PLA can certainly improve chip utilization and design freedom compared to PLA that uses a basic construction method.

However, as mentioned earlier, considering that the chip utilization rate R in basic PLA is generally quite low,
The chip utilization rate improved by PLA will not be that great.

This is also due to the fact that it is not always possible to expect optimal partitioning as described above, and also because this fold-dated PLA
This is also due to the fact that the allowable number of divisions of the product term line is limited to "2".

The present invention was made precisely in view of these circumstances, and aims to provide a new PLA construction method that can further improve chip utilization and design freedom compared to the above-mentioned folded PLA.

<Means for Solving the Problems> In order to achieve the above object, the present invention sets n to a positive integer of 3 or more, m to a number O times this n, and the number O is also 1 or more. is defined as a positive integer, and then a total of n input lines or a total of n complement input line pairs carrying logic variables that are complementary to each other, and a total of m output lines are defined as a positive integer. A method of configuring a programmable logic array having only one input line or only one pair of complementary input lines, the one input line or the one pair of complementary input lines A plurality of product term lines are connected to each other through programmable intersection points, and when one input line or one pair of complement input lines is cut at one point in the middle of its length, one line is connected to each other through programmable intersection points. A programmable and array part of a unit that allows input of independent logical variables from both ends of the input line or the pair of complement input lines, and a programmable intersection point for each of the plurality of product term lines. A programmable unit that has O output lines connected through a wire, and can obtain independent logic variable outputs from both ends of each output line by cutting each of the output lines at one point in the middle of its length. Or
To construct a basic array unit from the array part; To arrange n basic array units all having the same configuration as described above on the same chip by connecting a plurality of product term lines in common. We propose a method that has the following constituent requirements: selectively cutting each of a plurality of product term lines at one or more arbitrary points;

<Operation> According to the configuration of the present invention as described above, when the required number of basic array units are arranged in parallel on a chip, each product term line that traverses the chip can be cut at any plurality of points. You will be able to do this.

Therefore, the chip utilization rate Rd of the PLA constructed according to the present invention is expressed by the following equation 6). However, to simplify the explanation, the area of the load transistor TPj is ignored.

Rd≦N/(l/L) {n+(m/2)} where L is the average value of product term line divisions; L=(total number of product term line divisions)/(total number of product term lines)
...6 Comparing the chip utilization rate Rd according to the present invention with the chip utilization rate R described above in the most basic PLA shown in Figure 4, it becomes Rd/R≦2L ...7.

As is clear from this equation, when L = 2, as seen in equation 5) above, the chip utilization rate in the folded PLA as an example of conventional chip utilization improvement shown in Fig. 5 is "4". corresponds to
When the area of the load transistor TPj is taken into consideration, the chip utilization rate is 4 or less in the method of the present invention when L=2, but as L becomes larger, the configuration of the present invention becomes much more advantageous. I'm getting old. In fact, in the PLA constructed according to the present invention, the product term line can be divided quite finely, so it can be said that as the degree of the product term increases, the effect of improving the chip utilization rate increases.

Embodiment FIGS. 1A and 1B show an example of a basic array unit 10 used in the PLA construction method of the present invention. As before, FIG. 1B is a schematic diagram in which the AND function point is shown by the symbol "." and the OR function point is shown by the symbol "X" in the programmable intersection group in a simplified manner.

The basic array unit 10 used in the present invention consists of a programmable AND array 11 and an OR array 12 which is also programmable.

First, the AND array 11 has only one input line 13a as an input line that crosses one product term line Pj, or a pair of input lines 13 carrying input logic variable signals that are complementary to each other.
It has only a, 13b.

The figure shows the latter case, that is, a configuration having a pair of input lines 13a and 13b carrying a pair of mutually complementary signals, but this is the most basic form of the basic array unit used in the present invention. Considering this, the complement signal line 13b may not be necessary in an actual logic program, so there may be only one input line as described above.

Such a single input line 13a or a pair of input lines 13 in a mutually complementary relationship
a, 13b can be cut at any one point in the middle of its length, as shown by the encircled portion Ci. How to cut it may be done by any known and existing appropriate method, as in the case of folded PLA mentioned above.
Anyway, by making it possible to disconnect in this way, each input line can be disconnected from both ends of the input line without mutual interference.
A total of two mutually independent logical variables Ii, Ii±1 can be input.

Each product term line Pj and each input line 13a or 13a,1
The programmable intersection formed by 3b may also have an appropriate configuration as in the conventional example described above, and no special modification is required in the present invention. In the case shown above,
The NMOSFEH configuration is adopted.

Each product term line Pj is connected to a load transistor TPj, which may be disconnected in some cases, as described below.
The opposite ends, that is, the output ends that output the result of the logical product, are input to the OR array 12 as they are.

The OR array 12 has O (O=0, 1, 2,
...q) It has output lines.

Although the case of O=1 is shown in Fig. 1,
When the above-mentioned basic array units are arranged in parallel with the required number and product term line in common as described later to configure a PLA, the total number of AND intersections and OR intersections required will vary depending on the logic circuit to be realized. Therefore, as a general rule, the number of output lines O is 0 as shown above.
By allowing the number to be set arbitrarily between books and q books, the degree of freedom in design can be increased.

These O output lines are connected to the AND array 11
As in , it can be cut at any point along its length as shown by the circle Co. Therefore, 2×O logical outputs can be taken out to both ends of the line. In the case shown in the first diagram, the number of output lines is O=1, so two mutually independent output signals Ok, Ok±1 are sent to both ends of the single output line.
can be output.

Note that the number of product term lines Pj is of course arbitrary, but in the illustrated case, only four from P1 to P4 are shown to simplify the explanation.

In the present invention, the above basic array unit 1
A PLA is constructed by arranging the required number of 0's in parallel with a common product term line.

In that case, as shown in FIG. 1, the basic array unit 1 can be arranged without breaking the vertical relationship of the AND array 11 at the top and the OR array 12 at the bottom.
If 0 are placed vertically in the paper,
When looking at a complete PLA chip in plan, it has two inputs and array 11-20 and an output or array 12.
-2 input AND array 11-20 output OR array 12...Simply put, AND-
It becomes a simple repeating arrangement of OR-AND-OR-.

In contrast, vertically adjacent basic arrays
If the vertical relationship of the AND array and OR array is reversed between units 10 and 10, the completed PLA chip will have two input AND arrays 11-20 and an output OR array 12-2.
A 0-output OR array 12 - 2-input AND array 11 . . . is a repeating arrangement of AND-OR-OR-AND.

In the present invention, any arrangement is acceptable, and both of the above repeating arrangements may coexist within the same chip.

FIG. 2 shows, based on the idea of the present invention, the basic array unit 10 when the number of output lines O of the OR array 12 is 1, and the AND array 11 and the OR array unit 10.
A schematic configuration of an example in which arrays 12 are arranged side by side in a repeating arrangement of and-or-or-and is shown.

In the illustrated case, 12 inputs and 12 outputs are assumed, so the number of basic array units 10 used is six.

However, if such a configuration is adopted according to the present invention, as described above, a plurality of basic array units 1
Although the product term lines 0 are commonly arranged in parallel, each product term line can be cut at any number of locations.

Therefore, for example, in the case shown in the figure, although the physical number of product term lines that actually traverse the PLA chip is only eight, by cutting the appropriate points as shown by the circle Cm, the number of product terms can be reduced. It has been expanded to 21. By the way, the previously mentioned Folded PLA
In this case, the number of divisions is limited to "2", so if there are only eight product term lines, the number of product terms can only be double that, 16. In other words, in the PLA in which the basic array units are arranged in parallel according to the present invention, the limitation on the number of product term line divisions can be removed, and the number of product term line divisions can be arbitrarily selected.
There was a huge difference in effectiveness compared to PLA.

In the case of the PLA according to the present invention, for the load transistor TPj, for each product term line P1, ..., Pj, ..., P21 divided as a result of cutting, each product term line having a function point is You only need to connect at one point each.

In order to make it easier to intuitively understand the degree of improvement in chip utilization according to the present invention, a description will be given with reference to FIG. 3 based on the case of 2n inputs, m outputs and a product term line 1.

Figure 3A shows the most basic conventional configuration shown in Figure 4 with respect to 2n inputs, m outputs, and 1 product term.
This shows the case where PLA is applied.

In the AND array 1 of this PLA, for each input line group #1, #2, ..., #6, there are AND function points only in the shaded areas Sa1, Sa2, ..., Sa6 in the figure. , at the same time or array 2
In the area, hatched areas SO1, SO2,..., regarding each output line group #1, #2,..., #6
Assuming that only SO6 has an OR function point, such a PLA can be reconfigured as shown in FIG. 3B by applying the present invention. However, in Figure 3B, for ease of understanding, the AND array section and OR section are shown.
Although the array section is divided and shown to be logically equivalent to Fig. 3A, the actual arrangement is shown in Fig. 3C.
It looks like this.

For example, in PLA1, basic array unit 1
0 is repeatedly arranged to satisfy the number of input line group #1 and the number of output line group #1, or the number of input line group #2 and the number of output line group #2, and in the same way.
Both PLA2 and PLA3 are configured.

As is apparent from FIG. 3B, according to the present invention, the length of one side required for the product term line can be set to l/L depending on the number of divisions L of the product term line. For example, in the case illustrated in Figure 3B, L = 3, so the AND array and OR array both allow input from both sides, and the area S of the entire PLA is , the conventional basic in Figure 3A
Compared to the PLA configuration, it can be reduced to 1/6,
Chip utilization can therefore be improved by a factor of six.

Furthermore, FIG. 3B also shows that the function of FIG. 3A is equivalently implemented by three independent PLAs from PLA1 to PLA3.
This also means that from a design perspective, the conventional folded PLA consists of only two independent PLAs as mentioned above, whereas the present invention's
Since the PLA can be configured with a number of PLAs corresponding to the number of divisions L of the product term line, this also means that the degree of freedom in design can be extremely high.

<Effects of the Invention> As detailed above, according to the PLA construction method of the present invention, the PLA chip utilization rate can be greatly improved, the chip area can be sufficiently reduced, and the design You can also have an extremely high degree of freedom.

In particular, such an effect results from the introduction of a configuration in which basic array units are repeatedly arranged in order to make it possible to divide the product term line at multiple locations.In other words, the number of divisions of the product term line The fact that it can be chosen arbitrarily is in itself an extremely significant effect.

That is, in conventional fold-dated PLA, etc., there was a limit to the number of divisions itself, so there was a limit to the degree to which the chip utilization rate could be improved, and these limitations remained regardless of the degree of integration. In this case, as the degree of integration increases and the number of product term line divisions increases, the chip utilization rate and area reduction ability increase, which is a truly desirable result. Furthermore, not only the degree of freedom in design but also the degree of freedom in pattern assignment according to a desired program can be extremely high.

[Brief explanation of drawings]

Figure 1 is a schematic configuration diagram of an example of a basic array unit used in the PLA configuration method of the present invention;
The figure is a schematic configuration diagram of a PLA configured according to an embodiment of the present invention, FIG. 3 is an explanatory diagram of the effects of the present invention, and FIG. 4 is a schematic configuration diagram of an example of the most basic PLA in the past. Fig. 5 is a schematic configuration diagram of a fold-dated PLA as another conventional example, and Fig. 6 is a schematic diagram of the two conventional PLA examples shown in Figs. 4 and 5.
FIG. In the figure, 10 is a basic array unit used in the present invention, 11 is a programmable and array unit,
12 is a programmable OR array, Ii is a logical variable input, Pj is a product term line, Ok is a logical output of the calculation result, and Ci, Co, and Cm are cut portions of each line.

Claims (1)

[Claims] 1 n is a positive integer of 3 or more; O is a positive integer of 1 or more; A method of configuring a programmable logic array having a total of n complementary input line pairs carrying related logic variables and a total of m output lines; It has only one complement input line pair, and a plurality of product term lines are connected to the one input line or the pair of complement input lines through programmable intersection points, respectively. When one input line or the pair of complementary input lines is cut at one point along its length, independent logic variables are generated from both ends of the input line or the pair of complement input lines. has a unit programmable and array part capable of inputting , and O output lines each connected to the plurality of product term lines via the programmable intersection points, and each of the output lines has a length of A basic array unit is composed of a programmable OR array unit that can obtain independent logical variable outputs from both ends of each output line by cutting at one point in the middle of the output line; After arranging the above-mentioned n basic array units and the above-mentioned plurality of product term lines in common on the same chip; A method for configuring a programmable logic array, characterized by: cutting at the above level.